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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com preliminary XRT86L34 quad t1/e1/j1 framer/liu combo november 2003 rev. p1.0.2 general description the XRT86L34 is a four-channel 1.544 mbit/s or 2.048 mbit/s ds1/e1/j1 framer and liu integrated solution. the XRT86L34 contains an integrated ds1/ e1/j1 framer and liu which provide ds1/e1/j1 fram- ing and error accumulation in accordance with ansi/ itu_t specifications. each framer has its own fram- ing synchronizer and transmit-receive slip buffers. the slip buffers can be independently enabled or dis- abled as required and can be configured to frame to the common ds1/e1/j1 signal formats. each framer block contains its own transmit and re- ceive t1/e1/j1 framing function. there are 3 trans- mit hdlc controllers per channel which encapsulate contents of the transmit hdlc buffers into lapd message frames. there are 3 receive hdlc control- lers per channel which extract the payload content of receive lapd message frames from the incoming t1/e1/j1 data stream and write the contents into the receive hdlc buffers. each framer also contains a transmit and overhead data input port, which per- mits data link terminal equipment direct access to the outbound t1/e1/j1 frames. likewise, a receive overhead output data port permits data link termi- nal equipment direct access to the data link bits of the inbound t1/e1/j1 frames. the XRT86L34 fully meets all of the latest t1/e1/j1 specifications: ansi t1/e1.107-1988, ansi t1/ e1.403-1995, ansi t1/e1.231-1993, ansi t1/ e1.408-1990, at&t tr 62411 (12-90) tr54016, and itu g-703, g.704, g706 and g.733, at&t pub. 43801, and ets 300 011, 300 233, jt g.703, jt g.704, jt g706, i.431. extensive test and diagnostic functions include loop-backs, boundary scan, pseu- do random bit sequence (prbs) test pattern gener- ation, performance monitor, bit error rate (ber) meter, forced error insertion, and lapd unchannel- ized data payload processing according to itu-t standard q.921. applications and features (next page) f igure 1. XRT86L34 4- channel ds1 (t1/e1/j1) f ramer /liu c ombo performance monitor prbs generator & analyser hdlc (lapd) controller & 96-byte buffer liu & loopback control dma interface signaling & alarms jtag wr ale_as rd rdy_dtack m p select a[13:0] d[7:0] microprocessor interface 4 3 tx serial clock rx serial clock 8khz sync osc back plane 1.544-16.384 mbit/s local pcm highway st-bus 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out rtip rring ttip tring external data link controller tx overhead in rx overhead out XRT86L34 1 of 4-channels tx framer llb lb 4 4 system (terminal) side line side 1:1 turns ratio 1:2 turns ratio memory intel/motorola p configuration, control & status monitor rxlos txon int
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 2 applications ? high-density t1/e1/j1 interfaces for multiplexers, switches, lan routers and digital modems ? sonet/sdh terminal or add/drop multiplexers (adms) ? t1/e1/j1 add/drop multiplexers (mux) ? channel service units (csus): t1/e1/j1 and frac- tional t1/e1/j1 ? digital access cross-connect system (dacs) ? digital cross-connect systems (dcs) ? frame relay switches and access devices (frads) ? isdn primary rate interfaces (pra) ? pbxs and pcm channel bank ? t3 channelized access concentrators and m13 mux ? wireless base stations ? atm equipment with integrated ds1 interfaces ? multichannel ds1 test equipment ? t1/e1/j1 performance monitoring ? voice over packet gateways ? routers features ? four independent, full duplex ds1 tx and rx framer/lius ? two 512-bit (two-frame) elastic store, pcm frame slip buffers (fifo) on tx and rx provide up to 8.192 mhz asynchronous back plane connections with jitter and wander attenuation ? supports input pcm and signaling data at 1.544, 2.048, 4.096 and 8.192 mbits. also supports 4- channel multiplexed 12.352/16.384 (hmvip/h.100) mbit/s on the back plane bus ? programmable output clocks for fractional t1/e1/ j1 ? supports channel associated signaling (cas) ? supports common channel signalling (ccs) ? supports isdn primary rate interface (isdn pri) signaling ? extracts and inserts robbed bit signaling (rbs) ? 3 integrated hdlc controllers per channel for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) ? hdlc controllers support ss7 ? timeslot assignable hdlc ? v5.1 or v5.2 interface ? automatic performance report generation (pmon status) can be inserted into the transmit lapd interface every 1 second or for a single transmis- sion ? alarm indication signal with customer installation signature (ais-ci) ? remote alarm indication with customer installation (rai-ci) ? gapped clock interface mode for transmit and receive. ? intel/motorola mp and mips power pc interfaces for configuration, control and status monitoring ? parallel search algorithm for fast frame synchroni- zation ? wide choice of t1 framing structures: d4, esf, slc ? 96, tidm and n-frame (non-framing) ? direct access to d and e channels for fast trans- mission of data link information ? prbs, qrss, and network loop code generation and detection ? programmable interrupt output pin ? supports programmed i/o, burst and dma modes of read-write access ? each framer block encodes and decodes the t1/ e1/j1 frame serial data ? detects and forces red (sai), yellow (rai) and blue (ais) alarms ? detects oof, lof, los errors and cofa condi- tions ? loopbacks: local (llb) and line remote (lb) ? facilitates inverse multiplexing for atm ? performance monitor with one second polling ? boundary scan (ieee 1149.1) jtag test port ? accepts external 8khz sync reference ? 3.3v cmos operation with 5v tolerant inputs ? 225-pin tbga package with C40c to +85c oper- ation
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 3 ordering information p art n umber p ackage o perating t emperature r ange XRT86L34ib 225 tape ball grid array -40 c to +85 c
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary i table of contents 1.0 microprocessor interface block ........................................................................................27 1.1 intel mode programmed i/o access (asynchronous) ............................................................... 30 1.2 motorola mode programmed i/o access (synchronous) ....................................................... 32 1.3 memory mapped i/o addressing ............................................................................................ ............. 36 1.4 description of the control registers .................................................................................... ..... 37 1.5 the interrupt structure within the framer ............................................................................ 12 2 1.6 programming the line interface unit (liu section) ................................................................ 128 2.0 hdlc controllers and lapd ............................................................................................... ...148 2.1 ds1 transmit hdlc controller block ...................................................................................... ... 148 2.2 automatic performance report (apr) ...................................................................................... ... 166 2.3 ds1 receive hdlc controller block ....................................................................................... ..... 168 2.4 ss7 (signaling system number 7) ......................................................................................... ............ 180 2.5 e1 transmit hdlc controller block ....................................................................................... ..... 180 2.6 e1 receive hdlc controller block ........................................................................................ ....... 185 3.0 overhead interface block ................................................................................................ ....189 3.1 ds1 transmit overhead input interface block ........................................................................ 189 3.2 ds1 receive overhead output interface block ...................................................................... 192 3.3 e1 overhead interface block ............................................................................................. ............. 196 3.4 e1 transmit overhead input interface block .......................................................................... 196 3.5 e1 receive overhead interface ........................................................................................... ............ 199 4.0 the e1 transmit section ................................................................................................. ..........203 4.1 the e1 transmit payload data input interface block .......................................................... 203 4.2 transmit high-speed back-plane interface .............................................................................. 2 14 4.3 e1 transmit framer block ................................................................................................ ................. 231 5.0 the ds1 transmit section ................................................................................................ ........253 5.1 the ds1 transmit payload data input interface block ....................................................... 253 5.2 transmit high-speed back-plane interface .............................................................................. 2 64 5.3 ds1 transmit framer block ............................................................................................... ............... 286 6.0 liu transmit path ....................................................................................................... .................304 6.1 transmit diagnostic features ............................................................................................ ............ 304 6.2 t1 long haul line build out (lbo) ....................................................................................... ............ 306 6.3 t1 short haul line build out (lbo) ...................................................................................... ........... 307 6.4 line termination (ttip/tring) ........................................................................................... .................. 309 7.0 the e1 receive section .................................................................................................. ............311 7.1 the receive payload data output interface block .............................................................. 311 7.2 e1 receive framer block ................................................................................................. .................. 336 8.0 the ds1 receive section ................................................................................................. ..........355 8.1 the ds1 receive payload data output interface block ...................................................... 355 8.2 ds1 receive framer block ................................................................................................ ................. 386 9.0 liu receive path ........................................................................................................ ...................398 9.1 line termination (rtip/rring) ........................................................................................... ................. 398 9.2 receive sensitivity ..................................................................................................... ........................... 400 10.0 alarms and error conditions ............................................................................................ 403 10.1 ais alarm .............................................................................................................. ................................... 403 10.2 red alarm .............................................................................................................. ................................. 405 10.3 yellow alarm ........................................................................................................... ............................ 406 10.4 bipolar violation ...................................................................................................... .......................... 408 11.0 performance monitoring (pmon) .......................................................................................410 11.1 receive line code viloation counter (16-bit) ........................................................................... 410 11.2 16-bit receive frame alignment error counter (16-bit) ...................................................... 410 11.3 receive severely errored frame counter (8-bit) ................................................................. 410 11.4 receive crc-6/4 block error counter (16-bit) ......................................................................... 4 10 11.5 receive far-end block error counter (16-bit) ....................................................................... 410 11.6 receive slip counter (8-bit) ........................................................................................... .................. 410 11.7 receive loss of frame counter (8-bit) .................................................................................. ..... 410 11.8 receive change of frame alignment counter (8-bit) ........................................................... 410
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 ii 11.9 frame check sequence error counters 1, 2, and 3 (8-bit each) ...................................... 410 11.10 prbs error counter (16-bit) ........................................................................................... .............. 410 11.11 transmit slip counter (8-bit) ......................................................................................... ............... 410 11.12 excessive zero violation counter (16-bit) ............................................................................. 411 12.0 appendix a: ds-1/e1 framing formats ............................................................................... 413 12.1 the e1 framing structure ............................................................................................... ................ 413 12.2 the e1 multi-frame structure ........................................................................................... ............ 414 12.3 the ds1 framing structure .............................................................................................. .............. 417 12.4 t1 super frame format (sf) ............................................................................................. ................ 418 12.5 t1 extended superframe format (esf) .................................................................................... ... 420 12.6 t1 data multiplexed framing format (t1dm) ............................................................................ 4 22 12.7 slc-96 format (slc-96) ................................................................................................. ....................... 423
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 4 t able 1: l ist by p in n umber p in p in n ame a1 gndpll a2 avdd a3 e1mclknout a4 mclkin a5 vss a6 trst a7 rxserclk0 a8 rxchclk0 a9 rxohclk0 a10 txmsync0 a11 txohclk0 a12 txserclk0 a13 txchnclk0 a14 txchn0_3 a15 rxser1 a16 rxchclk1 a17 rxchn1_2 a18 rxsync1 b1 vddpll b2 jtag_ring b3 agnd b4 t1mclknout b5 atest b6 tdi b7 rxlos0 b8 vdd b9 rxchn0_2 b10 rxchn0_4 b11 test b12 txchn0_0 b13 txchn0_2 b14 vss b15 rxchn1_1 b16 rxoh1 b17 rxcasync1 b18 txsync1 c1 gndpll c2 vddpll c3 jtag_tip c4 dvdd c5 dgnd c6 tms c7 tclk c8 rxcrcsync0 c9 rxchn0_1 c10 rxchn0_3 c11 rxoh0 c12 txoh0 c13 rxcrcsync1 c14 txchn0_4 c15 txchnclk1 c16 vss c17 txmsync1 c18 rxlos1 d1 gndpll d2 vddpll d3 vddpll d4 gndpll d5 tdo d6 rxser0 d7 rxchn0_0 d8 rxsync0 d9 txsync0 d10 rxcasync0 p in p in n ame d11 txser0 d12 txchn0_1 d13 rxserclk1 d14 rxchn1_0 d15 rxserclk2 d16 vdd d17 rxohclk1 d18 rxchn1_3 e1 rtip0 e2 rgnd0 e3 rvdd0 e4 ttip0 e5 analog e15 txohclk1 e16 txser1 e17 rxchn1_4 e18 txserclk1 f1 rring0 f2 tgnd0 f3 tvdd0 f4 tring0 f15 txoh1 f16 txchn1_0 f17 txchn1_1 f18 rxsync2 g1 rtip1 g2 rgnd1 g3 rvdd1 g4 ttip1 g15 rxchn2_1 g16 rxlos2 g17 txchn1_2 g18 txchn1_3 p in p in n ame h1 rring1 h2 tgnd1 h3 tvdd1 h4 tring1 h15 rxcasync2 h16 rxchn2_0 h17 rxchclk2 h18 txchn1_4 j1 rtip2 j2 rgnd2 j3 rvdd2 j4 ttip2 j15 txserclk2 j16 vdd j17 rxcrcsync2 j18 rxser2 k1 rring2 k2 tgnd2 k3 tvdd2 k4 tring2 k15 rxoh2 k16 rxchn2_4 k17 rxohclk2 k18 rxchn2_2 l1 rtip3 l2 rgnd3 l3 rvdd3 l4 ttip3 l15 txsync2 l16 rxchn2_3 l17 txmsync2 l18 txser2 m1 rring3 p in p in n ame
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 5 m2 tgnd3 m3 tvdd3 m4 tring3 m15 vss m16 vss m17 txchn2_1 m18 txchn2_0 n1 txon n2 lop n3 nc n4 8kextosc n15 txchn2_4 n16 txchn2_3 n17 txchnclk2 n18 txohclk2 p1 reset p2 e1oscclk p3 vdd p4 t1oscclk p15 txoh2 p16 rxsync3 p17 rxchnclk3 p18 rxoh3 r1 req0 r2 8ksync r3 req1 r4 vss r5 addr2 r6 addr6 r7 addr10 r8 int r9 addr11 r10 addr12 p in p in n ame r11 data7 r12 txmsync3 r13 vdd r14 txoh3 r15 vdd r16 rxohclk3 r17 rxcrcsync3 r18 rxchn3_0 t1 faddr t2 ack0 t3 rdy t4 data0 t5 vss t6 addr3 t7 addr7 t8 ptype2 t9 vdd t10 data4 t11 txchn3_4 t12 txchn3_2 t13 txchn3_0 t14 rxchn3_3 t15 rxchn3_2 t16 txchn2_2 t17 rxserclk3 t18 rxcasync3 u1 iaddr u2 ack1 u3 data1 u4 dben u5 addr0 u6 addr4 u7 vdd p in p in n ame u8 ale u9 addr9 u10 blast u11 data6 u12 txchn3_3 u13 txchn3_1 u14 rxchn3_4 u15 txsync3 u16 vss u17 rxser3 u18 rlos3 v1 pclk v2 ptype0 v3 rd v4 ptype1 v5 addr1 v6 addr5 v7 addr8 v8 data2 v9 data3 v10 data5 v11 addr13 v12 wr v13 cs v14 txser3 v15 txserclk3 v16 txohclk3 v17 txchnclk3 v18 rxchn3_1 p in p in n ame
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 6 pin descriptions transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription txser0 txser1 txser2 txser3 d11 e16 l18 v14 i transmit serial data inputtransmit framer_n: this input pin along with txserclk_n functions as the transmit serial input port for framer_n. ds1 mode: any payload data applied to this pin would be inserted into a ds1 frame and output onto the t1 line. if framer_n is configured accordingly, the framing alignment bits, the facility data link bits and the crc-6 bits can also be inserted to input pin.the signal applied to this input pin can be latched to the transmit payload data input interface on either the rising edge or the falling edge of txserclk_n according to configurations of framer_n. e1 mode: any payload data applied to this pin would be inserted into an e1 frame and output onto the e1 line. all data intended to be transported via time slots 1 through 15 and time slots 17 through 31, within each e1 frame, must be applied to this input pin. if framer_n is configured accordingly, data intended for time slots 0 and 16 can also be applied to this input pin. txserclk0 txserclk1 txserclk2 txserclk3 a12 e18 j15 v15 i or o transmit serial clock signal --transmit framer_n: this clock signal is used by the transmit payload data input interface, to latch the contents of the txser_n signal into the quad t1/e1/j1 framer ic. data that is applied at the txser_n input is latched into the transmit payload data input interface (for framer_n) on either the rising edge or the falling edge of txserclk_n depending on configurations of framer_n. txserclk_n can either be an input or an output. ds1 mode: transmit back-plane interface-1.544 mhz clock mode if txmuxen = 0 and tximode[1:0] = 00 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 1.544 mbit/s. if the transmit section of framer_n has been configured to use the txserclk_n signal as the timing source, then this signal will be an input . if the transmit section of framer_n has been configured to use either the rxlineclk_n signal or the oscclk signal as the timing source, then txserclk_n will be an output . transmit back-plane interface-high speed clock mode if txmuxen 1 0 and tximode[1:0] 1 00 in transmit interface control register, transmit back-plane interface of framer_n is operating at a high-speed mode and is taking data at rates of 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, 12.352 mbit/s or 16.384 mbit/s. the txserclk_n signal will be an input clock signal running at 1.544 mhz. e1 mode: transmit back-plane interface-2.048 mhz clock mode if txmuxen = 0 and tximode[1:0] = 00 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 2.048 mbit/s. if the transmit section of framer_n has been configured to use the txserclk_n signal as the timing source, then this signal will be an input . if the transmit section of framer_n has been configured to use either the rxlineclk_n signal or the oscclk signal as the timing source, then txserclk_n will be an output . transmit back-plane interface-high speed clock mode if txmuxen 1 0 or tximode[1:0] 1 00 in transmit interface control register, transmit back-plane interface of framer_n is operating at a high-speed mode. the txserclk_n signal will be an input clock signal running at 2.048 mhz.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 7 txsync0 txsync1 txsync2 txsync3 d9 b18 l15 u15 i or o single frame sync pulse input/outputtransmit framer_n: this pin is configured to be an input if the txserclk_n input pin is configured to be the timing reference for the transmit portion of framer_n. this pin is configured as an output if the rxlineclk_n input pin or the oscclk input pins are configured to be the timing reference for the transmit portion of framer_n. ds1 mode: when pin is configured to be an input if this pin is configured to be an input , then the user must pulse this pin "high" for one period of txserclk_n, when the transmit payload data input interface (of framer_n) is processing the first bit (f-bit) of an outbound ds1 frame. n ote : it is imperative that the txsync_n input signal be synchronized with the txserclk_n input signal. when pin is configured to be an output if this pin is configured to be an output , then it will pulse "high", for one period of txserclk_n, when the transmit payload data input interface (of framer_n) is processing the last payload bit within an outbound ds1 frame. e1 mode: when pin is configured to be an input if this pin is configured to be an input , then the user must pulse this pin "high" for one period of txserclk_n, when the transmit payload data input interface (of framer_n) is processing the international bit (si) of an outbound e1 frame. n ote : it is imperative that the txsync_n input signal be synchronized with the txserclk_n input signal. when pin is configured to be an output if this pin is configured to be an output , then it will pulse "high", for one period of txserclk_n, when the transmit payload data input interface (of framer_n) is processing the last bit within a given outbound e1 frame. transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 8 txmsync0 txmsync1 txmsync2 txmsync3 a10 c17 l17 r12 i or o multiframe sync pulse input/outputframer_n: this signal indicates the boundary of an outbound multi-frame. ds1 mode: transmit back-plane interface-1.544 mhz clock mode if txmuxen = 0 and tximode[1:0] = 00 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 1.544 mbit/s. this pin is configured to be an input if the txserclk_n input pin is con- figured to be the timing reference for the transmit section of framer_n. con- versely, this pin will be configured as an output if the rxlineclk input pin or the oscclk input pins are configured to be the timing reference for the trans- mit section of framer_n.the roles of these pins when configured as input or output, is described below. when pin is configured to be an input if this pin is configured to be an input , this pin must be pulsed "high" for one period of txserclk_n, the instant that the transmit payload data interface (of framer_n) is processing the first bit of a ds1 multi-frame. n ote : it is imperative that the txmsync_n input signal be synchronized with the txserclk_n input signal. when pin is configured to be an output if this pin is configured to be an output , then it will pulse "high", for one period of txserclk_n, when the transmit payload data input interface (of framer_n) is processing the last bit of a ds1 multi-frame. e1 mode: transmit back-plane interface-2.048 mhz clock mode if txmuxen = 0 and tximode[1:0] = 00 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 2.048 mbit/s. this pin is configured to be an input if the txserclk_n input pin is con- figured to be the timing reference for the transmit section of framer_n. con- versely, this pin will be configured as an output if the rxlineclk input pin or the oscclk input pins are configured to be the timing reference for the trans- mit section of framer_n. when pin is configured to be an input if this pin is configured to be an input, this pin must be pulsed "high" for one period of txserclk_n, the instant that the transmit payload data interface (of framer_n) is processing the first international bit (si) of an "outbound" crc payload data multiframe. n otes : 1. this pin is ignored if crc multiframe alignment has been disabled. 2. it is imperative that the txmsync_n input signal be synchronized with the txserclk_n input signal. when pin is configured to be an output if this pin is configured to be an output, then it will pulse "high", for one period of txserclk_n, when the transmit payload data input interface (of framer_n) is processing the last bit, within an "outbound" crc multi-frame. n otes : 1. this pin is inactive if crc multi-frame alignment has been disabled. 2. the purpose of this output pin is to permit the terminal equipment to maintain alignment with the "outbound" crc-multi-frame structure. transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 9 txchclk0 txchclk1 txchclk2 txchclk3 a13 c15 n17 v17 i or o transmit input clock signal -- transmit framer _n if txmuxen 1 0 or tximode[1:0] 1 00 in transmit interface control register, transmit back-plane interface of framer_n is operating at a high-speed mode. this pin will function as an input clock signal for the high-speed transmit back- plane interface. ds1 mode: transmit back-plane interface-mvip, 2.048 mhz clock mode if txmuxen = 0 and tximode[1:0] = 01 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 2.048 mbit/s. the txinclk_n signal will be an input clock signal running at 2.048 mhz. transmit back-plane interface-4.096 mhz clock mode if txmuxen = 0 and tximode[1:0] = 10 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 4.096 mbit/s. the txinclk_n signal will be an input clock signal running at 4.096 mhz. transmit back-plane interface-8.192 mhz clock mode if txmuxen = 0 and tximode[1:0] = 11 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 8.192 mbit/s. the txinclk_n signal will be an input clock signal running at 8.192 mhz. transmit back-plane interface-multiplexed at 12.352 mhz clock mode if txmuxen = 1 and tximode[1:0] = 00 in transmit interface control register, transmit back-plane interface of framer_n is taking multiplexed data at a rate of 12.352 mbit/s. txinclk_0 will be an input clock signal running at 12.352 mhz. txinclk_1, 2, 3 signals are not required. transmit payload data of chan- nel 0, 1, 2 and 3 are multiplexed and latched into transmit back-plane inter- face using clock edge of txinclk_0 via txser_0 input pin. inside the quad framer, data will be de-multiplexed into 4 channels from the serial input of channel 0. transmit back-plane interface-multiplexed at 16.384 mhz clock mode if txmuxen = 1 and tximode[1:0] = 01 in transmit interface control register, transmit back-plane interface of framer_n is taking multiplexed data at a rate of 16.384 mbit/s. txinclk_0 will be an input clock signal running at 16.384 mhz. txinclk_1, 2, 3 signals are not required. transmit payload data of chan- nel 0, 1, 2 and 3 are multiplexed and latched into transmit back-plane inter- face using clock edge of txinclk_0 via txser_0 input pin. inside the quad framer, data will be de-multiplexed into 4 channels from the serial input of channel 0. transmit back-plane interface-hmvip, 16.384 mhz clock mode if txmuxen = 1 and tximode[1:0] = 10 in transmit interface control register, transmit back-plane interface of framer_n is taking multiplexed data at a rate of 16.384 mbit/s. txinclk_0 will be an input clock signal running at 16.384 mhz. txinclk_1, 2, 3 signals are not required. transmit payload data of chan- nel 0, 1, 2 and 3 are multiplexed and latched into transmit back-plane inter- face using clock edge of txinclk_0 via txser_0 input pin. inside the quad framer, data will be de-multiplexed into 4 channels from the serial input of channel 0. transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 10 txchclkn (continued) i transmit input clock signal -- transmit framer _n (continued) transmit back-plane interface-h.100, 16.384 mhz clock mode if txmuxen = 1 and tximode[1:0] = 11 in transmit interface control register, transmit back-plane interface of framer_n is taking multiplexed data at a rate of 16.384 mbit/s. txinclk_0 will be an input clock signal running at 16.384 mhz. txinclk_1, 2, 3 signals are not required. transmit payload data of chan- nel 0, 1, 2 and 3 are multiplexed and latched into transmit back-plane inter- face using clock edge of txinclk_0 via txser_0 input pin. inside the quad framer, data will be de-multiplexed into 4 channels from the serial input of channel 0. e1 mode: transmit back-plane interface-2.048 mhz clock mode if txmuxen = 0 and tximode[1:0] = 01 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 2.048 mbit/s. the txinclk_n signal will be an input clock signal running at 2.048 mhz. transmit back-plane interface-4.096 mhz clock mode if txmuxen = 0 and tximode[1:0] = 10 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 4.096 mbit/s. the txinclk_n signal will be an input clock signal running at 4.096 mhz. transmit back-plane interface-8.192 mhz clock mode if txmuxen = 0 and tximode[1:0] = 11 in transmit interface control register, transmit back-plane interface of framer_n is taking data at a rate of 8.192 mbit/s. the txinclk_n signal will be an input clock signal running at 8.192 mhz. transmit back-plane interface-multiplexed at 16.384 mhz clock mode if txmuxen = 1 and tximode[1:0] = 01 in transmit interface control register, transmit back-plane interface of framer_n is taking multiplexed data at a rate of 16.384 mbit/s. txinclk_0 will be an input clock signal running at 16.384 mhz. txinclk_1, 2, 3 signals are not required. transmit payload data of chan- nel 0, 1, 2 and 3 are multiplexed and latched into transmit back-plane inter- face using clock edge of txinclk_0 via txser_0 input pin. inside the quad framer, data will be de-multiplexed into 4 channels from the serial input of channel 0. transmit back-plane interface-hmvip, 16.384 mhz clock mode if txmuxen = 1 and tximode[1:0] = 10 in transmit interface control register, transmit back-plane interface of framer_n is taking multiplexed data at a rate of 16.384 mbit/s. txinclk_0 will be an input clock signal running at 16.384 mhz. txinclk_1, 2, 3 signals are not required. transmit payload data of chan- nel 0, 1, 2 and 3 are multiplexed and latched into transmit back-plane inter- face using clock edge of txinclk_0 via txser_0 input pin. inside the quad framer, data will be de-multiplexed into 4 channels from the serial input of channel 0. transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 11 txchclkn (continued) i o transmit input clock signal -- transmit framer _n (continued) transmit back-plane interface-h.100, 16.384 mhz clock mode if txmuxen = 1 and tximode[1:0] = 11 in transmit interface control register, transmit back-plane interface of framer_n is taking multiplexed data at a rate of 16.384 mbit/s. txinclk_0 will be an input clock signal running at 16.384 mhz. txinclk_1, 2, 3 signals are not required. transmit payload data of chan- nel 0, 1, 2 and 3 are multiplexed and latched into transmit back-plane inter- face using clock edge of txinclk_0 via txser_0 input pin. inside the quad framer, data will be de-multiplexed into 4 channels from the serial input of channel 0. transmit channel clock output signalframer_n: this pin indicates the boundary of each time slot of an outbound ds1/e1 frame. ds1 mode: each of these output pins are a 192khz clock output which pulses "high" whenever the transmit payload data input interface block accepts the lsb of each of the 24 time slots, within the ds1 data stream, being processed via framer _n. the terminal equipment should use this clock signal to sample the txtsb0_n through txtsb4_n output signals and identify the time-slot being processed via the "transmit section" of each framer_n. if txtsb1_n pin is configured as txfrtd_n to input fractional ds1 payload data into framer_n, the txtsclk_n pin can be configured to function as one of the following: the pin will output gaped fractional ds1 clock that can be used by terminal equipment to clock out fractional ds1 payload data at rising edge of the clock. framer_n will then input fractional ds1 payload data using falling edge of the clock.otherwise, this pin will be a clock enable signal to transmit fractional ds1 input (txfrtd_n) if framer_n is configured accordingly. in this mode, fractional ds1 payload data is clocked into the chip using un-gaped txserclk_n. e1 mode: each of these output pins are a 256khz clock output which pulses "high" whenever the transmit payload data input interface block accepts the lsb of each of the 32 time slots, within the e1 data stream, being processed via framer _n. the terminal equipment should use this clock signal to sample the txtsb0_n through txtsb4_n output signals, and identify the time-slot being processed via the "transmit section" of each framer_n. if txtsb1_n pin is configured as txfrtd_n to input fractional e1 payload data into framer_n, the txtsclk_n pin can be configured to function as one of the following: the pin will output gaped fractional e1 clock that can be used by ter- minal equipment to clock out fractional e1 payload data at rising edge of the clock. framer_n will then input fractional e1 payload data using falling edge of the clock.otherwise, this pin will be a clock enable signal to transmit fractional e1 input (txfrtd_n) if framer_n is configured accordingly. in this mode, frac- tional e1 payload data is clocked into the chip using un-gaped txserclk_n. transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 12 txchn0_0 txchn1_0 txchn2_0 txchn3_0 b12 f16 m18 t13 o i transmit framer_n--time slot octet identifier output-bit [0:4]: these output signals (txtsb4_n through txtsb0_n) reflects the five-bit binary value of the number of time slot (in the incoming ds1 frame), being accepted and processed by the transmit payload data input interface block associated with framer_n. terminal equipment should use the txtsclk_n clock signal to sample the five output pins of each channel in order to identify the time-slot being processed by the transmit payload data input interface block of framer_n. transmit serial signaling input--transmit framer_n these pins can be used to input robbed-bit signaling data within an outbound ds1 frame or to input channel associated signaling (cas) bits within an out- bound e1 frame, if framer_n is configured accordingly. txchn0_1 txchn1_1 txchn2_1 txchn3_1 d12 f17 m17 u13 o i transmit framer_n--time slot octet identifier output-bit 1: these output signals (txtsb4_n through txtsb0_n) reflects the five-bit binary value of the number of time slot (in the incoming ds1 frame), being accepted and processed by the transmit payload data input interface block associated with framer_n. terminal equipment should use the txtsclk_n clock signal to sample the five output pins of each channel in order to identify the time-slot being processed by the transmit payload data input interface block of framer_n. transmit serial fractional t1/e1 input--transmit framer_n these pins can be used to input fractional ds1/e1 payload data within an out- bound ds1/e1 frame, if framer_n is configured accordingly. in this mode, ter- minal equipment will use either txtsclk_n or txserclk_n output pins to clock out fractional ds1/e1 payload data. framer_n will then use txtsclk_n or txserclk_n to clock in fractional ds1/e1 payload data. please see pin description of txtsclk_n for details. txchn0_2 txchn1_2 txchn2_2 txchn3_2 b13 g17 t16 t12 o transmit framer_n--time slot octet identifier output-bit 2: these output signals (txtsb4_n through txtsb0_n) reflects the five-bit binary value of the number of time slot (in the incoming ds1 frame) being accepted and processed by the transmit payload data input interface block associated with framer_n. terminal equipment should use the txtsclk_n clock signal to sample the five output pins of each channel in order to identify the time-slot being processed by the transmit payload data input interface block of framer_n. if txtsb1_n pin is configured as txfrtd_n to input fractional ds1 payload data into framer_n, the txtsb2_n pin will serially output the five-bit binary value of the number of the time slot being accepted and processed by the transmit payload data input interface block associated with framer_n. transmit 12.352mhz clock output-transmit framer_n: these pins can be used to output 12.352mhz clock derived from oscclk, if framer_n is configured accordingly. transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 13 txchn0_3 txchn1_3 txchn2_3 txchn3_3 a14 g18 n16 u12 o transmit framer_n-time slot octet identifier output-bit 3: these output signals (txtsb4_n through txtsb0_n) reflects the five-bit binary value of the number of time slot (in the incoming ds1 frame) being accepted and processed by the transmit payload data input interface block associated with framer_n. terminal equipment should use the txtsclk_n clock signal to sample the five output pins of each channel in order to identify the time-slot being processed by the transmit payload data input interface block of framer_n. transmit overhead synchronization pulse--transmit framer_n: these pins can be used to output overhead synchronization pulse that indi- cate the first bit of each multi-frame, if framer_n is configured accordingly. txchn0_4 txchn1_4 txchn2_4 txchn3_4 c14 h18 n15 t11 o transmit framer_n--time slot octet identifier output-bit 4: these output signals (txtsb4_n through txtsb0_n) reflects the five-bit binary value of the number of time slot (in the incoming ds1 frame) being accepted and processed by the transmit payload data input interface block associated with framer_n. terminal equipment should use the txtsclk_n clock signal to sample the five output pins of each channel in order to identify the time-slot being processed by the transmit payload data input interface block of framer_n. overhead interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription txoh0 txoh1 txoh2 txoh3 c12 f15 p15 r14 i transmit overhead inputframer_n: this input pin, along with txohclk_n functions as the transmit overhead input port for framer_n. ds1 mode: this input pin will become active if the transmit section of framer_n has been configured to use this input as the source of facility data link bits in esf fram- ing mode, fs bits in the slc96 and n framing mode, and r bit in t1dm mode. the data that is input into this pin will be inserted into the data link bits within the outbound ds1 frames at the falling edge of txohclk_n. n ote : this input pin will be disabled if framer_n is using the transmit hdlc controller, or the txser_n input as the source for the data link bits. e1 mode: this input pin will become active if the transmit section of framer_n has been configured to use this input as the source of data link bits. the data that is input into this pin will be inserted into the sa4 through sa8 bits (the national bits) within the outbound non-fas e1 frames. n ote : this input pin will be disabled if framer_n is using the transmit hdlc controller, or the txser_n input as the source for the data link bits. transmit serial data input (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 14 txohclk0 txohclk1 txohclk2 txohclk3 a11 e15 n18 v16 o transmit oh serial clock output signalframer_n: this output clock signal functions as a demand clock signal for the "transmit overhead data input interface" block associated with framer_n. ds1 mode: if the "transmit overhead data input interface" has been configured to be the source of facility data link bits in esf framing mode, fs bits in the slc96 and n framing mode, and r bit in t1dm framing mode, then the transmit overhead data input interface block will provide a clock edge for each data link bit. data link equipment, which is interfaced to this pin, should update its data (on the txoh_n line) on the rising edge of this clock signal. the transmit overhead data input interface will latch the data (on the txoh_n line) on the falling edge of this clock signal. n otes : 1. if the "transmit overhead data input interface has not been configured to be the source of the data link information, then this output signal will be inactive. 2. depending on the configurations of framer_n, the clock frequency in esf framing mode can be 2khz or 4khz in esf. e1 mode: if the "transmit overhead data input interface" has been configured to be the source of data link information, then the transmit overhead data input inter- face block will provide a clock edge for each "sa" bit that is carrying data link information. data link equipment, which is interfaced to this pin, should update its data (on the txoh_n line) on the rising edge of this clock signal. the transmit overhead data input interface will latch the data (on the txoh_n line) on the falling edge of this clock signal. n ote : if the "transmit overhead data input interface has not been configured to be the source of the data link information, then this output signal will be inac- tive. rxoh0 rxoh1 rxoh2 rxoh3 c11 b16 k15 p18 o receive overhead outputframer_n: this pin, along with rxohclk_n functions as the receive overhead output interface for framer_n. ds1 mode: this pin unconditionally outputs the contents of the facility data link bit in esf framing mode, fs bit in the slc96 and n framing mode, and r bit in t1dm framing mode. n ote : this output pin is active even if the receive hdlc controller (within framer_n) is active. e1 mode: this pin unconditionally outputs the contents of the national bits (the "sa4" through the "sa8" bits). if framer_n has been configured to interpret the national bits of the incoming e1 frames as carrying "data link" information; then the receive overhead output interface will provide a clock pulse (via the rxohclk_n output pin) for each "sa" bit carrying data link information. n ote : this output pin is active even if the receive hdlc controller (within framer_n) is active. overhead interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 15 rxohclk0 rxohclk1 rxohclk2 rxohclk3 a9 d17 k17 r16 o receive oh serial clock output signalframer_n: this pin, along with rxoh_n functions as the receive overhead output inter- face for framer_n. ds1 mode: this pin outputs a clock edge corresponding to each facility data link bit in esf framing mode, fs bit in the slc96 and n framing mode, and r bit in t1dm framing mode, which carries data link information. n otes : 1. depending on the configurations of framer_n, the clock frequency in esf framing mode can be 2khz or 4khz. 2. this output pin is inactive if the receive hdlc controller (within framer_n) has been enabled. e1 mode: this pin outputs a clock edge corresponding to each national bit that is carrying "data link" information. n ote : this output pin is inactive if the receive hdlc controller (within framer_n) has been enabled. receive serial data output (framer channel number indicated by _n) s ignal n ame p in #t ype d escription rxsync0 rxsync1 rxsync2 rxsync3 d8 a18 f18 p16 i or o single frame sync pulse input/output pinreceive framer_n: this pin is configured to be an input if the slip buffer associated with framer_n is enabled. conversely, this pin will be configured to be an output if the slip- buffer is by-passed. ds1 mode: when pin is configured to be an input if this pin is configured to be an input, then the user must pulse this pin "high" for one period of rxserclk_n, when the receive payload data output interface (of framer_n) is processing the first bit (f-bit) of an inbound ds1 frame. n ote : it is imperative that the rxsync_n input signal be synchronized with the rxserclk_n input signal. when pin is configured to be an output if this pin is configured to be an output, then it will pulse "high", for one period of rxserclk_n, when the receive payload data output interface (of framer_n) is processing the first bit (f-bit) of an inbound ds1 frame. e1 mode: when pin is configured to be an input if this pin is configured to be an input, then this pin must be pulsed "high" for one period of rxserclk_n, when the receive e1 serial (or overhead) output interface, outputs the international bit (si) of an inbound e1 frame. n ote : it is imperative that the rxsync_n input signal be synchronized with the rxserclk_n input signal. when pin is configured to be an output if this pin is configured to be an output, then it will pulse "high" for one period of rxserclk_n, when the receive e1 serial (or overhead) output interface out- puts the last bit, in an inbound e1 frame. overhead interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 16 rxcrcsync0 rxcrcsync1 rxcrcsync2 rxcrcsync3 c8 c13 j17 r17 o multiframe sync pulse output--receive framer_n: this ds1-only signal will pulse "high" for one period of rxserclk_n, the instant that the receive payload data interface (of framer_n) is processing the first bit of a ds1 multi-frame. receive "crc multiframe" sync output signal-framer_n: this e1-only signal pulses "high" for one period of rxserclk_n whenever the receive e1 output interface of framer_n outputs the first bit, within a given "crc multiframe". n ote : this output pin is inactive if crc multiframe alignment is disabled. rxserclk0 rxserclk1 rxserclk2 rxserclk3 a7 d13 d15 t17 i or o receive serial clock signalreceive framer_n: this signal is used by the receive payload data output interface, to latch the contents of the rxser_n signal out from the quad t1/e1/j1 framer ic. framer_n can use either the rising edge or the falling edge of rxserclk_n sig- nal to latch the received ds1 payload data out. depending on configurations of framer_n. rxserclk_n can either be an input or an output. ds1 mode: receive back-plane interface-1.544 mhz clock mode if rxmuxen = 0 and rximode[1:0] = 00 in receive interface control register, receive back-plane interface of framer_n is presenting data at a rate of 1.544 mbit/s. this pin is configured to be an input if the slip buffer associated with framer_n is enabled. conversely, this pin will be configured to be an output if the "slip-buffer" is "by-passed". receive back-plane interface-mvip, 2.048 mhz clock mode if rxmuxen = 0 and rximode[1:0] = 01 in receive interface control register, receive back-plane interface of framer_n is presenting data at a rate of 2.048 mbit/s. the rxserclk_n signal will be an input clock signal running at 2.048 mhz. receive back-plane interface-4.096 mhz clock mode if rxmuxen = 0 and rximode[1:0] = 10 in receive interface control register, receive back-plane interface of framer_n is presenting data at a rate of 4.096 mbit/s. the rxserclk_n signal will be an input clock signal running at 4.096 mhz. receive back-plane interface-8.192 mhz clock mode if rxmuxen = 0 and rximode[1:0] = 11 in receive interface control register, receive back-plane interface of framer_n is presenting data at a rate of 8.192 mbit/s. the rxserclk_n signal will be an input clock signal running at 8.192 mhz. receive back-plane interface-multiplexed at 12.352 mhz clock mode if rxmuxen = 1 and rximode[1:0] = 00 in receive interface control register, receive back-plane interface of framer_n is presenting multiplexed data at a rate of 12.352 mbit/s. rxserclk_0 will be an input clock signal running at 12.352 mhz. rxserclk_1, 2, 3 signals are not required. received ds1 payload data of channel 0, 1, 2 and 3 are multiplexed and latched out from receive back-plane interface using clock edge of rxserclk_0 via rxser_0 output pin. receive serial data output (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 17 rxserclkn (continued) i or o receive serial clock signalreceive framer_n: (continued) receive back-plane interface-multiplexed at 16.384 mhz clock mode if rxmuxen = 1 and rximode[1:0] = 01 in receive interface control register, receive back-plane interface of framer_n is presenting multiplexed data at a rate of 16.384 mbit/s. rxserclk_0 will be an input clock signal running at 16.384 mhz. rxserclk_1, 2, 3 signals are not required. received ds1 payload data of channel 0, 1, 2 and 3 are multiplexed and latched out from receive back-plane interface using clock edge of rxserclk_0 via rxser_0 output pin. receive back-plane interface-hmvip, 16.384 mhz clock mode if rxmuxen = 1 and rximode[1:0] = 10 in receive interface control register, receive back-plane interface of framer_n is presenting multiplexed data at a rate of 16.384 mbit/s. rxserclk_0 will be an input clock signal running at 16.384 mhz. rxserclk_1, 2, 3 signals are not required. received ds1 payload data of channel 0, 1, 2 and 3 are multiplexed and latched out from receive back-plane interface using clock edge of rxserclk_0 via rxser_0 output pin. receive back-plane interface-h.100, 16.384 mhz clock mode if rxmuxen = 1 and rximode[1:0] = 11 in receive interface control register, receive back-plane interface of framer_n is presenting multiplexed data at a rate of 16.384 mbit/s. rxserclk_0 will be an input clock signal running at 16.384 mhz. rxserclk_1, 2, 3 signals are not required. received ds1 payload data of channel 0, 1, 2 and 3 are multiplexed and latched out from receive back-plane interface using clock edge of rxserclk_0 via rxser_0 output pin. e1 mode: receive back-plane interface-2.048 mhz (xrt84v24 compatible) clock mode if rxmuxen = 0 and rximode[1:0] = 00 in receive interface control register, receive back-plane interface of framer_n is presenting data at a xrt84v24 compatible rate of 2.048 mbit/s. this pin is configured to be an input if the slip buffer associated with framer_n is enabled. conversely, this pin will be config- ured to be an output if the "slip-buffer" is "by-passed". receive back-plane interface-2.048 mhz clock mode if rxmuxen = 0 and rximode[1:0] = 01 in receive interface control register, receive back-plane interface of framer_n is presenting data at a rate of 2.048 mbit/s. the rxserclk_n signal will be an input clock signal running at 2.048 mhz. receive back-plane interface-4.096 mhz clock mode if rxmuxen = 0 and rximode[1:0] = 10 in receive interface control register, receive back-plane interface of framer_n is presenting data at a rate of 4.096 mbit/s. the rxserclk_n signal will be an input clock signal running at 4.096 mhz. receive back-plane interface-8.192 mhz clock mode if rxmuxen = 0 and rximode[1:0] = 11 in receive interface control register, receive back-plane interface of framer_n is presenting data at a rate of 8.192 mbit/s. the rxserclk_n signal will be an input clock signal running at 8.192 mhz. receive serial data output (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 18 rxserclkn (continued) i or o receive serial clock signalreceive framer_n: (continued) receive back-plane interface-multiplexed at 16.384 mhz clock mode if rxmuxen = 1 and rximode[1:0] = 01 in receive interface control register, receive back-plane interface of framer_n is presenting bit-multiplexed data at a rate of 16.384 mbit/s. rxserclk_0 will be an input clock signal running at 16.384 mhz. rxserclk_1, 2, 3 signals are not required. received ds1 payload data of channel 0, 1, 2 and 3 are multiplexed and latched out from receive back-plane interface using clock edge of rxserclk_0 via rxser_0 output pin. receive back-plane interface-hmvip, 16.384 mhz clock mode if rxmuxen = 1 and rximode[1:0] = 10 in receive interface control register, receive back-plane interface of framer_n is presenting multiplexed data at a rate of 16.384 mbit/s. rxserclk_0 will be an input clock signal running at 16.384 mhz. rxserclk_1, 2, 3 signals are not required. received ds1 payload data of channel 0, 1, 2 and 3 are multiplexed and latched out from receive back-plane interface using clock edge of rxserclk_0 via rxser_0 output pin. receive back-plane interface-h.100, 16.384 mhz clock mode if rxmuxen = 1 and rximode[1:0] = 11 in receive interface control register, receive back-plane interface of framer_n is presenting multiplexed data at a rate of 16.384 mbit/s. rxserclk_0 will be an input clock signal running at 16.384 mhz. rxserclk_1, 2, 3 signals are not required. received ds1 payload data of channel 0, 1, 2 and 3 are multiplexed and latched out from receive back-plane interface using clock edge of rxserclk_0 via rxser_0 output pin. rxser0 rxser1 rxser2 rxser3 d6 a15 j18 u17 o receive serial data outputreceive framer_n: this output pin along with rxserclk_n functions as the receive serial output port for framer_n. t1 mode: any incoming t1 line data that is received from the line will be decoded and out- put via this pin.framer_n can use either the rising edge or the falling edge of rxserclk_n input pin to latch the received t1 payload data out according to configurations of framer_n. e1 mode: much of the data that is received from the line will be decoded and output via this pin, in a binary format.all data that is transported via time slots 1 through 15 and time slots 17 through 31, within each incoming e1 frame, will be output via this pin. if framer_n is configured accordingly, the data for time slots 0 and 16 will also be output via this pin. framer_n can use either the rising edge or the falling edge of rxserclk_n input pin to latch the received ds1/e1 payload data out according to configurations of framer_n. rxchn0_0 rxchn1_0 rxchn2_0 rxchn3_0 d7 d14 h16 r18 o receive framer_n--time slot octet identifier output-bit 0: these output signals (rxtsb4_n through rxtsb0_n) reflect the five-bit binary value of the number of time slot (in the incoming ds1 frame) being received and output to the terminal equipment via the receive payload data output interface block associated with framer_n. the terminal equipment should use the rxtsclk_n clock to sample these five output pins in order to identify the time-slot being processed by the receive section of framer_n. receive serial signaling output--receive framer_n: these pins can be used to output robbed-bit signaling data extracted from an incoming ds1 frame, if framer_n is configured accordingly. receive serial data output (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 19 rxchn0_1 rxchn1_1 rxchn2_1 rxchn3_1 c9 b15 g15 v18 o receive framer_n--time slot octet identifier output-bit 1: these output signals (rxtsb4_n through rxtsb0_n) reflect the five-bit binary value of the number of time slot (in the incoming ds1 frame) being received and output to the terminal equipment via the receive payload data output interface block associated with framer_n. the terminal equipment should use the rxtsclk_n clock to sample these five output pins in order to identify the time-slot being processed by the receive section of framer_n. receive serial fractional t1/e1 input--receive framer_n: these pins can be used to output fractional ds1/e1 payload data extracted from an inbound ds1/e1 frame, if framer_n is configured accordingly. in this mode, terminal equipment will use either rising edge of rxtsclk_n or rxserclk_n to clock in fractional ds1/e1 payload data. please see pin descrip- tion of rxtsclk_n for details. rxchn0_2 rxchn1_2 rxchn2_2 rxchn3_2 b9 a17 k18 t15 o receive framer_n--time slot octet identifier output-bit 2: these output signals (rxtsb4_n through rxtsb0_n) reflect the five-bit binary value of the number of time slot (in the incoming ds1 frame) being received and output to the terminal equipment via the receive payload data output interface block associated with framer_n. the terminal equipment should use the rxtsclk_n clock to sample these five output pins in order to identify the time-slot being processed by the receive section of framer_n. receive framer_n -- time slot identifier serial output if rxtsb1_n pin is configured as rxfrtd_n to output fractional ds1 payload data from framer_n, then these pins serially output the five-bit binary value of the number of the time slot being accepted and processed by the transmit payload data input interface block associated with framer_n. rxchn0_3 rxchn1_3 rxchn2_3 rxchn3_3 c10 d18 l16 t14 o receive framer_n-time slot octet identifier output-bit 3: these output signals (rxtsb4_n through rxtsb0_n) reflect the five-bit binary value of the number of time slot (in the incoming ds1 frame) being received and output to the terminal equipment via the receive payload data output interface block associated with framer_n. the terminal equipment should use the rxtsclk_n clock to sample these five output pins in order to identify the time-slot being processed by the receive section of framer_n. receive 8khz clock-receive framer_n: these pins output a reference 8khz signal clock as if framer_n is configured accordingly. rxchn0_4 rxchn1_4 rxchn2_4 rxchn3_4 b10 e17 k16 u14 o receive framer_n--time slot octet identifier output-bit 4: these output signals (rxtsb4_n through rxtsb0_n) reflect the five-bit binary value of the number of time slot (in the incoming ds1 frame) being received and output to the terminal equipment via the receive payload data output interface block associated with framer_n. the terminal equipment should use the rxtsclk_n clock to sample these five output pins in order to identify the time-slot being processed by the receive section of framer_n. receive serial data output (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 20 rxchclk0 rxchclk1 rxchclk2 rxchclk3 a8 a16 h17 p17 o receive channel clock output signalframer_n: this pin indicates the boundary of each time slot of an inbound ds1/e1 frame. ds1 mode: each of these output pins are a 192khz clock output which pulses "high" when- ever the receive payload data output interface block outputs the lsb of each of the 24 time slots (within the inbound ds1 data stream) on the rxser_n pin. the terminal equipment should use this clock signal to sample the rxtsb0_n through rxtsb4_n output signals, and identify the time-slot being processed via the "receive section" of each framer_n. if rxtsb1_n pin is configured as rxfrtd_n to output fractional ds1 payload data from framer_n, the rxtsclk_n pin can be configured to function as one of the following: the pin will output gaped fractional ds1 clock that can be used by terminal equipment to clock out fractional ds1 payload data at rising edge of the clock. otherwise, this pin will be a clock enable signal to receive fractional ds1 out- put (rxfrtd_n) if framer_n is configured accordingly. in this mode, fractional ds1 payload data is clocked into the terminal equipment using un-gapped rxserclk_n. e1 mode: each of these output pins are a 256khz clock output which pulses "high" when- ever the receive payload data output interface block outputs the lsb of each of the 32 time slots (within the inbound e1 data stream) on the rxser_n pin. the terminal equipment should use this clock signal to sample the rxtsb0_n through rxtsb4_n output signals, and identify the time-slot being processed via the "receive section" of each framer_n. if rxtsb1_n pin is configured as rxfrtd_n to output fractional e1 payload data from framer_n, the rxtsclk_n pin can be configured to function as one of the following: the pin will output gaped fractional e1 clock that can be used by ter- minal equipment to clock out fractional e1 payload data at rising edge of the clock. otherwise, this pin will be a clock enable signal to receive fractional e1 output (rxfrtd_n) if framer_n is configured accordingly. in this mode, fractional e1 payload data is clocked into the terminal equipment using un-gaped rxserclk_n. rxcasync0 rxcasync1 rxcasync2 rxcasync3 d10 b17 h15 t18 o receive cas multiframe sync output signal--framer_n: this e1-only signal pulses "high" for one period of rxserclk_n whenever the receive e1 output interface of framer_n outputs the first bit, within a given "cas multiframe". n ote : this output pin is inactive if common channel signaling is enabled. receive line interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription rtip0 rtip1 rtip2 rtip3 e1 g1 j1 l1 i receive positive analog input rtip is the positive differential input from the line interface. along with the rring signal, these pins should be coupled to a 1:1 transformer for proper operation. receive serial data output (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 21 rring0 rring1 rring2 rring3 f1 h1 k1 m1 i receive negative analog input rring is the negative differential input from the line interface. along with the rtip signal, these pins should be coupled to a 1:1 transformer for proper opera- tion. rxlos_0 rxlos_1 rxlos_2 rxlos_3 b7 c18 g16 u18 o receive loss of signal output indicator this output pin will toggle high (declare los) if the receive block associated with channel n determines that an rlos condition occurs according to g.775. transmit line interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription ttip0 ttip1 ttip2 ttip3 e4 g4 j4 l4 o transmit positive analog output ttip is the positive differential output to the line interface. along with the tring signal, these pins should be coupled to a 1:2 step up transformer for proper operation. tring0 tring1 tring2 tring3 f4 h4 k4 m4 o transmit negative analog output tring is is the negative differential output to the line interface. along with the ttip signal, these pins should be coupled to a 1:2 step up transformer for proper operation. txon n1 i transmitter on upon power up, the transmit outputs (ttip/tring) are tri-stated. turning the transmitters on or off is selected by programming the appropriate channel reg- ister if this pin is pulled high. if the txon pin is pulled low, all 4 channels are tri-stated. n ote : internally pulled low with a 50k w resistor. timing interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription mclkin a4 i oscillator clock: this is a programmable operation clock input. this clock input can be selected by programming the appropriate global register. e1mclknout a3 o 2.048mhz output clock reference t1mclknout b4 o 1.544mhz output clock reference e1oscclk p2 i/o e1 master clock this pin is used to apply a 65.536mhz, 32.768mhz, or a 16.384mhz input clock to be used as the internal clock reference if 8kextosc is pulled high. if 8kextosc is pulled low, this pin becomes an e1 output clock. t1oscclk p4 i/o t1 master clock this pin is used to apply a 49.408mhz, 24.704mhz, or a 12.352mhz input clock to be used as the internal clock reference if 8kextosc is pulled high. if 8kextosc is pulled low, this pin becomes a t1 output clock. receive line interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 22 8ksync r2 i/o 8khz clock reference this pin accepts an 8khz clock reference when 8kextosc is pulled high. when 8kextosc is pulled low, this pin becomes an output reference of 8khz based on the mclkin input. therefore, the duty cycle of this output is determined by the time period of the input clock reference. 8kextosc n4 i external oscillator select this pin is used to select between an external or internal clock reference for t1 and e1 operation. if this pin is pulled high, pins e1oscclk and t1oscclk are used to provide the timing reference for this device. if this pin is pulled low, the device uses an external 8khz clock (applied directly to pin 8ksync, ab3) and the recovered clock from the line interface cdr. n ote : this pin is pulled low with a 50k w resistor. analog e5 o factory test mode pin note: for internal use only lop n2 i loss of power for e1 only / input pin for messaging jtag (framer channel number indicated by _n) s ignal n ame p in #t ype d escription tck c7 i test clock: boundary scan clock input. note : this input pin should be pulled low for normal operation tms c6 i test mode select: boundary scan mode select input. note : this input pin should be pulled low for normal operation tdi b6 i test data in: boundary scan test data input note : this input pin should be pulled low for normal operation tdo d5 o test data out: boundary scan test data output trst a6 i jtag test reset input test b11 i factory test mode pin note: user should tie this pin to ground atest b5 i factory test mode pin note: user should tie this pin to ground jtag_ring b2 i jtag_ring test pin jtag_tip c3 i jtag_tip test pin timing interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 23 microprocessor interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription data0 data1 data2 data3 data4 data5 data6 data7 t4 u3 v8 v9 t10 v10 u11 r11 i/o bidirectional microprocessor data bus data[7:0] is a bi-directional data bus used for read and write operations. n ote : the bi-directional data bus is used for storing and retrieving information through the dma interface if enabled. req0 req1 r1 r3 o dma cycle request outputdma controller 0 (write) : the framer asserts this output pin (toggles it "low") when at least one of the transmit hdlc buffers are empty and can receive one more hdlc message. the framer negates this output pin (toggles it high) when the hdlc buffer can no longer receive another hdlc message. dma cycle request outputdma controller 1 (read): the framer asserts this output pin (toggles it "low") when one of the receive hdlc buffer contains a complete hdlc message that needs to be read by the c/p. the framer negates this output pin (toggles it high) when the receive hdlc buffers are depleted. int r8 o interrupt request output: the framer will assert this active "low" output (toggles it "low"), to the local p, anytime it requires interrupt service. pclk v1 i microprocessor clock input: this clock signal is the microprocessor interface system clock. this clock signal is used for synchronous/burst/dma data transfer. the maximum frequency of this clock signal is 33mhz. iaddr u1 i this pin must be tied low for normal operation. faddr t1 i this pin must be tied high for normal operation. ptype0 ptype1 ptype2 v2 v4 t8 i microprocessor type input: bit 0 (lsb): this input pin, along with m ptype1 and m ptype2 permit the user to specify which type of microprocessor/microcontroller to be interfaced the framer. microprocessor type input: bit 1 microprocessor type input: bit 2 0 1 1 m ptype0 0 0 0 0 0 1 m ptype1 m ptype2 68hc11, 8051, 80c188 motorola 68k ibm power pc 403 microprocessor type
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 24 rdy t3 o ready/data transfer acknowledge output: the exact behavior of this pin depends upon which microprocessor the framer is configured to interface to: intel type microprocessors this output pin toggles "low" when the framer is ready to respond to the current pio (programmed i/o) or burst transaction. motorola type microprocessors this output pin toggles "low" when the framer has completed the current bus cycle. addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 u5 v5 r5 t6 u6 v6 r6 t7 v7 u9 r7 r9 r10 v11 i microprocessor interface address bus input bit 0 -- (lsb) a[13:0] is a direct address bus for permitting access to internal registers for read and write operations. dben u4 i data bus enable input pin . ale u8 i address latch enable input_address strobe cs v13 i microprocessor interfacechip select input: the microprocessor/microcontroller must assert this input pin (toggle it "low") in order to exchange data with the framer. note: for the 68k mpu, this signal is generated by address decode and address strobe. rd v3 i microprocessor interfaceread strobe input: the exact behavior of this pin depends upon the type of microprocessor/micro- controller the framer has been configured to interface to, as defined by the m ptype[2:0] pins. note: see pin t25 (ptype0) for the p selection table. wr v12 i microprocessor interfacewrite strobe input "low" : indicates current bus cycle is a write cycle: intel 51, 188, mips350x "high" : indicates present bus cycle is a write cycle: intel x86, i960 "low" : indicates current bus cycle is a read cycle: intel x86, i960 "high" : indicates present bus cycle is a read cycle: motorola, power pc 403 "low" : also used as write strobe in dma transfer microprocessor interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 25 ack0 ack1 t2 u2 i dma cycle acknowledge inputdma controller 0 (write): the external dma controller will assert this input pin low when the following two conditions are met: a. after the dma controller, within the framer has asserted (toggled low), the req_0 output signal. b. when the external dma controller is ready to transfer data from external memory to the selected transmit hdlc buffer. at this point, the dma transfer between the external memory and the selected transmit hdlc buffer may begin. after completion of the dma cycle, the external dma controller will negate this input pin after the dma controller within the framer has negated the req_0 out- put pin. the external dma controller must do this in order to acknowledge the end of the dma cycle. dma cycle acknowledge inputdma controller 1 (read): the external dma controller asserts this input pin low when the following two conditions are met: a. after the dma controller, within the framer has asserted (toggled "low"), the req_1 output signal. b. when the external dma controller is ready to transfer data from the selected receive hdlc buffer to external memory. at this point, the dma transfer between the selected receive hdlc buffer and the external memory may begin. after completion of the dma cycle, the external dma controller will negate this input pin after the dma controller within the framer has negated the req_1 out- put pin. the external dma controller will do this in order to acknowledge the end of the dma cycle. blast u10 i last cycle of burst indicator input: the microprocessor asserts this pin lowwhen it is performing its last read or write cycle, within a burst operation. reset p1 i hardware reset input reset is an active low input. if this pin is pulled low for more than 10 m s, the device will be reset. microprocessor interface (framer channel number indicated by _n) s ignal n ame p in #t ype d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 26 power supply pins s ignal n ame t ype d escription vdd pwr framer block power supply b8, d16, j16, p3, r13, r15, t9, u7 dvdd pwr digital power supply for liu section c4 avdd pwr analog power supply for liu section a2 rvdd pwr receiver analog power supply for liu section e3, g3, j3, l3 tvdd pwr transmitter analog power supply for liu section f3, h3, k3, m3 vddpll pwr analog power supply for pll b1, c2, d2, d3 ground pins s ignal n ame t ype d escription vss gnd framer block ground a5, b14, c16, m15, m16, r4, t5, u16 dgnd gnd digital ground for liu section c5 agnd gnd analog ground for liu section b3 rgnd gnd receiver analog ground for liu section e2, g2, j2, l2 tgnd gnd transmitter analog ground for liu section f2, h2, k2, m2 pllgnd gnd analog ground for pll a1, c1, d1, d4
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 27 1.0 microprocessor interface block the microprocessor interface section supports communication between the local microprocessor (p) and the framer/liu combo. the XRT86L34 supports an intel asynchronous interface, motorola 68k asynchronous, and a motorola power pc interface. the microprocessor interface is selected by the state of the ptype[2:0] input pins. selecting the microprocessor interface is shown in table 2. the XRT86L34 uses multipurpose pins to configure the device appropriately. the local p configures the framer/liu by writing data into specific addressable, on-chip read/write registers. the microprocessor inter- face provides the signals which are required for a general purpose microprocessor to read or write data into these registers. the microprocessor interface also supports polled and interrupt driven environments. a sim- plified block diagram of the microprocessor is shown in figure 2. 1.0.1 the microprocessor interface block signals the XRT86L34 may be configured into different operating modes and have its performance monitored by soft- ware through a standard microprocessor using data, address and control signals. these interface signals are described below in table 3, table 4, and table 5. the microprocessor interface can be configured to operate in intel mode or motorola mode. when the microprocessor interface is operating in intel mode, some of the con- trol signals function in a manner required by the intel 80xx family of microprocessors. likewise, when the mi- croprocessor interface is operating in motorola mode, then these control signals function in a manner as re- quired by the motorola power pc family of microprocessors. (for using a motorola 68k asynchronous proces- sor, see figure 5 and table 8) table 3 lists and describes those microprocessor interface signals whose role is constant across the two modes. table 4 describes the role of some of these signals when the microprocessor interface is operating in the intel mode. likewise, table 5 describes the role of these signals when the micro- processor interface is operating in the motorola mode. t able 2: s electing the m icroprocessor i nterface m ode ptype[2:0] m icroprocessor m ode 0h (000) intel 68hc11, 8051, 80c188 (asynchronous) 1h (001) motorola 68k (asynchronous) 7h (111) motorola mpc8260, mpc860 power pc (synchronous) f igure 2. s implified b lock d iagram of the m icroprocessor i nterface b lock m processor interface wr rd ale ptype [2:0] reset pclk cs addr[14:0] data[7:0] rdy int req[1:0] dben blast ack[1:0]
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 28 t able 3: XRT86L34 m icroprocessor i nterface s ignals that exhibit constant roles in both i ntel and m otorola m odes p in n ame t ype d escription ptype[2:0] i microprocessor interface mode select input pins these three pins are used to specify the microprocessor interface mode. the relationship between the state of these three input pins, and the corresponding microprocessor mode is presented in table 2. data[7:0] i/o bi-directional data bus for register "read" or "write" operations. addr[14:0] i 15-bit address bus inputs the XRT86L34 microprocessor interface uses a direct address bus. this address bus is pro- vided to permit the user to select an on-chip register for read/write access. cs i chip select input this active low signal selects the microprocessor interface of the XRT86L34 and enables read/write operations with the on-chip register locations. t able 4: i ntel mode : m icroprocessor i nterface s ignals XRT86L34 p in n ame i ntel e quivalent p in t ype d escription ale ale i address-latch enable: this active high signal is used to latch the contents on the address bus addr[14:0]. the contents of the address bus are latched into the addr[14:0] inputs on the falling edge of ale. rd rd i read signal: this active low input functions as the read signal from the local p. when this pin is pulled low (if cs is low) the XRT86L34 is informed that a read operation has been requested and begins the process of the read cycle. wr wr i write signal: this active low input functions as the write signal from the local p. when this pin is pulled low (if cs is low) the XRT86L34 is informed that a write operation has been requested and begins the process of the write cycle. rdy rdy o ready output: this active low signal is provided by the XRT86L34 device. it indicates that the current read or write cycle is complete, and the XRT86L34 is waiting for the next command.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 29 t able 5: m otorola m ode : m icroprocessor i nterface s ignals XRT86L34 p in n ame m otorola e quivalent p in t ype d escription ale ts i transfer start: this active high signal is used to latch the contents on the address bus addr[14:0]. the contents of the address bus are latched into the addr[14:0] inputs on the falling edge of ts. wr r/w i read/write: this input pin from the local p is used to inform the XRT86L34 whether a read or write operation has been requested. when this pin is pulled high, we will initiate a read operation. when this pin is pulled low, we will initiate a write operation. rd we i write enable: this active low input functions as the read or write signal from the local p dependent on the state of r/w . when we is pulled low (if cs is low) the XRT86L34 begins the read or write operation. no pin oe i output enable: this signal is not necessary for the XRT86L34 to interface to the mpc8260 or mpc860 power pcs. pclk clkout i synchronous processor clock: this signal is used as the timing reference for the power pc synchronous mode. rdy ta o transfer acknowledge: this active low signal is provided by the XRT86L34 device. it indicates that the current read or write cycle is complete, and the XRT86L34 is waiting for the next command.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 30 1.1 i ntel m ode p rogrammed i/o a ccess (a synchronous ) if the XRT86L34 is interfaced to an intel type p, then it should be configured to operate in the intel mode. intel type read and write operations are described below. intel mode read cycle whenever an intel-type p wishes to read the contents of a register, it should do the following. 1. place the address of the target register on the address bus input pins addr[14:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the XRT86L34, by toggling it "low". this action enables further communication between the p and the XRT86L34 microprocessor interface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproces- sor interface block of the XRT86L34. 4. the p should then toggle the ale pin "low". this step causes the XRT86L34 to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 5. next, the p should indicate that this current bus cycle is a read operation by toggling the rd input pin "low". this action also enables the bi-directional data bus output drivers of the XRT86L34. 6. after the p toggles the read signal "low", the XRT86L34 will toggle the rdy output pin "low". the XRT86L34 does this in order to inform the p that the data is available to be read by the p, and that it is ready for the next command. 7. after the p detects the rdy signal and has read the data, it can terminate the read cycle by toggling the rd input pin "high". n ote : ale can be tied high if this signal is not available. the intel mode write cycle whenever an intel type p wishes to write a byte or word of data into a register within the XRT86L34, it should do the following. 1. place the address of the target register on the address bus input pins addr[14:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the XRT86L34, by toggling it "low". this action enables further communication between the p and the XRT86L34 microprocessor interface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproces- sor interface block of the XRT86L34. 4. the p should then toggle the ale pin "low". this step causes the XRT86L34 to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 5. the p should then place the byte or word that it intends to write into the target register, on the bi-direc- tional data bus data[7:0]. 6. next, the p should indicate that this current bus cycle is a write operation by toggling the wr input pin "low". this action also enables the bi-directional data bus input drivers of the XRT86L34. 7. after the p toggles the write signal "low", the XRT86L34 will toggle the rdy output pin "low". the XRT86L34 does this in order to inform the p that the data has been written into the internal register loca- tion, and that it is ready for the next command. n ote : ale can be tied high if this signal is not available. the intel read and write timing diagram is shown in figure 3. the timing specifications are shown in table 6.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 31 f igure 3. i ntel p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 6: i ntel m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 65 - ns t 2 rd assert to rdy assert - 90 ns na rd pulse width (t 2 )90-ns t 3 cs falling edge to wr assert 65 - ns t 4 wr assert to rdy assert - 90 ns na wr pulse width (t 4 )90-ns cs addr[14:0] ale = 1 data[7:0] rd wr rdy valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 4 t 2 t 3 valid address valid address
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 32 1.2 m otorola m ode p rogrammed i/o a ccess (s ynchronous ) if the XRT86L34 is interfaced to a motorola type p, it should be configured to operate in the motorola mode. motorola type programmed i/o read and write operations are described below. motorola mode read cycle whenever a motorola type p wishes to read the contents of a register, it should do the following. 1. place the address of the target register on the address bus input pins addr[14:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the XRT86L34, by toggling it "low". this action enables further communication between the p and the XRT86L34 microprocessor interface block. 3. the p should then toggle the ts pin "low". this step causes the XRT86L34 to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate that this current bus cycle is a read operation by pulling the r/w input pin "high". 5. toggle the we input pin "low". this action enables the bi-directional data bus output drivers of the XRT86L34. 6. after the p toggles the we signal "low", the XRT86L34 will toggle the ta output pin "low". the XRT86L34 does this in order to inform the p that the data is available to be read by the p, and that it is ready for the next command. 7. after the p detects the ta signal and has read the data, it can terminate the read cycle by toggling the we input pin "high". motorola mode write cycle whenever a motorola type p wishes to write a byte or word of data into a register within the XRT86L34, it should do the following. 1. place the address of the target register on the address bus input pins addr[14:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the XRT86L34, by toggling it "low". this action enables further communication between the p and the XRT86L34 microprocessor interface block. 3. the p should then toggle the ts pin "low". this step causes the XRT86L34 to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate that this current bus cycle is a write operation by pulling the r/w input pin "low". 5. toggle the we input pin "low". this action enables the bi-directional data bus output drivers of the XRT86L34. 6. after the p toggles the we signal "low", the XRT86L34 will toggle the ta output pin "low". the XRT86L34 does this in order to inform the p that the data has been written into the internal register loca- tion, and that it is ready for the next command. 7. after the p detects the ta signal and has read the data, it can terminate the read cycle by toggling the we input pin "high". the motorola read and write timing diagram is shown in figure 4. the timing specifications are shown in ta b l e 7 .
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 33 f igure 4. m otorola p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 7: i ntel m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to we assert 0 - ns t 2 we assert to ta assert - 90 ns na we pulse width (t 2 )90-ns t 3 cs falling edge to ts falling edge 0 - t dc m pclk duty cycle 40 60 % t cp m pclk clock period 20 - ns cs addr[14:0] data[7:0] we r/w ta valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 valid address valid address t 3 t 3 t 1 t 2 ts upclk t cp t dc
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 34 1.2.1 dma read/write operations the XRT86L34 framer contains two dma controller interfaces which provide support for all eight framers with- in the chip. the purpose of the two dma controllers is to facilitate the rapid block transfer of data between an external memory location and the on-chip hdlc buffers via the microprocessor interface. dma-0 write dma interface dma 0 controller interface handles data transfer between external memory and the selected transmit hdlc buffer. the dma cycle starts when the XRT86L34 asserts the req 0 output pin. the external dma controller then re- sponds by asserting the ack0 input pin. the contents of the microprocessor interface bi-directional data bus are latched into the XRT86L34 each time the wr (write strobe) input pin is strobed low. the XRT86L34 ends the dma cycle by negating the dma request input (req 0) while wr is still active. the ex- ternal dma controller acknowledges the end of dma transfer by driving the ack0 input pin high. f igure 5. m otorola 68k p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 8: m otorola 68k m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to ds (pin rd _we ) assert 65 - ns t 2 ds assert to dtack assert - 90 ns na ds pulse width (t 2 )90-ns t 3 cs falling edge to as (pin ale_ts) falling edge 0 - ns cs addr[14:0] ale _ts data[7:0] rd _we wr _r/w rdy _dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 motorola asychronous mode valid address valid address t 3 t 3 t 1 t 2
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 35 f igure 6. dma m ode for the XRT86L34 and a m icroprocessor req[1:0] ack[1:0] wr rd m pclk data[7:0] microprocessor XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 36 1.3 m emory m apped i/o a ddressing t able 9: XRT86L34 f ramer /liu r egister m ap a ddress [14:0] c ontents n100h - n1ffh channel n - control register (framer block) n300h - n3ffh channel n - time slot (payload) control (framer block) n500h - n5ffh channel n - receive signaling array (framer block) n600h - n6ffh channel n - lapdn buffer 0 (framer block) n700h - n7ffh channel n - lapdn buffer 1 (framer block) n900h - n9ffh channel n - performance monitor (framer block) nb00h - nbffh channel n - interrupt generation/enable (framer block) nc00h - ndffh reserved 0f00h - 0fffh line interface control (liu block)
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 37 1.4 d escription of the c ontrol r egisters t able 10: r egister s ummary r eg #f unction s ymbol h ex m ode control registers (0xn100 - 0xn1ff) 0 clock and e1 select register (bit-6 selects e1 mode) csr 0xn100 e1 clock and t1 select register (bit-6 selects t1 mode) t1 1 line interface control register licr 0xn101 e1 line interface control register t1 2 reserved - 0xn102 - 3 reserved - 0xn103 - 4 reserved - 0xn104 - 5 reserved - 0xn105 - 6 reserved - 0xn106 - 7 framing select register fsr 0xn107 e1 framing select register fsr 0xn107 t1, j1 8 alarm generation register agr 0xn108 e1 alarm generation register t1 9 synchronization mux register smr 0xn109 e1 synchronization mux register t1 10 transmit signaling and data link select register tsdlsr 0xn10a e1 transmit signaling and data link select register tsdlsr 0xn10a t1 11 framing control register fcr 0xn10b e1 framing control register fcr 0xn10b t1 12 receive signaling & data link select register rs&dlsr 0xn10c e1 receive signaling & data link select register rs&dlsr 0xn10c t1 13 signaling change register 0 scr0 0xn10d t1/e1 14 signaling change register 1 scr1 0xn10e t1/e1 15 signaling change register 2 scr2 0xn10f t1/e1 16 signaling change register 3 scr3 0xn110 t1/e1 17 receive national bits register rnbr 0xn111 e1 18 receive extra bits register rebr 0xn112 t1/e1 19 data link control register 1 dlcr1 0xn113 t1/e1 20 transmit data link byte count register 1 tdlbcr1 0xn114 t1/e1
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 38 21 receive data link byte count register 1 rdlbcr1 0xn115 t1/e1 22 slip buffer control register sbcr 0xn116 t1/e1 23 fifo latency register fifolr 0xn117 t1/e1 24 dma 0 (write) configuration register d0wcr 0xn118 t1/e1 25 dma 1 (read) configuration register d1cr 0xn119 t1/e1 26 interrupt control register icr 0xn11a t1/e1 27 lapd select register lapdsr 0xn11b t1/e1 28 customer installation alarm generation register ciagr 0xn11c t1 29 performance report control register prcr 0xn11d t1 30 gapped clock control register gccr 0xn11e t1 31 transmit interface control register ticr 0xn120 e1 transmit interface control register t1 32 receive interface control register ricr 0xn122 e1 receive interface control register t1 33 ds1 test register: prbs control & status ds1tr 0xn123 t1 34 loopback code control register lccr 0xn124 t1/e1 35 transmit loopback code register tlcr 0xn125 t1/e1 36 receive loopback activation code register rlacr 0xn126 t1/e1 37 receive loopback deactivation code register rldcr 0xn127 t1/e1 38 transmit sa select register tsasr 0xn130 t1/e1 39 transmit sa auto control register 1 tsacr1 0xn131 t1/e1 40 transmit sa auto control register 2 tsacr2 0xn132 t1/e1 41 transmit sa4 register tsa4r 0xn133 t1/e1 42 transmit sa5 register tsa5r 0xn134 t1/e1 43 transmit sa6 register tsa6r 0xn135 t1/e1 44 transmit sa7 register tsa7r 0xn136 t1/e1 45 transmit sa8 register tsa8r 0xn137 t1/e1 46 receive sa4 register rsa4r 0xn13b t1/e1 47 receive sa5 register rsa5r 0xn13c t1/e1 48 receive sa6 register rsa6r 0xn13d t1/e1 49 receive sa7 register rsa7r 0xn13e t1/e1 50 receive sa8 register rsa8r 0xn13f t1/e1 t able 10: r egister s ummary r eg #f unction s ymbol h ex m ode
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 39 51 data link control register 2 dlcr2 0xn113 t1/e1 52 transmit data link byte count register 2 tdlbcr2 0xn114 t1/e1 53 receive data link byte count register 2 rdlbcr2 0xn115 t1/e1 54 data link control register 3 dlcr3 0xn113 t1/e1 55 transmit data link byte count register 3 tdlbcr3 0xn114 t1/e1 56 receive data link byte count register 3 rdlbcr3 0xn115 t1/e1 57 device id register devid 0xn1fe t1/e1 58 version number register revid 0xn1ff t1/e1 time slot (payload) control (0xn300 - 0xn3ff) 59-90 transmit channel control register 0-31 tccr 0-31 0xn300 to 0xn31f e1 transmit channel control register 0-31 t1 91-122 user code register 0-31 ucr0-31 0xn320 to 0xn33f t1/e1 123- 154 transmit signaling control register 0 -31 tscr0-31 0xn340 to 0xn35f e1 transmit signaling control register 0-31 t1 155- 186 receive channel control register 0-31 rccr0-31 0xn360 to 0xn37f e1 receive channel control register 0-31 t1 187- 218 receive user code register 0-31 rucr0-31 0xn380 to 0xn39f e1 receive user code register 0-31 t1 219- 250 receive signaling control register 0-31 rscr0-31 0xn3a0 to 0xn3bf t1/e1 251- 282 receive substitution signaling register 0-31 rssr0-31 0xn3c0 to 0xn3df e1 receive substitution signaling register 0-24 rssr0-24 t1 receive signaling array (0xn500 - 0xn51f) 283- 314 receive signaling array register 0 rsar0-31 0xn500 to 0xn51f t1/e1 t able 10: r egister s ummary r eg #f unction s ymbol h ex m ode
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 40 lapdn buffer 0 (0xn600 - 0xn660) 315- 410 lapd buffer 0 control register lapdbcr0 0xn600 to 0xn660 t1/e1 lapdn buffer 1 (0xn700 - 0xn760) 411- 506 lapd buffer 1 control register lapdbcr1 0xn700 to 0xn760 t1/e1 performance monitor 507 t1/e1 receive line code violation counter: msb t1/e1 rlcvcl 0xn900 t1/e1 508 t1/e1 receive line code violation counter: lsb t1/e1 rlcvcu 0xn901 t1/e1 509 t1/e1 receive frame alignment error counter: lsb t1/e1 rfbecu 0xn902 t1/e1 510 t1/e1 receive frame alignment error counter: lsb t1/e1 rfaecl 0xn903 t1/e1 511 t1/e1 receive severely errored frame counter: msb t1/e1rsefc 0xn904 t1/e1 512 t1/e1 receive synchronization bit (crc-6 (t1) crc-4 (e1) block) error counter: msb t1/e1 rsbec 0xn905 t1/e1 513 t1/e1 receive far-end block error counter: msb t1/e1 rfebecu 0xn907 t1/e1 514 pmon e1 receive far-end block error counter -msb pe1rfebec 0xn908 e1 515 t1/e1 receive far-end block error counter: lsb p t1/e1 rfebecl 0xn908 t1/e1 516 t1/e1 receive slip counter t1/e1rsr 0xn909 t1/e1 517 t1/e1 receive loss of frame counter t1/e1 rlovc 0xn90a t1/e1 518 t1/e1 receive change of frame alignment counter t1/e1 rcoac 0xn90b t1/e1 519 lapd frame check sequence error counter lfcsec 0xn90c t1/e1 520 t1/e1 prbs bit error counter: msb p t1/e1 pbecu 0xn90d t1/e1 521 t1/e1 prbs bit error counter: lsb p t1/e1 pbecl 0xn90e t1/e1 522 t1/e1 transmit slip counter t1/e1rsr 0xn90f t1/e1 interrupt generation/enable register address map (0xnb00 - 0xnb41) 523 block interrupt status register bisr 0xnb00 t1/e1 524 block interrupt enable register bier 0xnb01 t1/e1 525 alarm & error interrupt status register aesr 0xnb02 t1/e1 526 alarm & error interrupt enable register aeier 0xnb03 e1 alarm & error interrupt enable register t1 527 framer interrupt status register fisr 0xnb04 e1 framer interrupt status register t1 t able 10: r egister s ummary r eg #f unction s ymbol h ex m ode
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 41 528 framer interrupt enable register fier 0xnb05 e1 framer interrupt enable register t1 529 data link status register 1 dlsr1 0xnb06 t1/e1 530 data link interrupt enable register 1 dlier1 0xnb07 t1/e1 531 slip buffer interrupt enable register sbier 0xnb08 t1/e1 532 slip buffer interrupt status register sbisr 0xnb09 t1/e1 533 receive loopback code interrupt and status register rlcisr 0xnb0a t1/e1 534 receive loopback code interrupt enable register rlcier 0xnb0b t1/e1 535 receive sa (sa6) interrupt register rsair 0xnb0c t1/e1 536 receive sa (sa6) interrupt enable register rsaier 0xnb0d t1/e1 537 excessive zero status register exzsr 0xnb0e t1/e1 538 excessive zero enable register exzer 0xnb0f t1/e1 539 ss7 status register for lapd 1 ss7sr1 0xnb10 t1 540 ss7 enable register for lapd 1 ss7er1 0xnb11 t1 541 data link status register 2 dlsr2 0xnb16 t1/e1 542 data link interrupt enable register 2 dlier2 0xnb17 t1/e1 543 ss7 status register for lapd 2 ss7sr2 0xnb18 t1 544 ss7 enable register for lapd 2 ss7er2 0xnb19 t1 545 data link status register 3 dlsr3 0xnb26 t1/e1 546 data link interrupt enable register 3 dlier3 0xnb27 t1/e1 547 ss7 status register for lapd 3 ss7sr3 0xnb28 t1 548 ss7 enable register for lapd 3 ss7er3 0xnb29 t1 549 customer installation alarm status register ciasr 0xnb40 t1 550 customer installation alarm interrupt enable register ciaier 0xnb41 t1 liu register summary 551 to 566 channel 0 liu control register - 0x0f00 to 0x0f0f - t able 10: r egister s ummary r eg #f unction s ymbol h ex m ode
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 42 567 to 582 channel 1 liu control register - 0x0f10 to 0x0f1f - 583 to 598 channel 2 liu control register - 0x0f20 to 0x0f2f - 599 to 614 channel 3 liu control register - 0x0f30 to 0x0f3f - 615 to 630 reserved - 0x0f40 to 0x0f4f - 631 to 646 reserved - 0x0f50 to 0x0f5f - 647 to 662 reserved - 0x0f60 to 0x0f6f - 663 to 678 reserved - 0x0f70 to 0x0f7f - 679 to 694 reserved - 0x0f80 to 0x0fdf - 695 to 710 liu command control registers - 0x0fe0 to 0x0fe9 - 711 to 726 reserved - 0x0fea to 0x0fff - t able 10: r egister s ummary r eg #f unction s ymbol h ex m ode
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 43 1.4.1 register descriptions t able 11: c lock s elect r egister e1 m ode r egister 0 - e1 m ode c lock s elect r egister (csr) h ex a ddress : 0 x n100 b it f unction t ype d efault d escription -o peration 7 bpvi r/w 0 bipolar violation insertion this bit forces the bpv on transmit. 0 = no bpv is inserted on transmit encoder. 1 = bpv is inserted on transmit encoder once. a 0 to 1 transition will cause a bpv inserted in the non-bpv data 6 ist1 r/w 1 t1/e1 mode select this bit is used to program the chip to either t1 or e1 mode. 1 =t1 mode 0 =e1 mode. 5 8khz r/w 0 8khz sync enable this read/write bit-field allows the user to configure the transmit sections of all eight framer blocks to synchronize their frame alignment with the signal applied to the 8kref input pin. setting this bit-field to a 1 enables this feature for all eight channels. n ote : this bit-field is ignored if txserclk_n or rxlineclk_n is configured to be the timing reference for the transmit section. 4 cldet r/w 0 clock loss detect enable/disable select enables a protection feature for the framer whenever the recovered received line clock (rxlineclk) is used as the timing source for the transmit section of the framer. if the clock loss detection protection feature is enabled and the recovered received line clock is used as the timing source, then if the liu somehow loses clock recovery the clock distribution block will detect this occurrence and automatically begin to use the oscclk driven divided clock as the transmitter source, until the liu is able to regain clock recovery. 3 cfs(1) r/w 0 frequency select specifies the frequency of the oscillator clock. 00 = the oscclk input is 16.384 mhz (internally divided by 1) 01 = the oscclk input is 32.768 mhz (internally divided by 2) 10 = the oscclk input is 65.536 mhz (internally divided by 4) 11 = reserved n ote : this bit-field is ignored if txserclk_n or rxlineclk_n is configured to be the timing reference for the transmit section. 2 cfs(0) r/w 0 1 css(1) r/w 0 clock source select specifies the timing source for the transmit e1 framer block (associated with this register). 00 = rxlineclk - the recovered received channel input clock is chosen as the timing reference for the transmit section of framer n (loop timing) 01 = txserclk - the transmit serial data input clock is chosen as the timing reference for the timing source for the transmit section of framer n. 10 = oscclk - the oscclk-driven divided clock is chosen as the timing refer- ence for the transmit section of framer n. 11 = rxlineclk - the recovered received channel input clock is chosen as the timing reference for the transmit section of framer n. 0 css(0) r/w 1
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 44 t able 12: c lock s elect r egister - t1 m ode r egister 0 -t1 m ode c lock s elect r egister (csr) h ex a ddress : 0 x n100 b it f unction t ype d efault d escription -o peration 7 bpvi r/w 0 bipolar violation insertion this bit forces the bpv on transmit. 0 = no bpv is inserted on transmit encoder. 1 = bpv is inserted on transmit encoder once. a 0 to 1 transition will cause a bpv inserted in the non-bpv data 6 ist1 r/w 1 t1/e1 mode select this bit is used to program the chip to either t1 or e1 mode. 1 =t1 mode 0 =e1 mode. 5 8khz r/w 0 8khz sync enable this read/write bit-field allows the user to configure the transmit sections of all eight framer blocks to synchronize their frame alignment with the signal applied to the 8kref input pin. setting this bit-field to a 1 enables this feature for all eight channels. n ote : this bit-field is ignored if txserclk_n or rxlineclk_n is configured to be the timing reference for the transmit section. 4 cldet r/w 0 clock loss detect enable/disable select 1 = enables a protection feature for the framer whenever the recovered received line clock (rxlineclk) is used as the timing source for the transmit section of the framer. if the clock loss detection protection feature is enabled and the recovered received line clock is used as the timing source, then if the liu somehow loses clock recovery the clock distribution block will detect this occurrence and automatically begin to use the oscclk driven divided clock as the transmitter source, until the liu is able to regain clock recovery. 0 = disables protection feature. 3 cfs(1) r/w 0 frequency select t1 mode specifies the frequency of the oscillator clock. 00 = the oscclk input is 12.352 mhz (internally divided by 1) 01 = the oscclk input is 24.704 mhz (internally divided by 2) 10 = the oscclk input is 49.408 mhz (internally divided by 4) 11 = reserved n ote : this bit-field is ignored if txserclk_n or rxlineclk_n is configured to be the timing reference for the transmit section. 2 cfs(0) r/w 0 1 css(1) r/w 0 clock source select specifies the timing source for the transmit e1 framer block (associated with this register). 00 = rxlineclk - the recovered received channel input clock is chosen as the timing reference for the transmit section of framer n (loop timing) 01 = txserclk - the transmit serial data input clock is chosen as the timing reference for the timing source for the transmit section of framer n. 10 = oscclk - the oscclk-driven divided clock is chosen as the timing refer- ence for the transmit section of framer n. 11 = rxlineclk - the recovered received channel input clock is chosen as the timing reference for the transmit section of framer n. 0 css(0) r/w 1
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 45 t able 13: l ine i nterface c ontrol r egister e1 m ode r egister 1 - e1 m ode l ine i nterface c ontrol r egister (licr) h ex a ddress : 0 x n101 b it f unction t ype d efault d escription -o peration 7 force_los r/w 0 force transmit los this bit forces transmitter to emulate los outputs. 0 = no los is generated. 1 = los is transmitted on the line outputs. 6 reserved r/w 0 reserved 5 lb(1) r/w 0 loopback selection these two read/write bit-fields are used to configure a given channel to oper- ate in any of the following loop-back modes 00 = no local loopback 01 = local loopback 10 = remote line loopback 11 = reserved 4 lb(0) r/w 0 3 reserved r/w 0 reserved 2 reserved r/w 0 reserved 1 encode ami/hdb3 r/w 0 encode ami/hdb3 line code select configures the transmit liu interface block to transmit data via the ami or hdb3 line codes. 0 = transmit liu interface block transmits the e1 frame data in the hdb3 line code. 1 = transmit liu interface block transmits the e1 frame data in the ami line code. 0 decode ami/hdb3 r/w 0 decode ami/hdb3 line code select enables or disables the hdb3 decoder with in the receive liu interface block. 0 = enables the hdb3 decoder 1 = disables the hdb3 decoder
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 46 t able 14: l ine i nterface c ontrol r egister t1 m ode r egister 1 - t1 m ode l ine i nterface c ontrol r egister (licr) h ex a ddress : 0 x n101 b it f unction t ype d efault d escription -o peration 7 force_los r/w 0 force transmit los this bit forces transmitter to emulate los outputs. 0 = no los is generated. 1 = los is transmitted on the line outputs. 6 reserved - - reserved 5 lb(1) r/w 0 loopback selection these two read/write bit-fields are used to configure a given channel to oper- ate in any of the following loop-back modes 00 = no local loopback 01 = local loopback 10 = remote line loopback 11 = reserved 4 lb(0) r/w 0 3 reserved r/w 0 reserved 2 reserved r/w 0 reserved 1 encode ami/b8zs r/w 0 encode ami/b8zs line code select configures the transmit liu interface block to transmit data via the ami or b8zs line codes. 0 = transmit liu interface block transmits the t1 frame data in the b8zs line code. 1 = transmit liu interface block transmits the t1 frame data in the ami line code. 0 decode ami/b8zs r/w 0 decode ami/b8zs line code select enables or disables the hdb3 decoder with in the receive liu interface block. 0 = enables the b8zs decoder 1 = disables the b8zs decoder
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 47 t able 15: f raming s elect r egister -e1 m ode r egister 7- e1 m ode f raming s elect r egister (fsr) h ex a ddress : 0 x n107 b it f unction t ype d efault d escription -o peration 7 e1 modenb r/w 0 annex b enable this bit forces framing synchronizer to to be compliant with itu-t g.706 annex b for crc-to-non-crc interworking detection. 0 = normal operation. 1 = annex b is enabled. 6 e1 crcdiag r/w 0 crc diagnostics select enable/disable this read/write bit-field is used to force an errored crc pattern in the out- bound crc multiframe to be sent on the transmission line. the transmit sec- tion will implement this error by inverting the value of crc bit (c1) 0 = transmit e1 framer functions normally (no errors) 1 = transmits errored crc bit n ote : this bit-field is ignored if crc multi-framing is disabled. 5 e1 cassel(1) r/w 0 cas multiframe alignment algorithm select allows the user to select which cas multiframe alignment algorithm to employ. 00 = cas multiframe alignment disabled 01 = cas multiframe alignment algorithm 1 enabled 10 = cas multiframe alignment algorithm 2 (g.732) enabled 11 = cas multiframe alignment disabled 4 e1 cassel(0) r/w 0 3 e1 crcsel(1) r/w 0 crc multiframe alignment criteria select allows the user to select which crc-multiframe alignment to employ. 00 = crc multiframe alignment disabled 01 = crc multiframe alignment enabled. alignment is declared if at least one valid crc multiframe alignment signal (0,0,1,0,1,1,e1,e2) is observed within 8ms. 10 = crc multiframe alignment enabled. alignment is declared if at least two valid crc multiframe alignment signals (0,0,1,0,1,1,e1,e2) are observed within 8ms with the time separating the two alignment signals being multiples of 2ms. 11:crc multiframe alignment enabled. alignment is declared if at least 3 valid crc multiframe alignment signals (0,0,1,0,1,1,e1,e2) are observed within 8ms with the time separating the two alignment signals being multiples of 2ms. 2 e1 crcsel(0) r/w 0 1 e1 ckseq_enb r/w 0 check sequence enable-fas alignment enable/disable frame check sequence in fas alignment process. 0 = disables frame check sequence 1 = enables frame check sequence 0 e1 fassel r/w 0 fas alignment algorithm select specifies which algorithm the receive e1 framer block uses in its search for fas alignment. 0 = algorithm 1 1 = algorithm 2
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 48 t able 16: f raming s elect r egister -t1 m ode r egister 7- t1 m ode f raming s elect r egister (fsr) h ex a ddress : 0 x n107 b it f unction t ype d efault d escription -o peration 7 sigframe r/w 0 enable signaling update setting this bit to 1 will enable signaling update (transmit and receive) on the superframe boundary. otherwise, signaling data will be updated once it is received. 6 crcdiag r/w 0 force crc errors setting this bit to 1 will force crc error on transmit stream. 5 j1_crc r/w 0 crc calculation in j1 mode setting this bit to 1 will force crc calcualtion for j1 format. the j1 crc6 cal- culation is based on the actual values of all 4632 bits in a ds1 multiframe including fe bits instead of assuming all fe bits to be a one in t1 format. 4 oneonly r/w 0 allow only one sync candidate setting this bit to 1 will enable framing search engine to declare sync while there is one and only one candidate left. 3 fastsync r/w 1 faster sync algorithm setting this bit to 1 will enable framing search engine to declare sync condi- tion earlier. 2 1 0 fs[2] fs[1] fs[0] r/w r/w r/w 0 0 0 framing select bit 2 framing select bit 1 framing select bit 0 these three bits select the ds1 framing mode. bit 2 is msb and bit 0 is lsb. n ote : changing framing format will cause a resync to be generated auto- matically. framing fs[2] fs[1] fs[0] esf 0 x x sf 1 0 1 n 1 1 0 t1dm 1 1 1 slc a 96 1 0 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 49 t able 17: a larm g eneration r egister - e1 m ode r egister 8 -e1 m ode a larm g eneration r egister (agr) h ex a ddress : 0 x n108 b it f unction t ype d efault d escription -o peration 7 auxpg ro 0 auxp generation enables the generation of auxp pattern which is an unframed 1010. pattern. 0 = auxp is disabled. 1 = auxp is enabled. 6lof r/w 0 loss of frame declaration criteria this read/write bit-field is used to select the lof or red alarm generation cri- teria the receive e1 framer block will employ. 0 = receive e1 framer declares red alarm unless both fas and multi-frame alignment are achieved. 1 = prevents receive e1 framer from declaring red alarm condition; fas alignment is maintained. 5 yel(1) r/w 0 yellow alarm and multiframe yellow alarm generation these bits activate and deactivate the transmission of a yellow alarm. the yel- low alarm and multiframe yellow alarm data pattern can be injected either auto- matically upon detection of the loss of alignment or controlled by yel bits. setting thess bits to b01 will enable automatic yellow alarm transmission in response to a loss of frame alignment (fas red alarm) and multiframe yellow alarm is transmitted in response to a loss of multiframe alignment (cas red alarm). the decoding of these bits are explained as follows: 00 = disable the transmission of yellow alarm. 01 = enable automatical yellow alarm generation. 1. the yellow alarm bits (bit 3 of non-fas frames in ts0) is transmitted by echo- ing the receive fas alignment status. logic one is transmitted if loss of fas alignment occured. 2. the multiframe yellow alarm bits (bit 6 of frame 0 in ts16) is transmitted by echoing the receive cas multiframe alignment status. logic one is transmitted if loss of cas multiframe alignment occured. 10 = yellow and multiframe yellow alarms are transmitted as 0. 11 = yellow and multiframe yellow alarms are transmitted as 1. 4 yel(0) r/w 0 3 aisg(1) r/w 0 ais generation select these read/write bit-fields are used to configure the channel to generate and transmit an ais pattern, as described below. 00 = no ais alarm generated 01 = enable unframed ais alarm generation 10 = enable ais16 generation 11 = enable framed ais alarm generation 2 aisg(0) r/w 0 1 aisd(1) r/w 0 ais pattern detection select these read/write bit-fields are used to specify the type of ais pattern that the receive e1 framer block will detect as described below. 00 = ais alarm detection is disabled. 01 = enable unframed ais alarm detection. 10 = enable ais 16 detection. 11 = enable framed ais alarm detection. 0 aisd(0) r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 50 t able 18: a larm g eneration r egister -t1 m ode r egister 8 - t1 m ode a larm g eneration r egister (agr) h ex a ddress : 0 x n108 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6lof r/w 0 loss of frame declaration criteria a red alarm is generated by the receiver to indicate the loss of frame (lof) alignment. a yellow alarm is then returned to the remote transmitter to report that the receiver detects lof. setting this bit will set the criteria for preventing red alarm from generation as long as the frame is aligned. otherwise, the frame and multiframe must be both aligned in order to keep red alarm from happening. 5 yel(1) r/w 0 yellow alarm and multiframe yellow alarm generation these bits activate and deactivate the transmission of a yellow alarm. the decoding of these bits are explained as follows: 00, = disable the transmission of yellow alarm. 01 = in sf mode (or n mode), yellow alarm is transmitted as bit 2 = 0 (second msb) in all ds0 data channel. in t1dm mode, yellow is transmitted to the remote terminal by setting the outgoing y-bit to zero. in esf mode, follow the following scenario: 1. if yel[0] forms a pulse width shorter or equal to the time required to transmit 255 pattern of 1111_1111_0000_0000 (eight ones followed by eight zeros) on the 4-kbit/s data link (m1-m12), the alarm is transmitted for 255 patterns. 2. if yel[0] is a pulse width longer than the time required to transmit 255 patterns, the alarm continues until tyel[0] goes low. 3. a second yel[0] pulse during an alarm transmission resets the pattern counter and extends the alarm duration for another 255 patterns. 10 = in sf mode, yellow alarm is transmitted as a "1" for the fs bit of frame 12, this is yellow alarm for j1 standard. in t1dm mode, yellow is transmitted to the remote terminal by setting the outgoing y-bit to zero. in esf mode, yellow alarm is controlled by the duration of yel[1]. this allows continuous alarms of any length. 11 = disable the transmission of yellow alarm. 4 yel(0) r/w 0 3 aisg(1) r/w 0 ais generation select these read/write bit-fields are used to configure the channel to generate and transmit an ais pattern, as described below. 00 = no ais alarm generated 01 = enable unframed ais alarm generation 10 = no ais alarm generated 11 = enable framed ais alarm generation 2 aisg(0) r/w 0 1 aisd(1) r/w 0 ais pattern detection select these read/write bit-fields are used to specify the type of ais pattern that the receive e1 framer block will detect as described below. 00 = disabled 01 = unframed ais alarm detection 10 = ais16 detection 11 = unframed ais alarm detection 0 aisd(0) r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 51 t able 19: s ynchronization mux r egister - e1 m ode r egister 9 - e1 m ode s ynchronization mux r egister (smr) h ex a ddress : 0 x n109 b it f unction t ype d efault d escription -o peration 7-6 esrc[1:0] r/w 0 source for e bits these bits determine where the e bits should be inserted from. 00 = transparent, inserted from the status of receiver. 01 = 0. 10 = 1. 11 = data link. 5 reserved - - reserved 4 sync inv r/w 0 sync inversion select selects the direction of the transmit sync and multisync signals. 0 = syncs are input if the css(1:0) bits of csr equal 01 (txserclk input is selected as the timing reference for the transmit section of the framer); otherwise syncs are outputs 1 = syncs are output if css(1:0) bits of csr equal 01 (txserclk input is selected as the timing reference for the transmit section of the framer); otherwise syncs are inputs 3 dlsrc(1) r/w 0 data link source select specifies the source of the data link bits that will be inserted in the outbound e1 frames. 00 = txser_n input: transmit payload data input port will be source of data link bits. 01 = tx hdlc controller: transmit hdlc controller will generate either bos (bit oriented signaling) or mos (message oriented signaling) messages which will be inserted into the data link bit-fields in the outbound e1 frames. 10 = txoh_n input: transmit overhead data input port will be the source of the data link bits. 11 = txser_n input: transmit payload data input port will be the source of the data link bits. 2 dlsrc(0) r/w 0 1 crcsrc r/w 0 crc-4 bits source select this read/write bit-field is used to configure the transmit section of the chan- nel to use either internal generation or the txser_n input pin as the source of the crc-4 bits inserted into the outbound frames. 0 = internally generated and inserted into e1 data stream internally. 1 = tx_ser_n input: transmit payload data input port will be source of crc-4 bits. n ote : this bit-field is ignored if crc multiframe alignment is disabled 0fsrc r/w 0 framing alignment bits source select specifies source of the framing alignment bits, which include fas alignment bits, multiframe alignment bits, e and a bits. 0 = internally generated and inserted into the outbound e1 frames. 1 = txser_n input: transmit serial input port will be source of the fas bits, crc multiframe alignments and the e and a bits.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 52 t able 20: s ynchronization mux r egister - t1 m ode r egister 9 - t1 m ode s ynchronization mux r egister (smr) h ex a ddress : 0 x n109 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 mframealign r/w 0 multirame alignment this bit forces transmit frame counter aligns with the backplance multiframe sync. 0 = the multiframe alignment is not enforced from backplance interface. 1 = the transmit multiframe is aligned with the incoming backplance multiframe timing. 5 msync r/w o tx super frame sync this bit selects the transmit input sync signal from either the frame sync or superframe sync signals. 0 = sync input (txsync) is a frame sync. in 1.544mhz clock mode, txmsync is used, in other clock mode, txmsync is an input transmit clock. 1 = sync input is a superframe sync. 4 sync inv r/w 0 sync inversion select this bit changes the direction of transmit sync and multi-sync signals. 0 = the syncs are inputs if css bits of csr equal to 1, otherwise, syncs are outputs. 1 = the syncs are outputs if css bits of csr equal to 1, otherwise, syncs are inputs. 3 - 2 reserved - - reserved 1 crcsrc r/w 0 crc-6 bits source select this bit determines where the crc-6 bits should be inserted from. 0 = the crc-6 bits are generated and inserted internally. 1 = the crc-6 bits are passed through from the input serial data only when iomux=0 and css < 3. n ote : this bit-field is ignored if crc multiframe alignment is disabled 0fsrc r/w 0 framing alignment bits source select determines where the framing alignment bits should be inserted from. 0 = the framing alignment bits are inserted internally. 1 = the framing alignment bits are passed through from the input serial data only when iomux=0 and css < 3.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 53 t able 21: t ransmit s ignaling and d ata l ink s elect r egister - e1 m ode r egister 10 - e1 m ode t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x n10a b it f unction t ype d efault d escription -o peration 7 txsa8enb r/w 0 specifies if the sa8 bit-field (bit 7 within timeslot 0 of non-fas frames) will be involved in the transport of data link information 0 = data link interface does not use sa8 bit-field. sa8 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa8 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this reg- ister are set to 00x. this bit-field is ignored in all other case. 6 txsa7enb r/w 0 specifies if the sa7 bit-field (bit 6 within timeslot 0 of non-fas frames) will be involved in the transport of data link information 0 = data link interface does not use sa7 bit-field. sa7 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa7 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ignored in all other cases. 5 txsa6enb r/w 0 specifies if the sa6 bit-field (bit 5 within timeslot 0 of non-fas frames) will be involved in the transport of data link information 0 = data link interface does not use sa6 bit-field. sa6 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa6 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ignored in all other case. 4 txsa5enb r/w 0 specifies if the sa5 bit-field (bit 4 within timeslot 0 of non-fas frames) will be involved in the transport of data link information 0 = data link interface does not use sa5 bit-field. sa5 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa5 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ignored in all other case. 3 txsa4enb r/w 0 specifies if the sa4 bit-field (bit 3 within timeslot 0 of non-fas frames) will be involved in the transport of data link information 0 = data link interface does not use sa4 bit-field. sa4 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa4 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ignored in all other case.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 54 2 txsigdl(2) r/w 0 these three read/write bits are used to specify the type of data that is to be transported via national bits in timeslot 0 of the non-fas frames and in timeslot 16 in the outbound frames. the relationship between these bit fields and the role/function of the national and timeslot 16 bits are presented below. national bits (sa4-8 ) 000 = data link data inserted into national bits 001 = data link data inserted into national bits 010 = national bits forced to 1, not used to carry data link data 011 = none (forced to 1) 1xx = none (forced to 1) timeslot 16 000:pcm data. timeslot 16 data taken directly from pcm data input, could include signaling 001 = cas signaling bits a,b,c,d 010 = pcm data. timeslot 16 data taken directly from pcm data input, could include signaling 011 = cas signaling bits a,b,c,d 1xx = hdlc data link. common channel signaling enabled and timeslot 16 is taken from the transmit hdlc controller. 1 txsigdl(1) r/w 0 0 txsigdl(0) r/w 0 t able 22: t ransmit s ignaling and d ata l ink s elect r egister - t1 m ode r egister 10 - t1 m ode t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x n10a b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 reserved - - reserved 5txdlbw[1] r/w r/w 0 0 data link bandwidth 00 = fdl is a 4khz data link channel 01 = fdl is a 2khz data link channel caarried by odd framing bits (1,5,9....) 10 = fdl is a 2khz data link channel carried by even framing bits(3,7,11...) 4 txdlbw[0] r/w 0 3 txde[1] r/w 0 de select 00 = data (serial input). the d/e time slots are inserted from the serial data input. 01 = lapd controller. the d/e time slots are inserted from the lapd control- ler. 10 = data (serial input). the d/e time slots are inserted from the serial data input. 11 = fractional input. the d/e time slots are inserted from the fractional input. 2 txde[0] r/w 0 1 txdl[1] r/w 0 dl select 00 = lapd controlller/slc96 buffer. the data link bits are inserted from the lapd controller. (lapd1 is the only controller that can be used to transport lapd messages through the data link bits) 01 = serial input. the data link bits are inserted from serial data input. 10 = overhead input. the data link bits are inserted from overhead input. 11 = none (forced to 1). the data link bits are forced to 1. 0 txdl01] r/w 0 t able 21: t ransmit s ignaling and d ata l ink s elect r egister - e1 m ode r egister 10 - e1 m ode t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x n10a b it f unction t ype d efault d escription -o peration
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 55 t able 23: f raming c ontrol r egister e1 m ode r egister 11 -- e1 m ode f raming c ontrol r egister (fcr) h ex a ddress : 0 x n10b b it f unction t ype d efault d escription -o peration 7 rsync r/w 0 force re-synchronization a 0 to 1 transition in this bit-field forces the receive e1 framer to restart the synchronization process. this bit field is automatically cleared (set to 0) after frame synchronization is reached. 6 casc(1) r/w 0 loss of cas multiframe alignment criteria select these two read/write bits are used to select the loss of cas multi-frame align- ment declaration criteria. the relationship between the state of these two bit fields and the corresponding loss of cas multi-frame is presented below. 00 = two consecutive cas multi-frames with multiframe alignment signal (mas) errors 01 = three consecutive cas multi-frames with mas errors 10 = four consecutive cas multi-frames with mas errors 11 = eight consecutive cas multi-frames with mas errors n ote : these bits are only active if channel associated signaling is used. 5 casc(0) r/w 0 4 crcc(1) r/w 0 loss of crc-4 multiframe alignment criteria select selects criteria for loss of crc-4 multiframe alignment. 00 = four consecutive crc multiframe alignment signals have been received in error 01 = two consecutive crc multiframe alignment signals have been received in error 10 = eight consecutive crc multiframe alignment signals have been received in error 11 = 915 or more crc-4 errors have been detected in one second. n ote : these bit-fields are ignored if crc multiframe alignment has been dis- abled. 3 crcc(0) r/w 0 2 fasc(2) r/w 0 loss of fas alignment criteria select these three read/write bits are used to select loss of fas frame declaration criteria. the relationship between the state of these bits and the corresponding loss of fas frame declaration is presented below. 000 = illegal - do not use 001 = 1 errored fas pattern 010 = 2 consecutive errored fas patterns 011 = 3 consecutive errored fas patterns 100 = 4 consecutive errored fas patterns 101 = 5 consecutive errored fas patterns 110 = 6 consecutive errored fas patterns 111 = 7 consecutive errored fas patterns 1 fasc(1) r/w 1 0 fasc(0) r/w 1
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 56 t able 24: f raming c ontrol r egister t1 m ode r egister 11 -- t1 m ode f raming c ontrol r egister (fcr) h ex a ddress : 0 x n10b b it f unction t ype d efault d escription -o peration 7 rsync r/w 0 force re-synchronization a 0 to 1 transition in this bit-field forces the receive ds1 framer to restart the synchronization process. this bit field is automatically cleared (set to 0) after frame synchronization is reached. 6 crcenb/ oneonly r/w 0 sync with crc verification in esf. (assuming only one ft sync candidate exists.) 0 = no crc match test 1 = include crc match test as part of synchronization criteria. 5 tolr[2] r/w 0 tolerance bits [2:0] the tolerance (tolr) and range (rang) form the criteria for loss of frame alignment. a loss of frame is declared if there is tolr out of rang errors in the framing pattern. the recommended tolr value is 2. n ote : a 0 value for tolr is internally blocked. a tolr value must be spec- ified. 4 tolr[1] r/w 1 3 tolr[0] r/w 0 2rang[2] r/w 1 range bits [2:0] the tolerance (tolr) and range (rang) form the criteria for loss of frame alignment. a loss of frame is declared if there is tolr out of rang errors in the framing pattern. the recommended rang value is 5. n ote : a 0 value for rang is internally blocked. a rang value must be specified. 1rang[1] r/w 0 0rang[0] r/w 1
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 57 t able 25: r eceive s ignaling & d ata l ink s elect r egister - e1 m ode r egister 12 - e1 m ode r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) h ex a ddress : 0 x n10c b it f unction t ype d efault d escription -o peration 7 rxsa8enb r/w 0 this read/write bit is used to specify whether or not data link information will be transported via national bit sa8 (bit 7 within timeslot 0 of non-fas frames) 0 = sa8 does not carry data link information 1 = sa8 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry data link bits). 6 rxsa7enb r/w 0 this read/write bit is used to specify whether or not data link information will be transported via national bit sa7 (bit 6 within timeslot 0 of non-fas frames) 0 = sa7 does not carry data link information 1 = sa7 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry data link bits). 5 rxsa6enb r/w 0 this read/write bit is used to specify whether or not data link information will be transported via national bit sa6 (bit 5 within timeslot 0 of non-fas frames) 0 = sa6 does not carry data link information 1 = sa6 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry data link bits). 4 rxsa5enb r/w 0 this read/write bit is used to specify whether or not data link information will be transported via national bit sa5 (bit 4 within timeslot 0 of non-fas frames) 0 = sa5 does not carry data link information 1 = sa5 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry data link bits). 3 rxsa4enb r/w 0 this read/write bit is used to specify whether or not data link information will be transported via national bit sa4 (bit 3 within timeslot 0 of non-fas frames) 0 = sa4 does not carry data link information 1 = sa4 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (if the national bits have been configured to carry data link bits). 2 rxsigdl(2) r/w 0 these three read/write bits are used to configure the receive section of the channels on how to interpret the national and timeslot 16 bits. specifies how signaling and data link information is received via the e1 frames. national bits (sa4-8 ) 000 = data link data extracted from national bits 001 = data link data extracted from national bits 010 = data link data is not extracted from national bits 011 = data link data is not extracted from national bits 1xx = data link data is not extracted from national bits timeslot 16 bits 000 = pcm data. 001 = cas signal a,b,c,d 010 = pcm data. 011 = cas signal a,b,c,d 1xx = data link (ccs). timeslot 16 data is extracted by the receive hdlc controller 1 rxsigdl(1) r/w 0 0 rxsigdl(0) r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 58 t able 26: r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) t1 m ode r egister 12 - t1 m ode r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) h ex a ddress : 0 x n10c b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 reserved - - reserved 5 rxdlbw[1] r/w 0 data link bandwidth 00 = fdl is a 4khz data link channel. 01 = fdl is a 2khz data link channel carried by old framing bits(1,5,9,....). 10 = fdl is a 2khz data link channel carried by even framing bits(3,7,11,....). 4 rxdlbw[0] r/w 0 3 rxde[1] r/w 0 de select 00 = serial output only. the d/e time slots are sent to serial data output. 01 = lapd controller. the d/e time slots are fed into lapd controller. 10 = data (fractional output). the d/e time slots are sent to serial fractional data output. 11 = overhead output. the d/e time slots are sent to overhead output. 2 rxde[0] r/w 0 1 rxdl[1] r/w 0 dl select (esf,t1dm,slc96, n fs bits) 00 =lapd controller and serial output. the data link bits are fed into the lapd controller and also serial data output. (lapd1 is the only controller that can be used to receive lapd messages through the data link bits) 01 = serial output only. the data link bits are sent to serial data output. 10 = overhead output and serial output. the data link bits are sent to overhead output and also serial data output. 11 = none (forced to 1). the data link bits are forced to 1. 0 rxdl[0] r/w 0 t able 27: s ignaling c hange r egister 0 - t1 m ode r egister 13 - t1 m ode s ignaling c hange r egister 0 (scr 0) h ex a ddress : 0 x n10d b it f unction t ype d efault d escription -o peration 7 ch. 0 rur 0 these reset upon read bits indicate whether the signaling data associated with channels 0-7 has changed since the last read of this register. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of register n ote : this register is only relevant if the framing channel is using channel associated signaling 6 ch. 1 rur 0 5 ch.2 rur 0 4 ch.3 rur 0 3 ch.4 rur 0 2 ch.5 rur 0 1 ch.6 rur 0 0 ch.7 rur 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 59 t able 28: s ignaling c hange r egister 0 - e1 m ode r egister 13 - e1 m ode s ignaling c hange r egister 0 (scr 0) h ex a ddress : 0 x n10d b it f unction t ype d efault d escription -o peration 7 n/a ro 0 these reset upon read bits indicate whether the signaling data associated with channels 1-7 has changed since the last read of this register. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of register n ote : this register is only relevant if the framing channel is using channel associated signaling 6 ch. 1 rur 0 5 ch.2 rur 0 4 ch.3 rur 0 3 ch.4 rur 0 2 ch.5 rur 0 1 ch.6 rur 0 0 ch.7 rur 0 t able 29: s ignaling c hange r egister 1 r egister 14 s ignaling c hange r egister 1 (scr 1) h ex a ddress : 0 x n10e b it f unction t ype d efault d escription -o peration 7 ch.8 rur 0 these reset upon read bits indicate whether the signaling data associated with channels 8-15 has changed since the last read of this register. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of register n ote : this register is only relevant if the framing channel is using channel associated signaling 6 ch.9 rur 0 5 ch.10 rur 0 4 ch.11 rur 0 3 ch.12 rur 0 2 ch.13 rur 0 1 ch.14 rur 0 0 ch.15 rur 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 60 t able 30: s ignaling c hange r egister 2 r egister 15 s ignaling c hange r egister 2 (scr 2) h ex a ddress : 0 x n10f b it f unction t ype d efault d escription -o peration 7 ch.16 rur 0 these reset upon read bits indicate whether the signaling data associated with channels 16-23 has changed since the last read of this register. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of register n ote : this register is only relevant if the framing channel is using channel associated signaling 6 ch.17 rur 0 5 ch.18 rur 0 4 ch.19 rur 0 3 ch.20 rur 0 2 ch.21 rur 0 1 ch.22 rur 0 0 ch.23 rur 0 t able 31: s ignaling c hange r egister 3 r egister 16 - e1 o nly s ignaling c hange r egister 3 (scr 3) h ex a ddress : 0 x n110 b it f unction t ype d efault d escription -o peration 7 ch.24 rur 0 these reset upon read bits indicate whether the signaling data associated with channels 24-31 has changed since the last read of this register. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of register n ote : this register is only relevant if the framing channel is using channel associated signaling 6 ch.25 rur 0 5 ch.26 rur 0 4 ch.27 rur 0 3 ch.28 rur 0 2 ch.29 rur 0 1 ch.30 rur 0 0 ch.31 rur 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 61 n ote : the value of the bit-fields within this register only have meaning if the framer is using channel associated signaling. t able 32: r eceive n ational b its r egister r egister 17 r eceive n ational b its r egister (rnbr) h ex a ddress : 0 x n111 b it f unction t ype d efault d escription -o peration 7 si_fas ro x received international bit - fas frame this read only bit-field contains the value of the international bit in the most recently received fas frame 6 si_nonfas ro x received international bit - non fas frame this read only bit-field contains the value of the international bit in the most recently received non-fas frame 5 r_alarm ro x received fas yellow alarm this read only bit-field contains the value in the remote alarm bit-field (frame yellow alarm) within the non-fas frame. 4 sa4 ro x received national bits these read only bit-fields contain the values of the national bits within the most recently received non-fas frame. 3 sa5 ro x 2 sa6 ro x 1 sa7 ro x 0 sa8 ro x t able 33: r eceive e xtra b its r egister r egister 18 r eceive e xtra b its r egister (rebr) h ex a ddress : 0 x n112 b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3 ex1 ro x extra bit 1 corresponds to value in bit 5 within timeslot 16 of frame 0 of the signaling multi- frame 2 alarmfe ro x cas multi-frame yellow alarm corresponds to value in bit 6(cas multiframe yellow alarm) within timeslot 16 of frame 0 of the signaling multiframe. 0 = remote e1 transmitting terminal is not sending cas multiframe yellow alarm 1 = remote e1 transmitting terminal is sending cas multiframe yellow alarm 1 ex2 ro x extra bit 2 corresponds to value in bit 7 within timeslot 16 of frame 0 of the signaling multi- frame 0 ex3 ro x extra bit 3 corresponds to value in bit 8 within timeslot 16 of frame 0 of the signaling multi- frame
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 62 t able 34: d ata l ink c ontrol r egister r egister 19 d ata l ink c ontrol r egister 1 (dlcr1) h ex a ddress : 0 x n113 b it f unction t ype d efault d escription -o peration 7 slc-96 r/w 0 slc ? 96 enable, 6 bit for esf if slc ? 96 framing is selected, setting this bit high will enable slc ? 96 data link transmission; otherwise, the regular sf framing bits are transmitted. in esf framing mode, setting this bit high will cause facility data link to trans- mit/receive slc ? 96-like message. 6 mosa r/w 0 mos abort enable/disable select this read/write bit-field is used to configure the transmit hdlc1 controller to automatically transmit an abort sequence anytime it transitions from the mos mode to the bos mode. 0 = transmit hdlc1 controller inserts an mos abort sequence if the mos message is interrupted 1 = prevents transmit hdlc1 controller from inserting an mos abort sequence. 5 rx_fcs_dis r/w 0 receive fcs verification disable enables/disables receive hdlc1 controllers computation and verification of the fcs value in the incoming lapd message frame 0 = verifies fcs value of each mos frame. 1 = does not verify fcs value of each mos frame. 4autorx r/w 0 auto receive lapd message configures the rx hdlc1 controller to discard any incoming lapd mes- sage frame that exactly match which is currently stored in the rx hdlc1 buffer. 0 = disabled 1 = enables this feature. 3 tx_abort r/w 0 transmit abort configures the tx hdlc1 controller to transmit an abort sequence (string of 7 or more consecutive 1s) to the remote terminal. 0 = tx hdlc1 controller operates normally 1 = tx hdlc1 controller inserts an abort sequence into the data link channel. 2 tx_idle r/w 0 transmit idle (flag sequence byte) configures the tx hdlc1 controller to transmit a string of flag sequence octets (0x7e) in the data link channel to the remote terminal. 0 = tx hdlc1 controller resumes transmitting data to the remote terminal 1 = tx hdlc1 controller transmits a string of flag sequence bytes. n ote : this bit-field is ignored if the tx hdlc1 controller is operating in the bos mode - bit-field 0(mos/bos) within this register is set to 0. 1 tx_fcs_en r/w 0 transmit lapd message with fcs configure hdlc1 controller to include/not include fcs octets in the out- bound lapd message frames. 0 = does not include fcs octets into the outbound lapd message frame. 1 = inserts fcs octets into the outbound lapd message frame. n ote : this bit-field is ignored if the transmit hdlc1 controller has been configured to operate in the bos mode. 0 mos/bos r/w 0 message oriented signaling/bit oriented signaling select specifies whether the txrx hdlc1 controller will be transmitting and receiving lapd message frames (mos) or bit oriented signal (bos) mes- sages. 0 = tx/rx hdlc1 controller transmits and receives bos messages. 1 = tx/rx hdlc1 controller transmits and receives mos messages.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 63 t able 35: t ransmit d ata l ink b yte c ount r egister r egister 20 t ransmit d ata l ink b yte c ount r egister 1 (tdlbcr1) h ex a ddress : 0 x n114 b it f unction t ype d efault d escription -o peration 7 bufaval//bufsel r/w 0 transmit hdlc1 buffer available/buffer select specifies which of the two tx hdlc1 buffers that the tx hdlc1 controller should read from to generate the next outbound hdlc1 message. 0 = transmits message data residing in tx hdlc1 buffer 0. 1 = transmits message data residing in tx hdlc1 buffer 1. n ote : if one of these tx hdlc1 buffers contain a message which has yet to be completely read-in and processed for transmission by the tx hdlc1 controller, then this bit-field will automatically reflect the value corresponding to the available buffer. changing this bit-field to the in-use buffer is not per- mitted. 6 tdlbc6 r/w 0 transmit hdlc1 message - byte count depends on whether an mos or bos message is being transmitted to the remote terminal equipment if bos message is being transmitted : these bit fields contain the number of repetitions the bos message must be transmitted before the tx hdlc1 controller generates the txeot interrupt and halts transmission. if these fields are set to 00000000, then the bos message will be transmitted for an indefinite number of times. if mos message is being transmitted: these bit fields contain the length, in number of octets, of the message to be transmitted. 5 tdlbc5 r/w 0 4 tdlbc4 r/w 0 3 tdlbc3 r/w 0 2 tdlbc2 r/w 0 1 tdlbc1 r/w 0 0 tdlbc0 r/w 0 t able 36: r eceive d ata l ink b yte c ount r egister r egister 21 r eceive d ata l ink b yte c ount r egister 1 (rdlbcr1) h ex a ddress : 0 x n115 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc1 buffer-pointer identifies which rxhdlc1 buffer contains the newly received hdlc1 mes- sage. 0 = hdlc1 message is stored in rx hdlc1 buffer 0. 1 = hdlc1 message is stored in rx hdlc1 buffer 1. 6 rdlbc6 r/w 0 re ceive hdlc message - byte count in mos mode these seven bit-fields contain the size in bytes of the hdlc1 message that has been extracted and written into the rx hdlc1 buffer. in bos mode these bits should be set to the value of the message repetitions before each receive interrupt. if ithey are set to 0, no rxeot interrupt will be generated. 5 rdlbc5 r/w 0 4 rdlbc4 r/w 0 3 rdlbc3 r/w 0 2 rdlbc2 r/w 0 1 rdlbc1 r/w 0 0 rdlbc0 r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 64 t able 37: s lip b uffer c ontrol r egister r egister 22 s lip b uffer c ontrol r egister (sbcr) h ex a ddress : 0 x n116 b it f unction t ype d efault d escription -o peration 7 txsb_isfifo r/w 0 selects slip buffer as a fifo for all clock modes while txclk and txserclk are synced. 0 = buffer acts as slip buffer if enabled. 1 = buffer acts as a fifo. the data latency is dictated by fifo latency. 6-5 reserved - - reserved 4 sb_forcesf r/w 0 force signaling freeze setting this bit high stops further signal updating until this bit is cleared. 1 = signaling array is not updated. 0 = signaling array is updated only if sb_enb[1:0] = 01 or 10 3 sb_sfenb r/w 0 signal freeze enable this bit enables signaling freeze for one multiframe after buffer slipping. 1 = signaling freeze is enabled. 0 = signaling freeze is disabled. 2sb_sdir r/w 1 slip buffer (rxsync) direction selec t allows rxsync output pin to be an input or an output. 0 = rxsync is an output pin 1 = rxsync is an input pin 1 sb_enb(1) r/w 0 slip buffer mode select selects mode of operation of slip buffer. 00 = buffer is bypassed and rxsync and rxserclk are outputs. 01 = elastic store slip buffer enabled. rxserclk is an input. 10 = buffer acts as fifo data latency dictated by the setting within the fifo latency register. rxserclk is an input. 11 = buffer is bypassed. rxsync and rxserclk are outputs. 0 sb_enb(0) r/w 0 t able 38: fifo l atency r egister r egister 23 fifo l atency r egister (ffolr) h ex a ddress : 0 x n117 b it f unction t ype d efault d escription -o peration 7-5 reserved - - reserved 4-0 latency r/w 0 sets the distance between slip buffer read and slip buffer write pointers in fifo mode.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 65 t able 39: dma 0 (w rite ) c onfiguration r egister r egister 24 dma 0 w rite c onfiguration r egister (d 0 wcr) h ex a ddress : 0 x n118 b it f unction t ype d efault d escription -o peration 7 dma0 rst r/w 0 dma_0 reset resets transmit dma 0 channel. 0 = normal operation. 1 = a zero to one transition resets dma channel_0. 6 dma0 enb r/w 0 dma_0 enable enables dma_0 interface. 0 = disables dma_0 interface 1 = enables dma_0 interface 5 wr type r/w 0 write type select selects function of wr signal. 0 = wr functions as direction signal (indicates whether the current bus cycle is a read or write operation) and rd functions as a data strobe signal. 1 = wr functions as a write strobe signal and rd functions as configured in the dma 1 configuration register. 4 - 3 reserved - - reserved 2 dma0_chan(2) r/w 0 channel select selects which channel, within the chip, is to use the dma_0 (write) interface. 000 = channel 0 001 = channel 1 001 = channel 2 011 = channel 3 100 = channel 4 101 = channel 5 110 = channel 6 111 = channel 7 1 dma0_chan(1) r/w 0 0 dma0_chan(0) r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 66 t able 40: dma 1 (r ead ) c onfiguration r egister r egister 25 dma 1 (r ead ) c onfiguration r egister (d1cr) h ex a ddress : 0 x n119 b it f unction t ype d efault d escription -o peration 7-6 reserved - - reserved 7 dma1 rst r/w 0 dma_1 reset resets the dma 1 channel 0 = normal operation. 1 = a zero to one transition resets dma channel. 6 dma1 enb r/w 0 dma1_enb enables dma_1 interface 0 = disables dma_1 interface 1 = enables dma_1 interface 5 rd type r/w 0 selects the function of prd_l signal. 0 = rd functions as a read strobe signal 11 = rd acts as a direction signal, wr works as a data strobe. 4 - 3 reserved - - reserved 2 dma1_chan(2) r/w 0 channel select selects which channel, within the chip, is to use the dma_1 interface. 000 = channel 0 001 = channel 1 001 = channel 2 011 = channel 3 100 = channel 4 101 = channel 5 110 = channel 6 111 = channel 7 1 dma1_chan(1) r/w 0 0 dma1_chan(0) r/w 0 t able 41: i nterrupt c ontrol r egister r egister 26 i nterrupt c ontrol r egister (icr) h ex a ddress : 0 x n11a b it f unction t ype d efault d escription -o peration 7-3 reserved - - reserved 2 int_wc_rur r/w 0 interrupt write-to-clear or reset-upon-read select configures interrupt status bits to either reset upon read or write-to-clear 0=interrupt status bit rur 1=interrupt status bit write-to-clear 1enbclr r/w 0 interrupt enable auto clear 0=interrupt enable bits are not cleared after status reading 1=interrupt enable bits are cleared after status reading 0 intrup_enb r/w 0 interrupt enable for framer_n enables framer n for interrupt generation. 0 = disables corresponding framer block for interrupt generation 1 = enables corresponding framer block for interrupt generation
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 67 t able 42: lapd s elect r egister r egister 20 lapd s elect r egister (lapdsr) h ex a ddress : 0 x n11b b it f unction t ype d efault d escription -o peration [7:2] reserved - - these bits are reserved [1:0] lapdsel r/w 0 lapd select bits [1:0] determine which hdlc controller has access to the read/ write registers 0xn600 and 0xn700 for storing or extracting lapd messages. 00 = hdlc controller 1 01 = hdlc controller 2 10 = hdlc controller 3 11 = hdlc controller 1 t able 43: c ustomer i nstallation a larm g eneration r egister r egister 20 - t1 c ustomer i nstallation a larm g eneration r egister (ciagr) h ex a ddress : 0 x n11c b it f unction t ype d efault d escription -o peration [7:4] reserved - - these bits are reserved [3:2] ciag r/w 0 ci alarm transmit (only in esf) alarm indication signal-customer installation (ais-ci) and remote alarm indication-customer installation (rai-ci) are intendedfor use in a network to differentiate between an issue within the network or the ci. ais-ci is an all ones signal with an embedded signature of 01111100 11111111 right-to left which recurs at 386 bit intervals in- the ds-1 signal. 00 = no ci alarm generation 01 = enable unframed ais-ci alarm generation 10 = enable rai-ci generation 11 = no ci alarm generation [1:0] ciad r/w 0 ci alarm detect (only in esf) 00 = ci alarm detection is disabled 01 = enable unframed ais-ci alarm detection 10 = enable rai-ci detection 11 = ci alarm detection is disabled
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 68 t able 44: p erformance r eport c ontrol r egister r egister 20 - t1 p erformance r eport c ontrol (prcr) h ex a ddress : 0 x n11d b it f unction t ype d efault d escription -o peration [7:2] reserved - - these bits are reserved [1:0] apcr r/w 0 automatic performance control/response report these bits automatically generates a summary report of the pmon status so that it can be inserted into an out going lapd message. 00 = no performance report issued 01 = single performance report issued when a write of 00 follows by a write of 01 10 = automatically issues a performance report every one second 11 = no performance report issued t able 45: g apped c lock c ontrol r egister r egister 20 - t1 g apped c lock c ontrol r egister (gccr) h ex a ddress : 0 x n11e b it f unction t ype d efault d escription -o peration [7:2] reserved - - these bits are reserved 1 txgccr r/w 0 transmit gapped clock interface this bit is used to select a gapped clock interface operating at 2.048mbit/s in ds-1 mode. in this application, 63 gaps (missing data) are inserted so that the overall bit rate is reduced to 1.544mbit/ s. (in this mode, txmsync is used as the 2.048mhz gapped clock input. txser is used as the 2.048mhz gapped data input. txserclk must be 1.544mhz.) 0 = disabled 1 = transmit gapped clock for the transmit path 0 rxgccr r/w 0 receive gapped clock interface this bit is used to select a gapped clock interface operating at 2.048mbit/s in ds-1 mode. in this application, 63 gaps (missing data) are inserted so that the overall bit rate is reduced to 1.544mbit/ s. (in this mode, rxserclk should be configured as an input so that a 2.048mhz gapped clock can be applied to the framer block. rxser is used as the 2.048mhz gapped data output. the posi- tion of the gaps will be determined by the gaps placed in rxser- clk by the user.) 0 = disabled 1 = receive gapped clock for the receive path
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 69 registers 0x1b thru 0x1f unused. t able 46: t ransmit i nterface c ontrol r egister - e1 m ode r egister 27 - e1 m ode t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x n120 b it f unction t ype d efault d escription -o peration 7 txsyncfrd r/w 0 tx synchronous fraction data interface 0 = fractionl data is clocked into the chip using txchclk 1 = fractional data is clocked in to the chip using txserclk (ungaped). txchn[4:0] still indicates the time slot number if txfr2048 is not 1, tximode[1:0] = 00, and txmuxen = 0. txchclk is used as fractional data enable. 6 reserved - - reserved 5 txplclkenb r/w 0 tx payload clock enable 1 = txserclk will output tx clock with oh bit period blocked in 2.048hz clock output mode. txsync is low r/w 0 txsync is low in h.100 and hmvip mode 0 = txsync is active low 1 = txsync is active high 4 txfr2048 r/w 0 if txmuxen = 0 and tximode[1:0] = 00 0 = txchn[4:0] outputs the channel number as ususal. 1 = txchn[0]/txsig inputs signaling information and txchn[1]/txfrtd will input fractional channel data in 2.048 mbit mode. note; this bit has no effect while either txmuxen = 1 or tximode[1:0] = 00, txchn[4:0] signals input txsig and fractional data. 3 txiclkinv r/w 0 clock inversion 0 = data transition happens on rising edge of the transmit clocks. 1 = data transition happens on falling edge of the transmit clocks. 2 txmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream. 1 tximode[1] r/w 0 tx interface mode selection this mode selection determines the interface speed. when txmuxen = 0, 00 = transmit interface is taking data at a rate of 2.048mbit/s. 01 = transmit interface is taking data at a rate of 2.048mbit/s. 10 = transmit interface is taking data at a rate of 4.096mbit/s. 11 = transmit interface is taking data at a rate of 8.192mbit/s. when txmuxen = 1, 00 = rserved 01 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and bit-demultiplexing into 4 channels from to the liu outputs on channels 0 through 3. the txsync pulse remains high during the framing bit of each e1 frame. 10 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte-demultiplexing into 4 channels from to the liu outputs on channels 0 through 3 (hmvip mode). the txsync pulse remains high during the last two bits of the previous e1 frame and the first two bits of the current e1 frame. 11 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte-demultiplexing into 4 channels from to the liu outputs on channels 0 through 3 (h.100 mode). the txsync pulse remains high during the last bit of the previous e1 frame and the first bit of the current e1 frame. n ote : channel 4 is de-multiplexed into the liu outputs at channel 4 through 7. 0 tximode[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 70 t able 47: t ransmit i nterface c ontrol r egister - t1 m ode r egister 27 - t1 m ode t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x n120 b it f unction t ype d efault d escription -o peration 7 txsyncfrd r/w 0 transmit synchronous fractional data interface 0 = fractional data is clocked into the chip using txchclk 1 = fractional data is clocked in to the chip using txserclk (ungapped). txchn[4:0] still indicates the time slot number if txfr1544 is not 1, tximode[1:0] = 00, and txmuxen = 0. txchclk is used as fractional data enable. 6 reserved - - reserved 5 txplclkenb r/w 0 transmit payload clock enable 1 = txserclk will output tx clock with oh bit period blocked in 1.544mhz clock output mode. txsync is low 0 txsync is low in h.100 and hmvip mode 0 = txsync is active low 1 = txsync is active high 4 txfr1544 r/w 0 if txmuxen = 0 and tximode[1:0] = 00 0 = txchn[4:0] will output the channel number as usual. 1 = txchn[0]/txsig will input signaling information and txchn[1]/txfrtd will input fractional channel data in 1.544 mbit mode. n ote : this bit has no effect while either txmuxen = 1 or tximode[1:0] = 00, txchn[4:0] signals input txsig and fractional data. 3 txiclkinv r/w 0 clock inversion 0 = data transition occurs on rising edge of the transmit clock. 1 = data transition occurs on falling edge of the transmit clock. 2 txmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream. 1 tximode[1] r/w 0 tx intf mode selection this mode selection determines the interface speed. when txmuxen = 0 00 = transmit interface is taking data at a rate of 1.544mbit/s. 01 = transmit interface is taking data at a rate of 2.048mbit/s. 10 = transmit interface is taking data at a rate of 4.096mbit/s. 11 = transmit interface is taking data at a rate of 8.192mbit/s. when txmuxen = 1, 00 = transmit interface is taking data at a rate of 12.352mbit/s from channel 0 and bit- demultiplexing into 4 channels from to the liu outputs on channels 0 through 3. the txsync pulse remains high during the framing bit of each ds-1 frame. 01 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and bit- demultiplexing into 4 channels from to the liu outputs on channels 0 through 3. the txsync pulse remains high during the framing bit of each ds-1 frame. 10 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte- demultiplexing into 4 channels from to the liu outputs on channels 0 through 3 (hmvip mode). the txsync pulse remains high during the last two bits of the previous ds-1 frame and the first two bits of the current ds-1 frame. 11 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte- demultiplexing into 4 channels from to the liu outputs on channels 0 through 3 (h.100 mode). the txsync pulse remains high during the last bit of the previous ds-1 frame and the first bit of the current ds-1 frame. n ote : channel 4 is de-multiplexed into the liu outputs at channel 4 through 7. 0 tximode[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 71 t able 48: r eceive i nterface c ontrol r egister (ricr) - e1 m ode register 28 - e1 mode r eceive i nterface c ontrol r egister (ricr) 0 x n122 b it f unction t ype d efault d escription -o peration 7 rxsyncfrd r/w 0 rx synchronous fractional data interface 0 = fractional data is clocked out from the chip using rxchclk 1 = rxchclk is used to output fractional data enable instead of being fraction data clock. in this mode, fractional data is clocked out of the chip using rxserclk (ungapped). rxchn still indicates the time slot number if rxfr2048 is not 1, rxi- mode[1:0] = 0, and rxmuxen = 0. 6 reserved - - reserved 5 rxplclkenb/ r/w 0 rx payload clock enable 1 = rxserclk outputs rx clock with oh bit period blocked while in 2.048mhz clock output mode. rxsyncislow rxsync is low in h.100 and hmvip mode 1 = rxsync active low. 0 = rxsync active high. 4 rxfr2048 r/w 0 clock inversion 1 = rxchn[0]/rxsig outputs signaling information, rxchn[1]/rxfrtd will output fractional channel data in 2.048 mhz mode and rxchn[2] will output the serial channel number of each time slot. 0 = rxchn[4:0] outputs the parallel channel number as usual. 3 rxiclkinv n/a 0 clock inversion 0 = data transition happens on the rising edge of the transmit clocks. 1 = data transition happens on the falling edge of the transmit clocks. 2 rxmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream. 1 rximode[1] r/w 0 rx intf mode selection this mode selection determines the interface speed. when rxmuxen = 0 00 = receive interface is presenting data at a rate of 2.048mbit/s. 01 = receive interface is presenting data at a rate of 2.048mbit/s. 10 = receive interface is presenting data at a rate of 4.096mbit/s. 11 = receive interface is presenting data at a rate of 8.192mbit/s. when rxmuxen = 1 00 = rserved 01 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into the serial output channel 0. the txsync pulse remains high during the framing bit of each e1 frame. 10 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into the serial output channel 0 (hmvip mode). the txsync pulse remains high during the last two bits of the previous e1 frame and the first two bits of the current e1 frame. 11 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into the serial output channel 0 (h.100 mode). the txsync pulse remains high during the last bit of the previous e1 frame and the first bit of the current e1 frame. n ote : channels 4 through 7 are multiplexed into the serial output at channel 4. 0 rximode[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 72 t able 49: r eceive i nterface c ontrol r egister (ricr) - t1 m ode register 28 - t1 mode r eceive i nterface c ontrol r egister (ricr) 0 x n122 b it f unction t ype d efault d escription -o peration 7 rxsyncfrd r/w 0 rx synchronous fractional data interface 1 = rxchclk is used to output fractional data instead of being fraction data clock. in this mode, fractional data is clocked out of the chip using rxserclk (ungapped). rxchn still indicates the time slot number if rxfr1544 is not 1, rximode[1:0] = 00, and rxmuxen = 0. rxcclk will be a valid signal for fractional data output (rxfrtd) if rxfr1544 is 1 or rxi- mode[1:0] = 00 or rxmuxen = 0 6 reserved - - reserved 5 rxplclkenb/ r/w 0 rx payload clock enable 1 = rxserclk will output rx clock with oh bit period blocked while in 1.544mhz clock output mode. rxsyncislow rxsync is low in h.100 and hmvip mode 1 =rx sync active low. 0 = rxsync active high. 4 rxfr1544 r/w 0 clock inversion/rxsig 1 = rxchn[0]/rxsig outputs signaling information, rxchn[1]/rxfrtd will output frac- tional channel data in 1.544 mhz mode and rxchn[2] will output the serial channel number of each time slot. 0 = rxchn[4:0] outputs the parallel channel number as usual. 3 rxiclkinv n/a 0 clock inversion 0 = data transition happens on the rising edge of the transmit clocks. 1 = data transition happens on the falling edge of the transmit clocks. 2 rxmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream. 1 rximode[1] r/w 0 rx interface mode selection this mode selection determines the interface speed. when rxmuxen = 0, 00 = receive interface is presenting data at a rate of 1.544mbit/s. 01 = receive interface is presenting data at a rate of 2.048mbit/s. 10 = receive interface is presenting data at a rate of 4.096mbit/s. 11 = receive interface is presenting data at a rate of 8.192mbit/s. when rxmuxen = 1, 00 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 12.352mhz serial output on channel 0. the txsync pulse remains high during the framing bit of each ds-1 frame. 01 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 16.384mhz serial output on channel 0. the txsync pulse remains high during the framing bit of each ds-1 frame. 10 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 16.384mhz serial output on channel 0 (hmvip mode). the txsync pulse remains high during the last two bits of the previous ds-1 frame and the first two bits of the current ds-1 frame. 11 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 16.384mhz serial output on channel 0 (h.100 mode). the txsync pulse remains high during the last bit of the previous ds-1 frame and the first bit of the current ds-1 frame. n ote : channels 4 through 7 are multiplexed into the serial output at channel 4. 0 rximode[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 73 t able 50: ds1 t est r egister register 29 ds1 test register (ds1tr) 0x n123 b it f unction t ype d efault d escription -o peration 7 prbstyp r/w 0 prbs pattern type 0 = the (x 15 + x 14 +1) pbrs polynomial is generated. 1 = qrts (quasi-random test signal) pattern is generated. 6 errorins r/w 0 error insertion 0 to 1 transition will cause one output bit inverted 5 reserved - - reserved 4 rxprbslock r 0 lock status 0 = rx prbs has not locked. 1 = rx prbs has locked to the input patterns. 3 rxprbsenb r/w 0 rx prbs generation enable 0 = receive prbs checker is not enabled. 1 = receive prbs checker is enabled. 2 txprbsenb r/w 0 tx prbs generation enable 0 = tx prbs generator is not enabled. 1 = tx prbs generator is enabled. 1 rxds1bypass r/w 0 rx ds1 framer bypass reserved 0 txds1bypass r/w 0 tx ds1 framer bypass 0 = tx frame pulse bypassed. 1 = tx frame pulse and data are from txser and txsync inputs.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 74 t able 51: l oopback c ode c ontrol r egister register 30 l oopback c ode c ontrol r egister (lccr) 0 x n124 b it f unction t ype d efault d escription -o peration 7-6 rxlbcdlen[1:0] r/w 0 receive loopback code activation length determines the receive loopback code activation length. 00 = 4-bit sequence 01 = 5-bit sequence 10 = 6-bit sequence 11 = 7-bit sequence 5-4 rxlbcdlen[1:0] r/w 0 receive loopback code deactivation length determines the receive loopback code deactivation length 00 = 4-bit sequence 01 = 5-bit sequence 10 = 6-bit sequence 11 = 7-bit sequence 3-2 txlbcdlen[1:0] r/w 0 transmit loopback code length determines transmit loopback code length. 00 = 4-bit sequence 01 = 5-bit sequence 10 = 6-bit sequence 11 = 7-bit sequence 1 framed r 0 framed loopback code selects either framed or unframed loopback code operation. 0 = unframed 1 = framed 0 autoenb r/w 0 loopback automatically enables loopback automatically. 0 = automatic loopback is disabled 1 = automatic loopback is enabled t able 52: t ransmit l oopback c oder r egister register 31 transmit loopback coder register (tlcr) 0xn125 b it f unction t ype d efault d escription -o peration 7-1 txlbc[6:0] r/w 1010101 transmit loopback code determines the transmit loopback coding sequence. 0 txlbcenb r/w 0 transmit loopback code enable enables loopback code generation. 0 = transmit loopback code is disabled. 1 = transmit loopback code is enabled
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 75 t able 53: t ransmit l oopback a ctivation c ode r egister register 32 receive loopback activation code register (rlacr) 0xn126 b it f unction t ype d efault d escription -o peration 7-1 rxlbac[6:0] r/w 1010101 receive activation loopback code determines the receive activation loopback coding sequence. 0 rxlbacenb r/w 0 receive activation loopback code enable enables receive loopback code activation detection. 0 = receive loopback code activation detection is disabled. 1 = receive loopback code activation detection is enabled t able 54: t ransmit l oopback d eactivation c ode r egister register 33 receive loopback deactivation code register (rldcr) 0xn127 b it f unction t ype d efault d escription -o peration 7-1 rxlbdc[6:0] r/w 1010101 receive deactivation loopback code determines the receive deactivation loopback coding sequence. 0 rxlbdcenb r/w 0 receive deactivation loopback code enable enables receive loopback code deactivation detection. 0 = receive loopback code deactivation detection is disabled. 1 = receive loopback code deactivation detection is enabled
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 76 t able 55: t ransmit sa s elect r egister register 34 t ransmit sa s elect r egister (tsasr) 0xn130 b it f unction t ype d efault d escription -o peration 7 txsa8sel r/w 0 sa8 bit determines whether sa8 is from serial input or register. 0 = serial input. 1 = sa8 register. 6 txsa7sel r/w 0 sa7 bit select determines whether sa7 is from serial input or register. 0 = serial input. 1 = sa7 register 5 txsa6sel r/w 0 sa6 bit select determines whether sa6 is from serial input or register. 0 = serial input. 1 = sa6 register 4 txsa5sel r/w 0 sa5 bit select determines whether sa5 is from serial input or register. 0 = serial input. 1 = sa5 register 3 txsa4sel r/w 0 sa4 bit select determines whether sa4 is from serial input or register. 0 = serial input. 1 = sa4 register 2 lb1enb r/w 0 loopback 1 auto enable local loopback is activated while the followings happened from the transmit serial input. sa5 = 0 and sa6 = 1111 occur for 8 consecutive times. a = 1 1 lb2enb r/w 0 loopback 2 auto enable local loopback is activated while the followings happened from the transmit serial input. sa5 = 0 and sa6 = 1010 occur for 8 consecutive times. a = 1 0 lbrenb r/w 0 loopback release enable local loopback is released while the followings happened from the transmit serial input. sa5 = 0 and sa6 = 0000 occur for 8 consecutive times.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 77 the following table demonstrates the conditions on the receive side which trigger the actions while these bits are enabled. n ote : a will be and with the value generated from yellow alarm control. t able 56: t ransmit sa a uto c ontrol r egister 1 register 35 t ransmit sa a uto c ontrol r egister 1 (tsacr1) 0xn131 b it f unction t ype d efault d escription -o peration 7 loslfa_1_enb r/w 0 los/lfa 1 auto transmit 6 los_1_enb r/w 0 los 1 auto transmit 5 loslfa_2_enb r/w 0 los/lfa 2 auto transmit 4 loslfa_3_enb r/w 0 los/lfa 3 auto transmit 3 loslfa_4_enb r/w 0 los/lfa 4 auto transmit 2 nop_enb r/w 0 no power auto transmit 1 nop_loslfa_enb r/w 0 no power and los/lfa auto transmit 0 los_2_enb r/w 0 los 3 auto transmit t able 57: c onditions on r eceive side w hen tsacr1 bits a re enabled c onditions a ctions - sending pattern c omments a s a 5 s a 6 loslfa_1_enb: loss of signal or loss of frame alignment x 1 0000 los/lfa at te (fc2) los_1_enb: loss of signal 1 1 1110 los (fc3) loslfa_2_enb: los or lfa 1 0 0000 los/lfa (fcl) loslfa_3_enb: los or lfa 0 1 1100 los/lfa (fc4) loslfa_4_enb: los or lfa 0 1 1110 los/lfa (fc3&fc4) nop_enb: loss of power 0 1 1000 loss of power at nt1 nop_loslfa_enb: loss of power and los or lfa 1 1 1000 loss of power and los/lfa los_2_enb: los auxp pattern los (fc1). transmit auxp pattern
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 78 the following table demonstrates the conditions on receive side which trigger the actions while these bit are enabled. t able 58: t ransmit sa a uto c ontrol r egister 2 register 36 t ransmit sa s elect r egister (tsacr2) 0xn132 b it f unction t ype d efault d escription -o peration 7 ais_1_enb r/w 0 ais reception 6 ais_2_enb r/w 0 ais reception 5 reserved - - reserved 4 reserved - - reserved 3-2 crcrep_enb r/w 0 crc report 1 crcdet_enb r/w 0 crc detection 0 crcrec/det_enb r/w 0 crc report and detect t able 59: c onditions on r eceive side w hen tsacr1 bits enabled c onditions a ctions - sending pattern for as a 5s a 6e ais_1_enb 1 1 1111 x ais_2_enb 0 1 1111 x crcrep_enb = 01, crc reported (e = 0) 0 1 0000 0 crcrep_enb = 10, crc reported 0 0 0000 0 crcrep_enb = 11, crc reported 0 1 0001 1 crcdet_enb 0 1 0010 1 crcdet/rep_enb 0 1 0011 1 t able 60: t ransmit sa4 r egister register 37 t ransmit sa4 r egister (tsa4r) 0xn133 b it f unction t ype d efault d escription -o peration 7-0 txsa4[7:0] r/w 11111111 sa4 the content of this register sources the transmit sa4 bits while txsa4enb (register 0xn10ah) is 1 and txsa4sel (register 0xn130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 79 t able 61: t ransmit sa5 r egister register 38 t ransmit sa5 r egister (tsa5r) 0xn134 b it f unction t ype d efault d escription -o peration 7-0 txsa5[7:0] r/w 11111111 sa5 the content of this register sources the transmit sa5 bits while txsa5enb (register 0xn10ah) is 1 and txsa5sel (register 0xn130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc. t able 62: t ransmit sa6 r egister register 39 t ransmit sa6 r egister (tsa6r) 0xn135 b it f unction t ype d efault d escription -o peration 7-0 txsa6[7:0] r/w 11111111 sa6 the content of this register sources the transmit sa6 bits while txsa6enb (register 0xn10ah) is 1 and txsa6sel (register 0xn130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc. t able 63: t ransmit sa7 r egister register 40 t ransmit sa7 r egister (tsa7r) 0xn136 b it f unction t ype d efault d escription -o peration 7-0 txsa7[7:0] r/w 11111111 sa7 the content of this register sources the transmit sa7 bits while txsa7enb (register 0xn10ah) is 1 and txsa7sel (register 0xn130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc. t able 64: t ransmit sa8 r egister register 41 t ransmit sa8 r egister (tsa8r) 0xn137 b it f unction t ype d efault d escription -o peration 7-0 txsa8[7:0] r/w 11111111 sa8 the content of this register sources the transmit sa8 bits while txsa8enb (register 0xn10ah) is 1 and txsa8sel (register 0xn130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 80 t able 65: r eceive s a 4 r egister register 42 r eceive s a 4 r egister (rsa4r) 0xn13b b it f unction t ype d efault d escription -o peration 7-0 rxsa4[7:0] ro 11111111 sa4 the content of this register stores the received sa4 bits if rxsa4enb (regis- ter 0xn10ch) is 1. bit 7 is received in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc. t able 66: r eceive s a 5 r egister register 43 r eceive s a 5 r egister (rsa5r) 0xn13c b it f unction t ype d efault d escription -o peration 7-0 rxsa5[7:0] ro 11111111 sa5 the content of this register stores the received sa5 bits if rxsa5enb (regis- ter 0xn10ch) is 1. bit 7 is received in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc. t able 67: r eceive s a 6 r egister r egister 44 r eceive s a 6 r egister (rsa6r) 0 x n13d b it f unction t ype d efault d escription -o peration 7-0 rxsa6[7:0] ro 11111111 sa6 the content of this register stores the received sa6 bits if rxsa6enb (regis- ter 0xn10ch) is 1. bit 7 is received in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc. t able 68: r eceive s a 7 r egister r egister 45 r eceive s a 7 r egister (rsa7r) 0 x n13e b it f unction t ype d efault d escription -o peration 7-0 rxsa7[7:0] ro 11111111 sa7 the content of this register stores the received sa7 bits if rxsa7enb (regis- ter 0xn10ch) is 1. bit 7 is received in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc. t able 69: r eceive s a 8 r egister r egister 46 r eceive s a 8 r egister (rsa8r) 0 x n13f b it f unction t ype d efault d escription -o peration 7-0 rxsa8[7:0] ro 11111111 sa8 the content of this register stores the received sa8 bits if rxsa8enb (regis- ter 0xn10ch) is 1. bit 7 is received in frame 2 of the crc-4 multiframe, bit 6 is in frame 4, etc.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 81 t able 70: d ata l ink c ontrol r egister r egister 19 d ata l ink c ontrol r egister 2 (dlcr2) h ex a ddress : 0 x n143 b it f unction t ype d efault d escription -o peration 7 slc-96 r/w 0 slc ? 96 enable, 6 bit for esf if slc ? 96 framing is selected, setting this bit high will enable slc ? 96 data link transmission; otherwise, the regular sf framing bits are transmitted. in esf framing mode, setting this bit high will cause facility data link to trans- mit/receive slc ? 96-like message. 6 mosa r/w 0 mos abort enable/disable select this read/write bit-field is used to configure the transmit hdlc2 controller to automatically transmit an abort sequence anytime it transitions from the mos mode to the bos mode. 0 = transmit hdlc2 controller inserts an mos abort sequence if the mos message is interrupted 1 = prevents transmit hdlc2 controller from inserting an mos abort sequence. 5 rx_fcs_dis r/w 0 receive fcs verification disable enables/disables receive hdlc2 controllers computation and verification of the fcs value in the incoming lapd message frame 0 = verifies fcs value of each mos frame. 1 = does not verify fcs value of each mos frame. 4autorx r/w 0 auto receive lapd message configures the rx hdlc2 controller to discard any incoming lapd mes- sage frame that exactly match which is currently stored in the rx hdlc2 buffer. 0 = disabled 1 = enables this feature. 3 tx_abort r/w 0 transmit abort configures the tx hdlc2 controller to transmit an abort sequence (string of 7 or more consecutive 1s) to the remote terminal. 0 = tx hdlc2 controller operates normally 1 = tx hdlc2 controller inserts an abort sequence into the data link channel. 2 tx_idle r/w 0 transmit idle (flag sequence byte) configures the tx hdlc2 controller to transmit a string of flag sequence octets (0x7e) in the data link channel to the remote terminal. 0 = tx hdlc2 controller resumes transmitting data to the remote terminal 1 = tx hdlc2 controller transmits a string of flag sequence bytes. n ote : this bit-field is ignored if the tx hdlc2 controller is operating in the bos mode - bit-field 0(mos/bos) within this register is set to 0. 1 tx_fcs_en r/w 0 transmit lapd message with fcs configure hdlc2 controller to include/not include fcs octets in the out- bound lapd message frames. 0 = does not include fcs octets into the outbound lapd message frame. 1 = inserts fcs octets into the outbound lapd message frame. n ote : this bit-field is ignored if the transmit hdlc2 controller has been configured to operate in the bos mode. 0 mos/bos r/w 0 message oriented signaling/bit oriented signaling select specifies whether the txrx hdlc2 controller will be transmitting and receiving lapd message frames (mos) or bit oriented signal (bos) mes- sages. 0 = tx/rx hdlc2 controller transmits and receives bos messages. 1 = tx/rx hdlc2 controller transmits and receives mos messages.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 82 t able 71: t ransmit d ata l ink b yte c ount r egister r egister 20 t ransmit d ata l ink b yte c ount r egister 2 (tdlbcr2) h ex a ddress : 0 x n144 b it f unction t ype d efault d escription -o peration 7 bufaval//bufsel r/w 0 transmit hdlc2 buffer available/buffer select specifies which of the two tx hdlc2 buffers that the tx hdlc2 controller should read from to generate the next outbound hdlc2 message. 0 = transmits message data residing in tx hdlc2 buffer 0. 1 = transmits message data residing in tx hdlc2 buffer 1. n ote : if one of these tx hdlc2 buffers contain a message which has yet to be completely read-in and processed for transmission by the tx hdlc2 controller, then this bit-field will automatically reflect the value corresponding to the available buffer. changing this bit-field to the in-use buffer is not per- mitted. 6 tdlbc6 r/w 0 transmit hdlc2 message - byte count depends on whether an mos or bos message is being transmitted to the remote terminal equipment if bos message is being transmitted : these bit fields contain the number of repetitions the bos message must be transmitted before the tx hdlc2 controller generates the txeot interrupt and halts transmission. if these fields are set to 00000000, then the bos message will be transmitted for an indefinite number of times. if mos message is being transmitted: these bit fields contain the length, in number of octets, of the message to be transmitted. 5 tdlbc5 r/w 0 4 tdlbc4 r/w 0 3 tdlbc3 r/w 0 2 tdlbc2 r/w 0 1 tdlbc1 r/w 0 0 tdlbc0 r/w 0 t able 72: r eceive d ata l ink b yte c ount r egister r egister 21 r eceive d ata l ink b yte c ount r egister 2 (rdlbcr2) h ex a ddress : 0 x n145 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc2 buffer-pointer identifies which rxhdlc2 buffer contains the newly received hdlc2 mes- sage. 0 = hdlc2 message is stored in rx hdlc2 buffer 0. 1 = hdlc2 message is stored in rx hdlc2 buffer 1. 6 rdlbc6 r/w 0 re ceive hdlc message - byte count in mos mode these seven bit-fields contain the size in bytes of the hdlc2 message that has been extracted and written into the rx hdlc2 buffer. in bos mode these bits should be set to the value of the message repetitions before each receive interrupt. if ithey are set to 0, no rxeot interrupt will be generated. 5 rdlbc5 r/w 0 4 rdlbc4 r/w 0 3 rdlbc3 r/w 0 2 rdlbc2 r/w 0 1 rdlbc1 r/w 0 0 rdlbc0 r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 83 t able 73: d ata l ink c ontrol r egister r egister 19 d ata l ink c ontrol r egister 3 (dlcr3) h ex a ddress : 0 x n153 b it f unction t ype d efault d escription -o peration 7 slc-96 r/w 0 slc ? 96 enable, 6 bit for esf if slc ? 96 framing is selected, setting this bit high will enable slc ? 96 data link transmission; otherwise, the regular sf framing bits are transmitted. in esf framing mode, setting this bit high will cause facility data link to trans- mit/receive slc ? 96-like message. 6 mosa r/w 0 mos abort enable/disable select this read/write bit-field is used to configure the transmit hdlc3 controller to automatically transmit an abort sequence anytime it transitions from the mos mode to the bos mode. 0 = transmit hdlc3 controller inserts an mos abort sequence if the mos message is interrupted 1 = prevents transmit hdlc3 controller from inserting an mos abort sequence. 5 rx_fcs_dis r/w 0 receive fcs verification disable enables/disables receive hdlc3 controllers computation and verification of the fcs value in the incoming lapd message frame 0 = verifies fcs value of each mos frame. 1 = does not verify fcs value of each mos frame. 4autorx r/w 0 auto receive lapd message configures the rx hdlc3 controller to discard any incoming lapd mes- sage frame that exactly match which is currently stored in the rx hdlc3 buffer. 0 = disabled 1 = enables this feature. 3 tx_abort r/w 0 transmit abort configures the tx hdlc3 controller to transmit an abort sequence (string of 7 or more consecutive 1s) to the remote terminal. 0 = tx hdlc3 controller operates normally 1 = tx hdlc3 controller inserts an abort sequence into the data link channel. 2 tx_idle r/w 0 transmit idle (flag sequence byte) configures the tx hdlc3 controller to transmit a string of flag sequence octets (0x7e) in the data link channel to the remote terminal. 0 = tx hdlc3 controller resumes transmitting data to the remote terminal 1 = tx hdlc3 controller transmits a string of flag sequence bytes. n ote : this bit-field is ignored if the tx hdlc3 controller is operating in the bos mode - bit-field 0(mos/bos) within this register is set to 0. 1 tx_fcs_en r/w 0 transmit lapd message with fcs configure hdlc3 controller to include/not include fcs octets in the out- bound lapd message frames. 0 = does not include fcs octets into the outbound lapd message frame. 1 = inserts fcs octets into the outbound lapd message frame. n ote : this bit-field is ignored if the transmit hdlc3 controller has been configured to operate in the bos mode. 0 mos/bos r/w 0 message oriented signaling/bit oriented signaling select specifies whether the txrx hdlc3 controller will be transmitting and receiving lapd message frames (mos) or bit oriented signal (bos) mes- sages. 0 = tx/rx hdlc3 controller transmits and receives bos messages. 1 = tx/rx hdlc3 controller transmits and receives mos messages.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 84 t able 74: t ransmit d ata l ink b yte c ount r egister r egister 20 t ransmit d ata l ink b yte c ount r egister 3 (tdlbcr3) h ex a ddress : 0 x n154 b it f unction t ype d efault d escription -o peration 7 bufaval//bufsel r/w 0 transmit hdlc3 buffer available/buffer select specifies which of the two tx hdlc3 buffers that the tx hdlc3 controller should read from to generate the next outbound hdlc3 message. 0 = transmits message data residing in tx hdlc3 buffer 0. 1 = transmits message data residing in tx hdlc3 buffer 1. n ote : if one of these tx hdlc3 buffers contain a message which has yet to be completely read-in and processed for transmission by the tx hdlc3 controller, then this bit-field will automatically reflect the value corresponding to the available buffer. changing this bit-field to the in-use buffer is not per- mitted. 6 tdlbc6 r/w 0 transmit hdlc3 message - byte count depends on whether an mos or bos message is being transmitted to the remote terminal equipment if bos message is being transmitted : these bit fields contain the number of repetitions the bos message must be transmitted before the tx hdlc3 controller generates the txeot interrupt and halts transmission. if these fields are set to 00000000, then the bos message will be transmitted for an indefinite number of times. if mos message is being transmitted: these bit fields contain the length, in number of octets, of the message to be transmitted. 5 tdlbc5 r/w 0 4 tdlbc4 r/w 0 3 tdlbc3 r/w 0 2 tdlbc2 r/w 0 1 tdlbc1 r/w 0 0 tdlbc0 r/w 0 t able 75: r eceive d ata l ink b yte c ount r egister r egister 21 r eceive d ata l ink b yte c ount r egister 3 (rdlbcr3) h ex a ddress : 0 x n155 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc3 buffer-pointer identifies which rxhdlc3 buffer contains the newly received hdlc3 mes- sage. 0 = hdlc3 message is stored in rx hdlc3 buffer 0. 1 = hdlc3 message is stored in rx hdlc3 buffer 1. 6 rdlbc6 r/w 0 re ceive hdlc message - byte count in mos mode these seven bit-fields contain the size in bytes of the hdlc3 message that has been extracted and written into the rx hdlc3 buffer. in bos mode these bits should be set to the value of the message repetitions before each receive interrupt. if ithey are set to 0, no rxeot interrupt will be generated. 5 rdlbc5 r/w 0 4 rdlbc4 r/w 0 3 rdlbc3 r/w 0 2 rdlbc2 r/w 0 1 rdlbc1 r/w 0 0 rdlbc0 r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 85 t able 76: d evice id r egister r egister 47 d evice id r egister (devid) 0 x n1fe b it f unction t ype d efault d escription -o peration 7-0 devid[7:0] ro 00110100 devid this register is used to identify the XRT86L34 framer/liu. the contents of this regitster are 0x35h.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 86 t able 77: t ransmit c hannel c ontrol r egister 0 to 31 e1 m ode r egister 49-80 e1 t ransmit c hannel c ontrol r egister 0-31 (tccr 0-31) h ex a ddress : 0xn300 to 0 x n31f b it m ode f unction t ype d efault d escription -o peration 7-6 e1 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be activated. 00 = lapd1 01 = lapd2 10 = txde[1:0] will determine the data source for the d/e time slots 11 = lapd3 5-4 reserved - - reserved 3-0 txcond(3:0) r/w 0 transmit channel conditioning for timeslot 0 to 31 replaces the contents of timeslot 1 octet (pcm data within the next out- bound frame) with signaling codes as follows. 0x0 = contents of timeslot octet unchanged prior to transmission to remote terminal equipment. contents are transmitted without modification as received via the txser_n input pin. 0x1 = all 8 bits of the timeslot octet are inverted (1s complement) prior to transmission to the remote terminal equipment. this selection is equivalent to executing the following logic operation with each timeslot 1 octet: tx_time_slot_octet=(te_time_slot_octet) xor 0xff 0x2 = the even bits of the timeslot octet are inverted prior to trans mission to the remote terminal equipment. this selection is equivalent to executing the following logic operation: tx_time_slot_octet=(te_time_slot_octet) xor 0xaa 0x3 = the odd bits of the time slot octet are inverted prior to trans mission to the remote terminal equipment. this selection is equivalent to executing the following logic operation: tx_time_slot_octet=(te_time_slot_octet) xor 0x55 0x4 = the contents of the timeslot octet will be substituted with the 8 -bit value in programmable user code register, prior to transmission to the remote terminal equipment. 0x5 = the contents of the timeslot octet will be substituted with the value 0xff (busy) prior to transmission to the remote terminal equipment. 0x6 = the contents of the timeslot octet will be substituted with the value 0xd5 (vacant 0v) prior to transmission to the remote terminal equipment. 0x7 = the busy ts(111#_####) code replaces the input data for transmission. (##### is timeslot number.) 0x8 = the busy 00 code replaces the input data for transmission 0x9 = the a-law digital milliwatt pattern replaces the input data for transmission. 0xa = the m -law digital milliwatt pattern replaces the input data for transmission. 0xb = the msb (bit 1) of input data is inverted. 0xc = all input data except msb is inverted. 0xd = prbs, qrts/x 15 + x 14 + 1. 0xe = the input pcm data bit are unchanged. 0xf = this is a d/e time slots. see transmit signaling and data link select register. (tsdlsr)
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 87 t able 78: t ransmit c hannel c ontrol r egister 0 to 31 t1 m ode r egister 49-80 t1 t ransmit c hannel c ontrol r egister 0-31 (tccr 0-31) h ex a ddress : 0 x n300 to 0 x n31f b it f unction t ype d efault d escription -o peration 7-6 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be activated. 00 = lapd1 01 = lapd2 10 = txde[1:0] will determine the data source for the d/e time slots 11 = lapd3 5 - 4 txzero[1:0] r/w 00 selects type of zero suppression these bits select the zero code suppression used. 00 = no zero code suppression is used. 01 = at&t bit 7 stuffing is used. 10 = gte zero code suppression is used. bit 8 is stuffed in non-signaling frame. otherwise, bit 7 is stuffed in signaling frame if the signaling bit is zero. 11 = dds zero code suppression is applied where 0x98 replaces the input dat a.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 88 3-0 txcond(3:0) r/w 0 transmit channel conditioning for timeslot 0 to 23 replaces the contents of timeslot 1 octet (pcm data within the next out- bound frame) with signaling codes as follows. 0x0 = contents of timeslot octet unchanged prior to transmission to remote terminal equipment. contents are transmitted without modification as received via the txser_n input pin. 0x1 = all 8 bits of the timeslot octet are inverted (1s complement) prior to transmission to the remote terminal equipment. this selection is equivalent to executing the following logic operation with each timeslot 1 octet: tx_time_slot_octet=(te_time_slot_octet) xor 0xff 0x2 = the even bits of the timeslot octet are inverted prior to trans mission to the remote terminal equipment. this selection is equivalent to executing the following logic operation: tx_time_slot_octet=(te_time_slot_octet) xor 0xaa 0x3 = the odd bits of the time slot octet are inverted prior to trans mission to the remote terminal equipment. this selection is equivalent to executing the following logic operation: tx_time_slot_octet=(te_time_slot_octet) xor 0x55 0x4 = the contents of the timeslot octet will be substituted with the 8 -bit value in programmable user code register, prior to transmission to the remote terminal equipment. 0x5 = the contents of the timeslot octet will be substituted with the value 0xff (busy) prior to transmission to the remote terminal equipment. 0x6 = the contents of the timeslot octet will be substituted with the value 0xd5 (vacant 0v) prior to transmission to the remote terminal equipment. 0x7 = the busy ts(111#_####) code replaces the input data for transmission. (##### is timeslot number.) 0x8 = the busy 00 code replaces the input data for transmission 0x9 = the a-law digital milliwatt pattern replaces the input data for transmission. 0xa = the m -law digital milliwatt pattern replaces the input data for transmission. 0xb = the msb (bit 1) of input data is inverted. 0xc = all input data except msb is inverted. 0xd = prbs, qrts/x 15 + x 14 + 1. 0xe = the input pcm data bit are unchanged. 0xf = this is a d/e time slots. see transmit signaling and data link select register. (tsdlsr) t able 79: u ser c ode r egister 0 to 31 r egister 81-112 u ser c ode r egister 0 (ucr 0-31) h ex a ddress : 0 x n320 to 0 x n33f b it f unction t ype d efault d escription -o peration 7-0 r/w 0 programmable user code. t able 78: t ransmit c hannel c ontrol r egister 0 to 31 t1 m ode r egister 49-80 t1 t ransmit c hannel c ontrol r egister 0-31 (tccr 0-31) h ex a ddress : 0 x n300 to 0 x n31f b it f unction t ype d efault d escription -o peration
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 89 t able 80: t ransmit s ignaling c ontrol r egister x - e1 m ode r egister 113-144 - e1 t ransmit s ignaling c ontrol r egister x (tscr) h ex a ddress : 0 x n340 to 0 xn 35f b it f unction t ype d efault d escription -o peration 7 a (x) r/w 0 (1) signaling bit a or x bit a,b,c,d: these are programmable signaling information. note: time slot 16 of frame 0 is controlled by tscr0 (for 0 bits) and tscr16 (for xyxx bits). 6 b (y) r/w 0 (0) signaling bit b or y bit 5 c (x) r/w 0 (1) signaling bit c or x bit 4 d (x) r/w 0 (1) signaling bit d or x bit 3 reserved - - reserved 2 reserved - - reserved 1 txsigsrc[1] r/w 0 channel signaling control these bits determine the selection of signaling conditioning. 00 = no signaling data is inserted into input pcm data (passthrough). 01 = signaling data is inserted from tscrs. 10 = signaling data is inserted from txoh input while txmuxen=0 and tximode[1:0]=00, otherwise is inserted from txsig input. 11 = no signaling. for xyxx bits only, x's are from tscr and y is the alarm condition. 0 txsigsrc[0] r/w 0 t able 81: t ransmit s ignaling c ontrol r egister x - t1 m ode r egister 113-144 - t1 t ransmit s ignaling c ontrol r egister x (tscr) (0-23) h ex a ddress : 0 x n340 to 0 xn 35f b it f unction t ype d efault d escription -o peration 7 a (x) r/w 0 (1) signaling bit a a,b,c,d: these are programmable signaling information. 6 b (y) r/w 0 (0) signaling bit b 5 c (x) r/w 0 (1) signaling bit c 4 d (x) r/w 0 (1) signaling bit d 3 reserved - - reserved 2 rob_enb r/w 0 robbed-bit signaling enable this bit enables robbed-bit signaling transmission. 0 = robbed-bit is disabled. 1 = robbed-bit is enabled 1 txsigsrc[1] r/w 0 channel signaling control these bits determine the selection of signaling conditioning. 00 = no signaling data is inserted into input pcm data. 01 = signaling data is inserted from tscrs. 10 = signaling data is inserted from txsig input. 11 = no signaling. 0 txsigsrc[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 90 t able 82: r eceive c hannel c ontrol r egister x (rccr 0-31) - e1 m ode r egister 145-176 e1 r eceive c hannel c ontrol r egister x (rccr 0-31) h ex a ddress : 0 x n360 to 0 xn 37f b it f unction t ype d efault d escription -o peration 7-6 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be activated. 00 = lapd1 01 = lapd2 10 = rxde[1:0] will determine the data source for the d/e time slots 11 = lapd3 5-4 reserved - - reserved 3 rxcond[3] r/w 0 selects data conditioning these bits determines the type of data condition applying to input pcm data. 0x0 = the input pcm data is unchanged. 0x1 = all 8 bits of the pcm channel data are inverted. 0x2 = the even bits of input data are inverted. 0x3 = the odd bits of input data are inverted. 0x4 = data in user code register shown in table 3-27 replaces the input data. 0x5 = busy ff code (0xff)) replaces the input data. 0x6 = busy 0vcode (0xd5) replaces the input data. 0x7 = busy ts (111#_####) replaces the input data; ##### is timeslot number. 0x8 = busy 00 (0x00) replaces the input data. 0x9 = the a-law digital milliwatt pattern replaces the input data. 0xa = the m-law digital milliwatt pattern replaces the input data. 0xb = the msb (bit 1) of input data is inverted. 0xc = all input data except msb is inverted. 0xd = prbs, qrts/x 15 + x 14 +1. 0xe = the input pcm data bit are unchanged. 0xf = this is a d/e time slots. see receive signaling data link select register 12. (rs&dlsr) 2 rxcond[2] r/w 0 1 rxcond[1] r/w 0 0 rxcond[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 91 t able 83: r eceive c hannel c ontrol r egister x (rccr 0-23) - t1 m ode r egister 145-176 - t1 r eceive c hannel c ontrol r egister x (rccr 0-23) h ex a ddress : 0 x n360 to 0 xn 37f b it f unction t ype d efault d escription -o peration 7-6 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be activated. 00 = lapd1 01 = lapd2 10 = rxde[1:0] will determine the data source for the d/e time slots 11 = lapd3 5 rxzero[1] r/w 0 selects type of zero suppression these bits select the zero code suppression used. 00 = no zero code suppression is used. 01 = at&t bit 7 stuffing is used. 10 = gte zero code suppression is used. bit 8 is stuffed in non-signaling frame. otherwise, bit 7 is stuffed in signaling frame if the signaling bit is zero. 11 = dds zero code suppression is applied. 4 rxzero[0] r/w 0 3 rxcond[3] r/w 0 selects data conditioning these bits determines the type of data condition applying to input pcm data. 0x0 = the input pcm data is unchanged. 0x1 = all 8 bits of the pcm channel data are inverted. 0x2 = the even bits of input data are inverted. 0x3 = the odd bits of input data are inverted. 0x4 = data in user (idle) code register (table 3?49) replaces the input data for transmission. 0x5 = busy code (0x7f)) replaces the input data for transmission. 0x6 = vacant code (0xff) replaces the input data for transmission. 0x7 = busy ts (111#_####) replaces the input data for transmission; ##### is timeslot number. 0x8 = moof (0x1a) replaces the input data for transmission. 0x9 = the a-law digital milliwatt pattern replaces the input data. 0xa = the m-law digital milliwatt pattern replaces the input data. 0xb = the msb (bit 1) of input data is inverted. 0xc = all input data except msb is inverted. 0xd = prbs, qrts/x 15 + x 14 + 1. 0xe = the input pcm data bit are unchanged. 0xf = this is a d/e time slots. see receive signaling data link select register 12. (rs&dlsr) 2 rxcond[2] r/w 0 1 rxcond[1] r/w 0 0 rxcond[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 92 t able 84: r eceive u ser c ode r egister x (rucr 0-31) r egister 177-208 r eceive u ser c ode r egister x (rucr 0-31) h ex a ddress : 0 x n380 to 0 xn 39f b it f unction t ype d efault d escription -o peration 7 rxuser[7] r/w 1 programmable user code 6 rxuser[6] r/w 1 5 rxuser[5] r/w 1 4 rxuser[4] r/w 1 3 rxuser[3] r/w 1 2 rxuser[2] r/w 1 1 rxuser[1] r/w 1 0 rxuser[0] r/w 1 t able 85: r eceive s ignaling c ontrol r egister x (rscr) (0-31) r egister 209-240 r eceive s ignaling c ontrol r egister x (rscr) (0-31) h ex a ddress : 0 x n3a0 to 0 xn 3bf b it f unction t ype d efault d escription -o peration 6 sigc_enb r/w 0 signaling substitution enable this bit enables signaling substitution. 0 = substitution is disabled. 1 = substitution is enabled. 5 oh_enb r/w 0 signaling oh interface output enable this bit enables outputting signaling through overhead interface. the infor- mation in receive signaling array registers is output to receive overhead interface. 0 = output is disabled. 1 = output is enabled. 4 deb_enb r/w 0 per-channel debounce enable this bit enables signaling debounce feature. 0 = debounce is disabled. 1 = debounce is enabled. 3 rxsigc[1] r/w 0 signaling conditioning these bits control per-channel signaling substitution. 00 = substitutes all signaling bits with one. 01 = enables 16-code (sig16-a,b,c,d) signaling substitution. 10 = enables 4-code (sig4-a,b) signaling substitution. 11 = enables 2-code (sig2-a) signaling substitution. 2 rxsigc[0] r/w 0 1 rxsige[1] r/w 0 signaling extraction. these bits determines the extracted signaling coding. 00 = no signaling is extracted. 01 = extracts 16-code signaling. 10 = extracts 4-code signaling. 11 = extracts 2-code signaling. 0 rxsige[0] r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 93 t able 86: r eceive s ubstitution s ignaling r egister (rssr) e1 m ode r egister 241-272 e1 m ode r eceive s ubstitution s ignaling r egister (rssr) h ex a ddress 0 x n3c0 to 0 xn 3df b it f unction t ype d efault d escription -o peration 6 sig2-a r/w 0 2-code signaling a 5 sig4-b r/w 0 4-code signaling b 4 sig4-a r/w 0 4-code signaling a 3 sig16-d r/w 0 16-code signaling d 2 sig16-c r/w 0 16-code signaling c 1 sig16-b r/w 0 16-code signaling b 0 sig16-a r/w 0 16-code signaling a t able 87: lapd b uffer 0 c ontrol r egister r egister 241-272 lapd b uffer 0 c ontrol r egister (lapdbcr0) h ex a ddress : 0 x n600 to 0 xn 660 b it f unction t ype d efault d escription -o peration 7-0 lapd buffer 0 r/w 0 lapd buffer 0 (96-bytes) this register is used to transmit and receive lapd messages within buffer 0 of the hdlc controller chosen in the lapd select register (0xn11b). when writing to buffer 0, the message is inserted into the outgoing lapd frame and the data cannot be retrieved. after detecting the rx end of transfer interrupt (rxeot), the extracted lapd message is available to be read. n ote : when writing or reading from buffer 0, the register is auto- matically incremented such that 0xn600 can be written to or read from continuously. t able 88: lapd b uffer 1 c ontrol r egister r egister 241-272 lapd b uffer 0 c ontrol r egister (lapdbcr1) h ex a ddress : 0 x n700 to 0 xn 760 b it f unction t ype d efault d escription -o peration 7-0 lapd buffer 1 r/w 0 lapd buffer 1 (96-bytes) this register is used to transmit and receive lapd messages within buffer 1 of the hdlc controller chosen in the lapd select register (0xn11b). when writing to buffer 1, the message is inserted into the outgoing lapd frame and the data cannot be retrieved. after detecting the rx end of transfer interrupt, the extracted lapd mes- sage is available to be read. n ote : when writing or reading from buffer 1, the register is auto- matically incremented such that 0xn700 can be written to or read from continuously.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 94 t able 89: r eceive s ubstitution s ignaling r egister (rssr) t1 m ode r egister 241-272 - t1 r eceive s ubstitution s ignaling r egister (rssr) h ex a ddress : 0 x n3c0 to 0 xn 3df b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3 sig16-a, 4-a, 2-a r/w 0 16-code signaling a 4-code signaling a 2-code signaling a 2 sig16-b, 4-b, 2-a r/w 0 16-code signaling b 4-code signaling b 2-code signaling a 1 sig16-c, 4-a, 2-a r/w 0 16-code signaling c 4-code signaling a 2-code signaling a 0 sig16-d, 4-b, 2-a r/w 0 16-code signaling d 4-code signaling b 2-code signaling a t able 90: r eceive s ignaling a rray r egister 0 to 31 r egister 273-304 r eceive s ignaling a rray r egister (rsar 0-31) h ex a ddress : 0xn500 to 0 x n51f b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3a r/w 0 reflects the most recently received signaling value (a,b,c,d) asso- ciated with timeslot 0 to 31. n ote : the content of this register only has meaning when the framer is using channel associated signaling. 2b r/w 0 1c r/w 0 0d r/w 0 t able 91: pmon t1/e1 r eceive l ine c ode ( bipolar ) v iolation c ounter r egister 305 pmon r eceive l ine c ode ( bipolar ) v iolation c ounter (rlcvcmsb) h ex a ddress : 0 x n900 b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3-0 rxlcv count - high byte rur 0 these four reset upon read bits along with pmon receive line code vio- lation counter - lsb, provides a 12-bit representation of the number of line code violations that have been detected by the receive framer block since the last read of these registers. lower 8 bits. this register contains the lowest four bits within this 12 bit expression t able 92: pmon t1/e1 r eceive l ine c ode ( bipolar ) v iolation c ounter r egister 306 pmon r eceive l ine c ode ( bipolar ) v iolation c ounter (rlcvclsb) h ex a ddress : 0 x n901 b it f unction t ype d efault d escription -o peration 7-0 rxlcv count - low byte rur 0 these eight reset upon read bits along with pmon receive line code violation counter - msb, provides 12-bit representation of the number of line code violations that have been detected by receive framer block since the last read of these registers. upper 4 bits. this register contains the upper 8 bits within this 12 bit expression.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 95 . t able 93: pmon t1/e1 r eceive f raming a lignment b it e rror c ounter r egister 307 pmon r eceive f raming a lignment e rror c ounter (rfaeclsb) h ex a ddress : 0 x n902 b it f unction t ype d efault d escription -o peration 7-0 framing alignment error count - high byte rur 0 these eight reset upon read bits along with pmon e1 receive framing alignment bit error counter- lsb, provides a 12-bit representation of the number of framing alignment errors that have been detected by receive e1 framer number n since the last read of these registers. this register contains the upper 8bits within this 12-bit expression. t able 94: pmon t1/e1 r eceive f raming a lignment b it e rror c ounter r egister 308 pmon r eceive f raming a lignment b it e rror c ounter (rfab-ecmsb) h ex a ddress : 0 x n903 b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3-0 framing alignment error count - low byte rur 0 these four reset upon read bits along with pmon e1 receive framing alignment bit error counter- msb, provides 12-bit representation of the number of framing alignment errors that have been detected by receive e1 framer block since the last read of these register. this register contains the lowest four bits within this 12-bit expression t able 95: pmon t1/e1 r eceive s everely e rrored f rame c ounter r egister 309 pmon r eceive s everely e rrored f rame c ounter (rsefc) h ex a ddress : 0 x n904 b it f unction t ype d efault d escription -o peration 7-0 severely errored frame count rur 0 severely errored 8-bit frame accumulation counter note: a severely errored frame event is defined as the occurrence of two consecutive errored frame alignment signals that are not responsi- ble for loss of frame alignment. t able 96: pmon t1/e1 r eceive crc-4 b lock e rror c ounter - msb r egister 310 pmon r eceive s ynchronization b it b lock e rror c ounter (rsbbecmsb) h ex a ddress : 0 x n905 b it f unction t ype d efault d escription -o peration 7-0 crc-4 block error count - high byte rur 0 these eight reset upon read bits along with pmon e1 receive crc-4 block error counter - lsb, provides a 10-bit representation of the number of crc-4 block errors detected by receive e1 framer block since the last read of these registers. this register contains the upper eight bits of this 10 bit expression
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 96 t able 97: pmon t1/e1 r eceive crc-4 b lock e rror c ounter - lsb r egister 311 pmon r eceive s ynchronization b it b lock e rror c ounter (rsbbeclsb) h ex a ddress : 0 x n907 b it f unction t ype d efault d escription -o peration 7-2 reserved - - reserved 1-0 crc-4 block error count - low byte rur 0 these two reset upon read bits along with pmon e1 receive crc-4 block error counter - msb, provides a 10-bit representation of the number of crc-4 block errors that have been detected by a receive e1 framer block since the last read of these registers. this register contains the lower two bits within this 10 bit expression. note: counter contains the 10-bit synchronization bit error event. a synchro- nization bit error event is defined as a crc-4 error received. counter is dis- abled during loss of sync at either the frame/fas or esf/crc4 level, but it will not be disabled if loss of multiframe sync occurs at the cas level. t able 98: pmon t1/e1 r eceive f ar -e nd bl ock e rror c ounter - msb r egister 312 pmon r eceive f ar -e nd b lock e rror c ounter (e1rfebecmsb) h ex a ddress : 0 x n908 b it f unction t ype d efault d escription -o peration 7-0 far-end block error count - high byte rur 0 these eight reset upon read bits along with pmon e1 receive far-end block error counter - lsb, provides a 10-bit representation of the number of far end block error events that have been detected by the receive e1 framer block since the last read of these registers. this register contains the upper eight bits within this 10 bit expression. t able 99: pmon t1/e1 r eceive f ar e nd b lock e rror c ounter r egister 313 pmon r eceive f ar e nd b lock e rror c ounter (rfebeclsb) h ex a ddress : 0 x n908 b it f unction t ype d efault d escription -o peration 7-2 reserved - - reserved 1-0 far-end block error count -low byte rur 0 these two reset upon read bits along with pmon e1 receive far-end block error counter - msb, provides a 10-bit representation of the number of far end block error events that have been detected by the receive e1 framer block since the last read of these registers. this register contains the lower two bits within this 10 bit expression. note: counter contains the 10-bit far-end block error event. counter will increment once each time the received e-bit is set to zero. the counter is disabled during loss of sync at either the fas or crc-4 level and it will continue to count if loss of multiframe sync occurs at the cas level.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 97 t able 100: pmon t1/e1 r eceive s lip c ounter r egister 314 pmon r eceive s lip c ounter (rsc) h ex a ddress : 0 x n909 b it f unction t ype d efault d escription -o peration 7-0 slip count rur 0 note: counter contains the 8-bit receive buffer slip event. a slip event is defined as a replication or deletion of a t1/e1 frame by the receiving slip buffer. note: a 12 bit counter which counts the occurrence of a bipolar viola- tion on the receive data line. this counter is of sufficient length so that the probability of counter saturation over a one second interval at a 10 -3-bit error rate (ber) is less than 0.001%. t able 101: pmon t1/e1 r eceive l oss of f rame c ounter r egister 315 pmon r eceive l oss of f rame c ounter (rlfc) h ex a ddress : 0 x n90a b it f unction t ype d efault d escription -o peration 7-0 loss of frame counts rur 0 note: lofc is a count of the number of times a "loss of fas frame" has been declared. this counter provides the capability to measure an accumulation of short failure events. t able 102: pmon t1/e1 r eceive c hange of f rame a lignment c ounter r egister 316 pmon r eceive c hange of f rame a lignment c ounter (rcfac) h ex a ddress : 0 x n90b b it f unction t ype d efault d escription -o peration 7-0 cofa count rur 0 change of frame alignment accumulation counter. note: cofa is declared when the newly-locked framing is different from the one offered by off-line framer. t able 103: pmon lapd t1/e1 f rame c heck s equence e rror c ounter r egister 317 pmon lapd f rame c heck s equence e rror c ounter (fcsec) h ex a ddress : 0 x n90c b it f unction t ype d efault d escription -o peration 7-0 fcs error count rur 0 frame check sequence error accumulation counter. note: counter accumulates the times of occurrence of receive frame check sequence error detected by lapd controller.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 98 t able 104: t1/e1 prbs b it e rror c ounter msb r egister 318 t1/e1 prbs b it e rror c ounter msb h ex a ddress : 0 x n90d b it f unction t ype d efault d escription -o peration 7 prbse[15] rur 0 most significant bits of prbs bit error accumulation counter 6 prbse[14] rur 0 5 prbse[13] rur 0 4 prbse[12] rur 0 3 prbse[11] rur 0 2 prbse[10] rur 0 1 prbse[9] rur 0 0 prbse[8] rur 0 t able 105: t1/e1 prbs b it e rror c ounter lsb r egister 319 t1/e1 prbs b it e rror c ounter lsb h ex a ddress : 0 x n90e b it f unction t ype d efault d escription -o peration 7 prbse[7] rur 0 least significant byte of prbs bit error accumulation counter. 6 prbse[6] rur 0 5 prbse[5] rur 0 4 prbse[4] rur 0 3 prbse[3] rur 0 2 prbse[2] rur 0 1 prbse[1] rur 0 0 prbse[0] rur 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 99 t able 106: t1/e1 t ransmit s lip c ounter r egister 320 t1/e1 t ransmit s lip c ounter (t1/e1tsc) h ex a ddress : 0 x n90f b it f unction t ype d efault d escription -o peration 7 txslip[7] rur 0 slip accumulation counter. 6 txslip[6] rur 0 5 txslip[5] rur 0 4 txslip[4] rur 0 3 txslip[3] rur 0 2 txslip[2] rur 0 1 txslip[1] rur 0 0 txslip[0] rur 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 100 t able 107: b lock i nterrupt s tatus r egister r egister 321 b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x nb00 b it f unction t ype d efault d escription -o peration 7 sa6 ro 0 sa6 interrupt status 6lbcode ro 0 loopback code interrupt 5 rxclklos rur 0 rxclk los interrupt status indicates if framer n has experienced a loss of recovered clock interrupt since last read of this register. 0 = loss of recovered clock interrupt has not occurred since last read of this register 1 = loss of recovered clock interrupt has occurred since last read of this register. 4 onesec rur 0 one second interrupt status indicates if the XRT86L34 has experienced a one second interrupt since the last read of this register. 0 = no outstanding one second interrupts awaiting service 1 = outstanding one second interrupt awaits service 3 hdlc ro 0 hdlc block interrupt status indicates if the hdlc block has an interrupt request awaiting service. 0 = no outstanding interrupt requests awaiting service 1 = hdlc block has an interrupt request awaiting service. interrupt service routine should branch to and read data link status register (address xa,06). n ote : this bit-field will be reset to 0 after the microprocessor has performed a read to the data link status register. 2slip ro 0 slip buffer block interrupt status indicates if the slip buffer block has any outstanding interrupt requests awaiting service. 0 = no outstanding interrupts awaiting service 1 = slip buffer block has an interrupt awaiting service. interrupt service rou- tine should branch to and read slip buffer interrupt status register (address 0xxa,0x09. n ote : this bit-field will be reset to 0 after the microprocessor has performed a read of the slip buffer interrupt status register. 1 alarm ro 0 alarm & error block interrupt status indicates if the alarm & error block has any outstanding interrupts that are awaiting service. 0 = no outstanding interrupts awaiting service 1 = alarm & error block has an interrupt awaiting service. interrupt serstatus register (address xa,02) n ote : this bit-field will be reset to 0 after the microprocessor has per- formed a read of the alarm & error interrupt status register. 0 t1/e1 frame ro 0 t1/e1 framer block interrupt status indicates if an t1/e1 frame status interrupt request is awaiting service. 0 = no t1/e1 frame status interrupt is pending 1 = t1/e1 framer status interrupt is awaiting service.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 101 t able 108: b lock i nterrupt e nable r egister r egister 322 b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 x nb01 b it f unction t ype d efault d escription -o peration 7 sa6_enb r/w 0 sa6 interrupt enable 6 lbcode_enb r/w 0 loopback code interrupt enable 5 rxclkloss r/w 0 rxlineclk loss interrupt enable 0 = disables interrupt 1 = enables interrupt 4 onesec_enb r/w 0 one second interrupt enable 0 = disables interrupt 1 = enables interrupt 3 hdlc_enb r/w 0 hdlc block interrupt enable 0 = disables all hdlc block interrupts 1 = enables hdlc block (for interrupt generation) at the block level 2 slip_enb r/w 0 slip buffer block interrupt enable 0 = disables all slip buffer block interrupts 1 = enables slip buffer block at the block level 1 alarm_enb r/w 0 alarm & error block interrupt enable 0 = disables all alarm & error block interrupts 1 = enables alarm & error block at the block level 0 t1/e1frame_enb r/w 0 t1/e1 frame block enable 0 = disables all frame block interrupts 1 = enables the frame block at the block level t able 109: a larm & e rror i nterrupt s tatus r egister r egister 323 a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 x nb02 b it m ode f unction t ype d efault d escription -o peration 7 e1/t1 rxlof state ro 0 receive loss of frame state reflects a current loss of framing condition as detected by the receive t1/ e1 framer. 0 = receive framer not declaring loss of framing condition 1 = receive framer declaring loss of framing condition 6 e1/t1 rxais state ro 0 receive alarm indication status state this read only bit field indicates whether or not the receive t1/e1 frame is currently detecting an ais pattern in the incoming data stream. 0 = receive framer not detecting ais pattern in incoming t1/e1 data stream 1 = receive framer detecting ais pattern in incoming t1/e1 data stream 5 e1 rxmyel status rur 0 receipt of cas multiframe yellow alarm interrupt status. the receive e1 framer will set this bit-field to 1 if it detects the cas multiframe yellow alarm in the incoming e1 data stream. 0 = receipt of cas multiframe yellow alarm interrupt has not occurred since the last read of this register. 1 = receipt of cas multiframe yellow alarm interrupt has occurred since the last read of this register. 5 t1 rxyel_state r 0 yellow alarm state indicates a yellow alarm has been received. 0 = no yellow alarm is received 1 = yellow alarm is received
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 102 4 e1/t1 los status rur 0 loss of signal interrupt status. the receive e1 framer will set this bit- field to 1 if it detects a consecutive string of 0s at the rxpox_n and rxneg_n input pins for 32 bit period. 0 = los interrupt has not occurred since the last read of this register 1 = los interrupt has occurred since the last read of this register 3 e1/t1 lcv int status rur 0 line code violation interrupt status . the receive liu interrupt block will set this bit-field to 1 if it detects a line code violation in the incoming e1 data stream. 0 = line code violation interrupt has not occurred since the last read of this register. 1 = line code violation interrupt has occurred since the last read of this reg- ister. 2 e1/t1 rxlof status rur 0 change in receive loss of frame condition interrupt status . the receive e1 framer block will set this bit-field to 1 if the receive e1 framer has transition into the in-frame condition or loss of frame condition. 0 = change in rxlof interrupt has not occurred since the last read of this register 1 = change in rxlof interrupt has occurred since the last read of this regis- ter 1 e1/t1 rxais status rur 0 change in receive ais condition interrupt status . the receive e1 framer will generate the change in ais condition interrupt if it starts to detect the ais pattern in the incoming data stream or if it no longer detects the ais pattern in the incoming data stream. 0 = change in ais condition interrupt has not occurred since the last read of this register 1 = change in ais condition interrupt has occurred since the last read of this register 0 e1/t1 rxyel status rur 0 receipt of fas frame yellow alarm interrupt status. the receive e1 framer will generate the fas frame yellow alarm interrupt if it detects the fas frame yellow alarm in the incoming e1 data stream. 0 = fas frame yellow alarm interrupt has not occurred 1 = fas frame yellow alarm interrupt has occurred since the last read of this register. t able 109: a larm & e rror i nterrupt s tatus r egister r egister 323 a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 x nb02 b it m ode f unction t ype d efault d escription -o peration
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 103 t able 110: a larm & e rror i nterrupt e nable r egister - e1 m ode r egister 324 e1 m ode a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x nb03 b it f unction t ype d efault d escription -o peration 7-6 reserved - - reserved 5 rxmyel enb r/w 0 multiframe yellow alarm state change interrupt enable enables the generation of an interrupt when the yellow alarm has been received. 0 = a multiframe yellow alarm (y bit equals to 1) will not generate an interrupt. 1 = a multiframe yellow alarm will generate an interrupt. 4 los enb r/w 0 loss of signal interrupt enable enables the interrupt generation when the loss of signal has been detected. 0 = disables the interrupt generation of los detection. 1 = enables the interrupt generation of los detection 3 bpv enb r/w 0 bipolar violation interrupt enable enables the interrupt generation of a bipolar violation. 0 = disables the interrupt generation of a bipolar violation condition. 1 = enables the interrupt generation of a bipolar violation condition. 2 rxlof enb r/w 0 red alarm state change interrupt enable enables the interrupt generation when the change state of red alarm has been detected. 0 = disables the interrupt generation of loss of frame detection. 1 = enables the interrupt generation of loss of frame detection. 1 rxais enb r/w 0 ais state change interrupt enable enables the generation of an interrupt when the change state of ais event has been detected. 0 = the state change of ais does not generate an interrupt. 1 = the state change of ais does generate an interrupt. 0 rxyel enb r/w 0 yellow alarm state change interrupt enable enables the generation of an interrupt when the yellow alarm has been received. 0 = a yellow alarm (a bit equals to 1) will not generate an interrupt. 1 = a yellow alarm will generate an interrupt
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 104 t able 111: a larm & e rror i nterrupt e nable r egister -t1 m ode r egister 324 t1 m ode a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x nb03 b it f unction t ype d efault d escription -o peration 7-5 reserved - - reserved 4 los enb r/w 0 loss of signal interrupt enable enables the interrupt generation when the loss of signal has been detected. 0 = disables the interrupt generation of los detection. 1 = enables the interrupt generation of los detection. 3 bpv enb r/w 0 bipolar violation interrupt enable enables the interrupt generation of a bipolar violation. 0 = disables the interrupt generation of a bipolar violation condition. 1 = enables the interrupt generation of a bipolar violation condition. 2 rxred enb r/w 0 red alarm state change interrupt enable enables the interrupt generation when the change state of red alarm has been detected. 0 = disables the interrupt generation of framing mimic detection. 1 = enables the interrupt generation of framing mimic detection. 1 rxais enb r/w 0 ais state change interrupt enable enable the generation of an interrupt when the change state of ais event has been detected. 0 = the state change of ais does not generate an interrupt. 1 = the state change of ais does generate an interrupt 0 rxyel enb r/w 0 yellow alarm state change interrupt enable enables the generation of an interrupt when the change state of yellow alarm has been detected. 0 = any state change of yellow alarm will not generate an interrupt. 1 = changing state of yellow alarm will generate an interrupt.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 105 1 t able 112: f ramer i nterrupt s tatus r egister e1 m ode r egister 325 e1 m ode f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x nb04 b it f unction t ype d efault d escription -o peration 7 comfa status e1 only rur 0 change in cas multiframe alignment interrupt status 0 = change in cas multiframe alignment interrupt has not occurred since the last read of this register 1 = change in cas multiframe alignment interrupt has occurred since the last read of this register 6 nbit status e1 only rur 0 change in national bits interrupt status the receive e1 framer will generate this interrupt if it has detected a change in the national bits in the incoming non-fas e1 frames. 0 = change in national bits interrupt has not occurred since the last read of this register 1 = change in national bits interrupt has occurred since the last read of this register. 5 sig status rur 0 change in cas signaling interrupt status the receive e1 framer will generate this interrupt if it detects a change in the four-bit signaling values for any one of the 30 voice channels. 0 = change in cas signaling interrupt has not occurred since the last read of this register 1 = change in cas signaling interrupt has occurred since the last read of this register. 4 cofa status rur 0 change of fas frame alignment interrupt status 0 = change in fas frame alignment interrupt has not occurred since the last read of this register 1 = change in fas frame alignment interrupt has occurred since the last read of this register 3 if status rur 0 change of in frame condition interrupt status 2 fmd status rur 0 1 sync error status rur 0 crc-4 error interrupt status. the receive e1framer will declare this interrupt if it detects an error in the crc-4 bits within a given sub-multiframe. 0 = sync error has not occurred since the last read of this register 1 = sync error has occurred since the last read of this register 0 framing error status rur 0 0 = framing bit error interrupt has not occurred since the last read of this register 1 = framing bit error interrupt has occurred since the last read of this regis- ter
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 106 1 t able 113: f ramer i nterrupt s tatus r egister t1 m ode r egister 325 t1 m ode f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x nb04 b it f unction t ype d efault d escription -o peration 5 sig rur/ wc 0 signaling updated this bit indicates the occurrence of state change of any signaling channel. 0 = no state change occurs of any signaling. 1 = change of signaling state occurs. 4 cofa rur/ wc 0 change of frame alignment this bit is used to indicate that the receive synchronization signal has changed alignment with respect to its last multiframe position. 0 = no cofa occurs. 1 = cofa occurs. 3 if rur/ wc 0 in-frame state this bit indicates the occurrence of state change of in-frame indication. 0 = no state change occurs of in-frame indication. 1 = in-frame indication has changed state. 2 fmd rur/ wc 0 frame mimic state change this bit indicates the occurrence of state change of framing mimic detection. 0 = no state change occurs of framing mimic detection. 1 = framing mimic detection has changed state. 1 se rur/ wc 0 synchronization bit error this bit indicates the occurrence of synchronization bit error event. 0 = no synchronization bit error occurs. 1 = synchronization bit error occurs. 0 fe rur/ wc 0 framing error this bit is used to indicate that one or more frame alignment bit error have occurred. this bit doesn't not necessarily indicate that synchronization has been lost. 0 = no framing bit error occurs. 1 = framing bit error occurs.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 107 t able 114: f ramer i nterrupt e nable r egister e1 m ode r egister 326 e1 m ode f ramer i nterrupt e nable r egister (fier) h ex a ddress : 0 x nb05 b it f unction t ype d efault d escription -o peration 7 comfa enb - e1 only r/w 0 change in cas multiframe alignment interrupt enable - e1 only 0 = disables the change in cas multiframe alignment interrupt 1 = enables the change in cas multiframe alignment interrupt 6 nbit enb - e1 only r/w 0 change in national bits interrupt enable - e1 only 0 = disables the change in national bits interrupt 1 = enables the change in national bits interrupt 5 sig enb r/w 0 change in cas signaling bits interrupt enable 0 = disables the change in cas signaling bits interrupt enable 1 = enables the change in cas signaling bits interrupt enable 4 cofa enb r/w 0 change in fas framing alignment interrupt enable 0 = disables the change in fas framing alignment interrupt enable 1 = enables the change in fas framing alignment interrupt enable 3 if enb r/w 0 if enable 2fmd enb r/w 0 fmd enable 1 se_enb r/w 0 sync (crc-4) error interrupt enable 0 = sync error interrupt disabled 1 = sync error interrupt enabled 0fe_enb r/w0 0 framing bit error interrupt enable 0 = disables the framing bit error interrupt 1 = enables the framing bit error interrupt
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 108 t able 115: f ramer i nterrupt e nable r egister t1 m ode r egister 326 t1 m ode f ramer i nterrupt e nable r egister (fier) h ex a ddress : 0 x nb05 b it f unction t ype d efault d escription -o peration 5 sig_enb r/w 0 this bits enables the generation of an interrupt when any signaling channel has changed state. 0 = change of signaling data does not generate an interrupt. 1 = change of signaling data does generate an interrupt. 4 cofa_enb r/w 0 setting this bit will enable the interrupt generation when the frame search logic determines that frame alignment has been reached and that the new alignment differs from the previous alignment. 0 = disables the interrupt generation of cofa detection. 1 = enables the interrupt generation of cofa detection. 3 if_enb r/w 0 if enable setting this bit will enable the interrupt generation of an in-frame recognition. 0 = disables the interrupt generation of an in-frame detection. 1 = enables the interrupt generation of an in-frame detection. 2 fmd_enb r/w 0 fmd enable setting this bit will enable the interrupt generation when the frame search logic detects the presence of framing bit mimics. 0 = disables the interrupt generation of framing mimic detection. 1 = enables the interrupt generation of framing mimic detection. 1 se_enb r/w 0 sync (crc-4) error interrupt enable setting this bit will enable the generation of an interrupt when a synchroniza- tion bit error event has been detected. a synchronization bit error event is defined as crc-4 error. 0 = the detection of synchronization bit errors does not generate an inter- rupt. 1 = the detection of synchronization bit errors does generate an interrupt 0fe_enb r/w0 0 framing bit error interrupt enable this bits enables the generation of an interrupt when a framing bit error has been detected. 0 = any error in the framing bits does not generate an interrupt. 1 = a error in the framing bits does generate an interrupt.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 109 t able 116: d ata l ink s tatus r egister 1 r egister 327 d ata l ink s tatus r egister 1 (dlsr1) h ex a ddress : 0 x nb06 b it f unction t ype d efault d escription -o peration 7 msg type rur 0 hdlc1 message type identifier indicates type of data link message received by rx hdlc1 controller 0 = bit oriented signaling type data link message received 1 = message oriented signaling type data link message received 6 txsot rur 0 transmit hdlc1 start of transmission interrupt status indicates if the transmit hdlc1 start of transmission interrupt has occurred since the last read of this register. transmit hdlc1 controller will declare this interrupt when it has started to transmit a data link message. 0 = transmit hdlc1 start of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc1 start of transmission interrupt has occurred since the last read of this register. 5 rxsot rur 0 receive hdlc1 start of reception interrupt status indicates if the receive hdlc1 start of reception interrupt has occurred since the last read of this register. receive hdlc1 controller will declare this interrupt when it has started to receive a data link message. 0 = receive hdlc1 start of reception interrupt has not occurred since the last read of this register 1 = receive hdlc1 start of reception interrupt has occurred since the last read of this register 4 txeot rur 0 transmit hdlc1 end of transmission interrupt status indicates if the transmit hdlc1 end of transmission interrupt has occurred since the last read of this register. transmit hdlc1 controller will declare this interrupt when it has completed its transmission of a data link message. 0 = transmit hdlc1 end of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc1 end of transmission interrupt has occurred since the last read of this register 3 rxeot rur 0 receive hdlc1 controller end of reception interrupt status indicates if receive hdlc1 end of reception interrupt has occurred since the last read of this register. receive hdlc1 controller will declare this inter- rupt once it has completely received a full data link message. 0 = receive hdlc1 end of reception interrupt has not occurred since the last read of this register 1 = receive hdlc1 end of reception interrupt has occurred since the last read of this register 2 fcs error rur 0 fcs error interrupt status indicates if the fcs error interrupt has occurred since the last read of this register. receive hdlc1 controller will declare this interrupt if it detects an error in the most recently received data message. 0 = fcs error interrupt has not occurred since last read of this register 1 = fcs error interrupt has occurred since last read of this register 1 rx abort rur 0 receipt of abort sequence interrupt status indicates if the receipt of abort interrupt has occurred since last read of this register. receive hdlc1 controller will declare this interrupt if it detects a string of seven (7) consecutive 1s in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occurred since last read of this register 1 = receipt of abort sequence interrupt has occurred since last read of this register
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 110 0 rxidle rur 0 receipt of idle sequence interrupt status indicates if the receipt of idle sequence interrupt has occurred since the last read of this register. the receive hdlc1 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. 0 = receipt of idle sequence interrupt has not occurred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 117: d ata l ink i nterrupt e nable r egister 1 r egister 328 d ata l ink i nterrupt e nable r egister 1 (dlier1) h ex a ddress : 0 x nb07 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc1 start of transmission interrupt enable 0 = disables the transmit hdlc1 start of transmission interrupt 1 = enables the transmit hdlc1 start of transmission interrupt 5 rxsot enb r/w 0 receive hdlc1 start of reception interrupt enable 0 = disables the receive hdlc1 start of reception interrupt 1 = enables the receive hdlc1 start of reception interrupt 4 txeot enb r/w 0 transmit hdlc1 end of transmission interrupt enable 0 = disables the transmit hdlc1 end of transmission interrupt 1 = enables the transmit hdlc1 end of transmission interrupt 3 rxeot enb r/w 0 receive hdlc1 end of reception interrupt enable 0 = disables the receive hdlc1 end of reception interrupt 1 = enables the receive hdlc1 end of reception interrupt 2 fcs err enb r/w 0 fcs error interrupt enable 0 = disables fcs error interrupt 1 = enables fcs error interrupt 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable 0 = disables receipt of abort sequence interrupt 1 = enables receive of abort sequence interrupt 0 rxidle enb r/w 0 receipt of idle sequence interrupt enable 0 = disables receipt of idle sequence interrupt 1 = enables receipt of idle sequence interrupt t able 116: d ata l ink s tatus r egister 1 r egister 327 d ata l ink s tatus r egister 1 (dlsr1) h ex a ddress : 0 x nb06 b it f unction t ype d efault d escription -o peration
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 111 t able 118: s lip b uffer i nterrupt s tatus r egister (sbsr) r egister 329 s lip b uffer i nterrupt s tatus r egister (sbsr) h ex a ddress : 0 x nb08 b it f unction t ype d efault d escription -o peration 7 txsb_full rur/ wc 0 slip buffer fills & a frame is deleted this bit is set when the elastic store fills and a frame is deleted. 6 txsb_empt rur/ wc 0 slip buffer empties and a frame is repeated this bit is set when the elastic store empties and a frame is repeated. 5 txsb_slip rur/ wc 0 receive slips this bit is set when the slip buffer slips. 4 96lock r 0 slc ? 96 is in sync this bit indicates that slc96 is in sync. 3 mlock r 0 multiframe is in sync this bit indicates that multiframe is in sync. 2 sb_full rur/ wc 0 slip buffer fills & a frame is deleted this bit is set when the elastic store fills and a frame is deleted. 1 sb_empt rur/ wc 0 slip buffer empties and a frame is repeated this bit is set when the elastic store empties and a frame is repeated. 0 sb_slip rur/ wc 0 receive slips this bit is set when the slip buffer slips. t able 119: s lip b uffer i nterrupt e nable r egister (sbier) r egister 330 s lip b uffer i nterrupt e nable r egister (sbier) h ex a ddress : 0 x nb09 b it f unction t ype d efault d escription -o peration 7 txfull_enb r/w 0 tx interrupt enable bit for slip buffer full setting this bit enables interrupt when the elastic store fills and a frame is deleted. 6 txempt_enb r/w 0 tx interrupt enable bit for slip buffer empty setting this bit enables interrupt when the elastic store empties and a frame is repeated. 5 txslip_enb r/w 0 tx interrupt enable bit for slip buffer slip setting this bit enables interrupt when the slip buffer slips. 4-3 reserved - - reserved 2 full_enb r/w 0 interrupt enable bit for slip buffer full setting this bit enables interrupt when the elastic store fills and a frame is deleted. 1 empt_enb r/w 0 interrupt enable bit for slip buffer empty setting this bit enables interrupt when the elastic store empties and a frame is repeated. 0 slip_enb r/w 0 interrupt enable bit for slip buffer slip setting this bit enables interrupt when the slip buffer slips.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 112 t able 120: r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) r egister 331 r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) h ex a ddress : 0 x nb0a b it f unction t ype d efault d escription -o peration 7 auxpstat r0 auxp state this bit indicates the status of receive auxp pattern. 6 auxpint rur/wc 0 auxp state change interrupt 1 = indicates the receive auxp status has changed. 5 noncrcstat r0 crc-4-to-non-crc-4 interworking status this bit indicates the status of crc-4 interworking status in modenb mode. 1 = crc-4-to-non-crc-4 interworking is established. 4 noncrcint rur/wc 0 crc-4-to-non-crc-4 interworking interrupt 1 = indicates the interworking status has changed. 3 rxastat r0 receive activation status this bit indicates the status of receive activation process. 1 = indicates the loopback code activation is received. 2 rxdstat r0 receive deactivation status this bit indicates the status of receive deactivation process. 1 = indicates the loopback code deactivation is received. 1 rxaint rur/wc 0 receive activation interrupt 1 = indicates the loopback code activation status has changed. 0 rxdint rur/wc 0 receive deactivation interrupt 1 = indicates the loopback code deactivation status has changed. t able 121: r eceive l oopback c ode i nterrupt e nable r egister (rlcier) r egister 332 r eceive l oopback c ode i nterrupt e nable r egister (rlcier) h ex a ddress : 0 x nb0b b it f unction t ype d efault d escription -o peration 6 auxpintenb r/w 0 auxp interrupt enable 1 = enables the receive auxp detect interrupt. 5 reserved - - reserved 4 noncrcenb r/w 0 crc-4 interworking interrupt enable 1 = enables the crc-4-non-crc-4 interworking interrupt. 3-2 reserved - - reserved 1 rxaenb r/w 0 receive activation interrupt enable 1 = enables the loopback code activation interrupt. 0 rxdenb r/w 0 receive deactivation interrupt enable 1 = enables the loopback code deactivation interrupt.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 113 t able 122: r eceive sa i nterrupt r egister (rsair) r egister 333 r eceive sa i nterrupt r egister (rsair) h ex a ddress : 0 x nb0c b it f unction t ype d efault d escription -o peration 7 sa6_1111 r/w 0 debounced sa6 = 1111 received 1 = indicates a debounced sa6 = 1111 has been received. 6 sa6_1110 r/w 0 debounced sa6 = 1110 received 1 = indicates a debounced sa6 = 1111 has been received. 5 sa6_1100 r/w 0 debounced sa6 = 1100 received 1 = indicates a debounced sa6 = 1111 has been received. 4 sa6_1010 r/w 0 debounced sa6 = 1010 received 1 = indicates a debounced sa6 = 1010 has been received. 3 sa6_1000 r/w 0 debounced sa6 = 1000 received 1 = indicates a debounced sa6 = 1111 has been received. 2 sa6_001x r/w 0 debounced sa6 = 001x received 1 = indicates a debounced sa6 = 1111 has been received. 1 sa6_other r/w 0 debounced sa6 = other received 1 = indicates a debounced sa6 equals to other combination received. 0 sa6_0000 r/w 0 debounced sa6 = 0000 received 1 = indicates a debounced sa6 = 0000 has been received.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 114 t able 123: r eceive sa i nterrupt e nable r egister (rsaier) r egister 334 r eceive sa i nterrupt e nable r egister (rsaier) h ex a ddress : 0 x nb0d b it f unction t ype d efault d escription -o peration 7 sa6_1111_enb r/w 0 debounced sa6 = 1111 received enable 1 = indicates a debounced sa6 = 1111 has been received. 6 sa6_1110_enb r/w 0 debounced sa6 = 1110 received enable 1 = enables the generation of an interrupt when a debounced sa6 = 1111 has been received. 5 sa6_1100_enb r/w 0 debounced sa6 = 1100 received enable 1 = enables the generation of an interrupt when a debounced sa6 = 1111 has been received. 4 sa6_1010_enb r/w 0 debounced sa6 = 1010 received enable 1 = enables the generation of an interrupt when a debounced sa6 = 1111 has been received. 3 sa6_1000_enb r/w 0 debounced sa6 = 1000 received enable 1 = enables the generation of an interrupt when a debounced sa6 = 1111 has been received. 2 sa6_001x_enb r/w 0 debounced sa6 = 001x received enable 1 = enables the generation of an interrupt when a debounced sa6 = 1111 has been received. 1 sa6_other_enb r/w 0 debounced sa6 = other received enable 1 = enables the generation of an interrupt when a debounced sa6 equals to other combinations received. 0 sa6_0000_enb r/w 0 debounced sa6 = 0000 received enable 1 = enables the generation of an interrupt when a debounced sa6 = 0000 has been received. t able 124: e xcessive z ero s tatus r egister r egister 334 e xcessive z ero s tatus r egister (exzsr) h ex a ddress : 0 x nb0e b it f unction t ype d efault d escription -o peration 0 exz_status rur 0 excessive zero state change 0 = no change in status 1 = change in status has occured t able 125: e xcessive z ero e nable r egister r egister 334 e xcessive z ero e nable r egister (exzer) h ex a ddress : 0 x nb0f b it f unction t ype d efault d escription -o peration 0 exz_enb r/w 0 excessive zero interrupt enable 0 = disabled 1 = enable excessiver zero interrupt generation
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 115 t able 126: ss7 s tatus r egister for lapd1 r egister 334 ss7 s tatus r egister for lapd1 (ss7sr1) h ex a ddress : 0 x nb10 b it f unction t ype d efault d escription -o peration 0 ss7_1_status rur 0 ss7 interrupt status for lapd1 0 = no change in status 1 = change in status has occured t able 127: ss7 e nable r egister for lapd1 r egister 334 ss7 e nable r egister for lapd1 (ss7er1) h ex a ddress : 0 x nb11 b it f unction t ype d efault d escription -o peration 0 ss7_1_enb r/w 0 ss7 interrupt enable for lapd1 0 = disabled 1 = enable ss7 interrupt generation if more than 276 bytes are received within the lapd1 message
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 116 t able 128: d ata l ink s tatus r egister 2 r egister 327 d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 x nb16 b it f unction t ype d efault d escription -o peration 7 msg type rur 0 hdlc2 message type identifier indicates type of data link message received by rx hdlc2 controller 0 = bit oriented signaling type data link message received 1 = message oriented signaling type data link message received 6 txsot rur 0 transmit hdlc2 start of transmission interrupt status indicates if the transmit hdlc2 start of transmission interrupt has occurred since the last read of this register. transmit hdlc2 controller will declare this interrupt when it has started to transmit a data link message. 0 = transmit hdlc2 start of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc2 start of transmission interrupt has occurred since the last read of this register. 5 rxsot rur 0 receive hdlc2 start of reception interrupt status indicates if the receive hdlc2 start of reception interrupt has occurred since the last read of this register. receive hdlc2 controller will declare this interrupt when it has started to receive a data link message. 0 = receive hdlc2 start of reception interrupt has not occurred since the last read of this register 1 = receive hdlc2 start of reception interrupt has occurred since the last read of this register 4 txeot rur 0 transmit hdlc2 end of transmission interrupt status indicates if the transmit hdlc2 end of transmission interrupt has occurred since the last read of this register. transmit hdlc2 controller will declare this interrupt when it has completed its transmission of a data link message. 0 = transmit hdlc2 end of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc2 end of transmission interrupt has occurred since the last read of this register 3 rxeot rur 0 receive hdlc2 controller end of reception interrupt status indicates if receive hdlc2 end of reception interrupt has occurred since the last read of this register. receive hdlc2 controller will declare this inter- rupt once it has completely received a full data link message. 0 = receive hdlc2 end of reception interrupt has not occurred since the last read of this register 1 = receive hdlc2 end of reception interrupt has occurred since the last read of this register 2 fcs error rur 0 fcs error interrupt status indicates if the fcs error interrupt has occurred since the last read of this register. receive hdlc2 controller will declare this interrupt if it detects an error in the most recently received data message. 0 = fcs error interrupt has not occurred since last read of this register 1 = fcs error interrupt has occurred since last read of this register 1 rx abort rur 0 receipt of abort sequence interrupt status indicates if the receipt of abort interrupt has occurred since last read of this register. receive hdlc2 controller will declare this interrupt if it detects a string of seven (7) consecutive 1s in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occurred since last read of this register 1 = receipt of abort sequence interrupt has occurred since last read of this register
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 117 0 rxidle rur 0 receipt of idle sequence interrupt status indicates if the receipt of idle sequence interrupt has occurred since the last read of this register. the receive hdlc2 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. 0 = receipt of idle sequence interrupt has not occurred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 129: d ata l ink i nterrupt e nable r egister 2 r egister 328 d ata l ink i nterrupt e nable r egister 2 (dlier2) h ex a ddress : 0 x nb17 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc2 start of transmission interrupt enable 0 = disables the transmit hdlc2 start of transmission interrupt 1 = enables the transmit hdlc2 start of transmission interrupt 5 rxsot enb r/w 0 receive hdlc2 start of reception interrupt enable 0 = disables the receive hdlc2 start of reception interrupt 1 = enables the receive hdlc2 start of reception interrupt 4 txeot enb r/w 0 transmit hdlc2 end of transmission interrupt enable 0 = disables the transmit hdlc2 end of transmission interrupt 1 = enables the transmit hdlc2 end of transmission interrupt 3 rxeot enb r/w 0 receive hdlc2 end of reception interrupt enable 0 = disables the receive hdlc2 end of reception interrupt 1 = enables the receive hdlc2 end of reception interrupt 2 fcs err enb r/w 0 fcs error interrupt enable 0 = disables fcs error interrupt 1 = enables fcs error interrupt 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable 0 = disables receipt of abort sequence interrupt 1 = enables receive of abort sequence interrupt 0 rxidle enb r/w 0 receipt of idle sequence interrupt enable 0 = disables receipt of idle sequence interrupt 1 = enables receipt of idle sequence interrupt t able 130: ss7 s tatus r egister for lapd2 r egister 334 ss7 s tatus r egister for lapd2 (ss7sr2) h ex a ddress : 0 x nb18 b it f unction t ype d efault d escription -o peration 0 ss7_2_status rur 0 ss7 interrupt status for lapd2 0 = no change in status 1 = change in status has occured t able 128: d ata l ink s tatus r egister 2 r egister 327 d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 x nb16 b it f unction t ype d efault d escription -o peration
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 118 t able 131: ss7 e nable r egister for lapd2 r egister 334 ss7 e nable r egister for lapd2 (ss7sr2) h ex a ddress : 0 x nb19 b it f unction t ype d efault d escription -o peration 0 ss7_2_enb r/w 0 ss7 interrupt enable for lapd2 0 = disabled 1 = enable ss7 interrupt generation if more than 276 bytes are received within the lapd2 message
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 119 t able 132: d ata l ink s tatus r egister 3 r egister 327 d ata l ink s tatus r egister 3 (dlsr3) h ex a ddress : 0 x nb26 b it f unction t ype d efault d escription -o peration 7 msg type rur 0 hdlc3 message type identifier indicates type of data link message received by rx hdlc3 controller 0 = bit oriented signaling type data link message received 1 = message oriented signaling type data link message received 6 txsot rur 0 transmit hdlc3 start of transmission interrupt status indicates if the transmit hdlc3 start of transmission interrupt has occurred since the last read of this register. transmit hdlc3 controller will declare this interrupt when it has started to transmit a data link message. 0 = transmit hdlc3 start of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc3 start of transmission interrupt has occurred since the last read of this register. 5 rxsot rur 0 receive hdlc3 start of reception interrupt status indicates if the receive hdlc3 start of reception interrupt has occurred since the last read of this register. receive hdlc3 controller will declare this interrupt when it has started to receive a data link message. 0 = receive hdlc3 start of reception interrupt has not occurred since the last read of this register 1 = receive hdlc3 start of reception interrupt has occurred since the last read of this register 4 txeot rur 0 transmit hdlc3 end of transmission interrupt status indicates if the transmit hdlc3 end of transmission interrupt has occurred since the last read of this register. transmit hdlc3 controller will declare this interrupt when it has completed its transmission of a data link message. 0 = transmit hdlc3 end of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc3 end of transmission interrupt has occurred since the last read of this register 3 rxeot rur 0 receive hdlc3 controller end of reception interrupt status indicates if receive hdlc3 end of reception interrupt has occurred since the last read of this register. receive hdlc3 controller will declare this inter- rupt once it has completely received a full data link message. 0 = receive hdlc3 end of reception interrupt has not occurred since the last read of this register 1 = receive hdlc3 end of reception interrupt has occurred since the last read of this register 2 fcs error rur 0 fcs error interrupt status indicates if the fcs error interrupt has occurred since the last read of this register. receive hdlc3 controller will declare this interrupt if it detects an error in the most recently received data message. 0 = fcs error interrupt has not occurred since last read of this register 1 = fcs error interrupt has occurred since last read of this register 1 rx abort rur 0 receipt of abort sequence interrupt status indicates if the receipt of abort interrupt has occurred since last read of this register. receive hdlc3 controller will declare this interrupt if it detects a string of seven (7) consecutive 1s in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occurred since last read of this register 1 = receipt of abort sequence interrupt has occurred since last read of this register
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 120 0 rxidle rur 0 receipt of idle sequence interrupt status indicates if the receipt of idle sequence interrupt has occurred since the last read of this register. the receive hdlc2 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. 0 = receipt of idle sequence interrupt has not occurred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 133: d ata l ink i nterrupt e nable r egister 3 r egister 328 d ata l ink i nterrupt e nable r egister 3 (dlier3) h ex a ddress : 0 x nb27 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc3 start of transmission interrupt enable 0 = disables the transmit hdlc3 start of transmission interrupt 1 = enables the transmit hdlc3 start of transmission interrupt 5 rxsot enb r/w 0 receive hdlc3 start of reception interrupt enable 0 = disables the receive hdlc3 start of reception interrupt 1 = enables the receive hdlc3 start of reception interrupt 4 txeot enb r/w 0 transmit hdlc3 end of transmission interrupt enable 0 = disables the transmit hdlc3 end of transmission interrupt 1 = enables the transmit hdlc3 end of transmission interrupt 3 rxeot enb r/w 0 receive hdlc3 end of reception interrupt enable 0 = disables the receive hdlc3 end of reception interrupt 1 = enables the receive hdlc3 end of reception interrupt 2 fcs err enb r/w 0 fcs error interrupt enable 0 = disables fcs error interrupt 1 = enables fcs error interrupt 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable 0 = disables receipt of abort sequence interrupt 1 = enables receive of abort sequence interrupt 0 rxidle enb r/w 0 receipt of idle sequence interrupt enable 0 = disables receipt of idle sequence interrupt 1 = enables receipt of idle sequence interrupt t able 134: ss7 s tatus r egister for lapd3 r egister 334 ss7 s tatus r egister for lapd3 (ss7sr3) h ex a ddress : 0 x nb28 b it f unction t ype d efault d escription -o peration 0 ss7_3_status rur 0 ss7 interrupt status for lapd3 0 = no change in status 1 = change in status has occured b it f unction t ype d efault d escription -o peration
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 121 t able 135: ss7 e nable r egister for lapd3 t able 136: r egister 334 ss7 e nable r egister for lapd3 (ss7sr3) h ex a ddress : 0 x nb29 b it f unction t ype d efault d escription -o peration 0 ss7_3_enb r/w 0 ss7 interrupt enable for lapd3 0 = disabled 1 = enable ss7 interrupt generation if more than 276 bytes are received within the lapd3 message t able 137: c ustomer i nstallation a larm s tatus r egister r egister 334 c ustomer i nstallation a larm s tatus r egister (ciasr) h ex a ddress : 0 x nb40 b it f unction t ype d efault d escription -o peration [7:6] reserved - - these bits are reserved 5 rxais-ci_state r/w 0 rx ais-ci state 0 = no ais-ci state detected 1 = ais-ci state detected 4 rxrai-ci_state r/w 0 rx rai-ci state 0 = no rai-ci state detected 1 = rai-ci state detected [3:2] reserved - - these bits are reserved 1 rxais-ci rur 0 rx ais-ci state change 0 = no change in status 1 = change of status has occured 0 rxrai-ci rur 0 rx rai-ci state change 0 = no change in status 1 = change of status has occured t able 138: c ustomer i nstallation a larm s tatus r egister r egister 334 c ustomer i nstallation a larm i nterrupt e nable r egister (ciaier) h ex a ddress : 0 x nb41 b it f unction t ype d efault d escription -o peration 1 rxais-ci_enb r/w 0 rx ais-ci interrupt generation enable 0 = disabled 1 - enable rx ais-ci interrupt generation 0 rxrai-ci_enb r/w 0 rx rai-ci interrupt generation enable 0 = disabled 1 - enable rx rai-ci interrupt generation
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 122 1.5 t he i nterrupt s tructure within the f ramer the XRT86L34 framer is equipped with a sophisticated interrupt servicing structure. this interrupt structure includes an interrupt request output pin int , numerous interrupt enable registers and numerous interrupt status registers. the interrupt servicing structure, within the XRT86L34 framer contains three levels of hierarchy: ? the framer level ? the block level ? the source level. the framer interrupt structure has been carefully designed to allow the user to quickly determine the exact source of this interrupt (with minimal latency) which will aid the mc/mp in determining the which interrupt ser- vice routine to call up in order to eliminate or properly respond to the condition(s) causing the interrupt. the XRT86L34 framer comes equipped with registers to support the servicing of this wide array of potential "interrupt request" sources. table 139 lists the possible conditions that can generate interrupts. general flow of interrupt servicing when any of the conditions presented in table 139 occur, (if their interrupt is enabled), then the framer gener- ates an interrupt request to the mp/mc by asserting the active-low interrupt request output pin, int . shortly af- ter the local mc/mp has detected the activated int signal, it will enter into the appropriate user-supplied inter- rupt service routine. the first task for the mp/mc, while running this interrupt service routine, may be to isolate the source of the interrupt request down to the device level (e.g, the framer ic), if multiple peripheral ics exist in the user's system. however, once the interrupting peripheral device has been identified, the next task for the mp/mc is to determine exactly what feature of functional section within the device requested the interrupt. determine the framer(s) requesting the interrupt t able 139: l ist of the p ossible c onditions that can g enerate i nterrupts , in each f ramer i nterrupt b lock i nterrupting c ondition framer level loss of rxlineclk signal one second interrupt hdlc controller block transmit hdlc - start of transmission receive hdlc - start of reception transmit hdlc - end of transmission receive hdlc - end of reception fcs error receipt of abort sequence receipt of idle sequence slip buffer block slip buffer full slip buffer empty slip buffer - slip alarm & error block receipt of cas multi-frame yellow alarm detection of loss of signal condition detection of line code violation change in receive loss of framer condition change in receive ais condition receipt of fas frame yellow alarm t1/e1 frame block change in cas multi-frame alignment change in national bits change in cas signaling bits change in fas frame alignment change in the "in frame" condition detection of "frame mimicking data" detection of sync (crc-4/crc-6) errors detection of framing bit errors
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 123 if the interrupting device turns out to be the framer, then the mp/mc must determine which of the eight framer channels requested the interrupt. hence, upon reaching this state, one of the very first things that the mp/mc must do within the user framer interrupt service routine, is to perform a read of each of the block interrupt sta- tus registers within all of the framer channels that have been enabled for interrupt generation via their re- spective interrupt control registers. table 140 lists the address for the block interrupt status registers associated with each of the framer chan- nels within the framer. the bit-format of each of these block interrupt status registers is listed below. t able 140: a ddress of the b lock i nterrupt s tatus r egisters f ramer n umber a ddress of b lock i nterrupt s tatus r egister 0 0x0b02 1 0x1b02 2 0x2b02 3 0x3b02 4 0x4b02 5 0x5b02 6 0x6b02 7 0x7b02
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 124 for a given framer, the block interrupt status register presents the "interrupt request" status of each "inter- rupt block" within the framer. the purpose of the "block interrupt status register" is to help the mp/mc identi- fy which "interrupt block(s) have requested the interrupt. whichever bit(s) are asserted, in this register, identi- fies which block(s) have experienced an "interrupt generating" condition, as presented in table 141. once the t able 141: b lock i nterrupt s tatus r egister r egister 321 b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x nb00 b it f unction t ype d efault d escription -o peration 7 sa6 ro 0 sa6 interrupt status 7-6 lbcode ro 0 loopback code interrupt 5 rxclklos rur 0 rxclk los interrupt status indicates if framer n has experienced a loss of recovered clock interrupt since last read of this register. 0 = loss of recovered clock interrupt has not occurred since last read of this register 1 = loss of recovered clock interrupt has occurred since last read of this register. 4 onesec rur 0 one second interrupt status indicates if the XRT86L34 has experienced a one second interrupt since the last read of this register. 0 = no outstanding one second interrupts awaiting service 1 = outstanding one second interrupt awaits service 3 hdlc ro 0 hdlc block interrupt status indicates if the hdlc block has an interrupt request awaiting service. 0 = no outstanding interrupt requests awaiting service 1 = hdlc block has an interrupt request awaiting service. interrupt service routine should branch to and read data link status register (address xa,06). n ote : this bit-field will be reset to 0 after the microprocessor has performed a read to the data link status register. 2slip ro 0 slip buffer block interrupt status indicates if the slip buffer block has any outstanding interrupt requests awaiting service. 0 = no outstanding interrupts awaiting service 1 = slip buffer block has an interrupt awaiting service. interrupt service rou- tine should branch to and read slip buffer interrupt status register (address 0xxa,0x09. n ote : this bit-field will be reset to 0 after the microprocessor has performed a read of the slip buffer interrupt status register. 1 alarm ro 0 alarm & error block interrupt status indicates if the alarm & error block has any outstanding interrupts that are awaiting service. 0 = no outstanding interrupts awaiting service 1 = alarm & error block has an interrupt awaiting service. interrupt serstatus register (address xa,02) n ote : this bit-field will be reset to 0 after the microprocessor has performed a read of the alarm & error interrupt status register. 0 t1/e1 frame ro 0 t1/e1 framer block interrupt status indicates if an t1/e1 frame status interrupt request is awaiting service. 0 = no t1/e1 frame status interrupt is pending 1 = t1/e1 framer status interrupt is awaiting service.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 125 mp/mc has read this register, it can determine which "branch" within the interrupt service routine that it must follow; in order to properly service this interrupt. the framer ic further supports the "interrupt block" hierarchy by providing the "block interrupt enable regis- ter. the bit-format of this register is identical to that for the "block interrupt status register", and is presented below for the sake of completeness. the block interrupt enable register permits the user to individually enable or disable the interrupt requesting capability of each of the "interrupt blocks" within the framer. if a particular bit-field, within this register contains the value "0"; then the corresponding functional block has been disabled from generating any interrupt re- quests. the procedures for configuring, enabling and servicing interrupts for each of these hierarchical levels is dis- cussed below. 1.5.1 configuring the interrupt system, at the framer level the XRT86L34 framer ic permits the user to enable or disable each of the eight framers for interrupt genera- tion. further, the chip permits the user to make the following configuration selection. 1. whether the "source-level" interrupt status bits are "reset-upon-read" or "write-to-clear". 2. whether or not an "activated interrupt" is automatically cleared. 1.5.1.1 enabling/disabling the framer for interrupt generation each of the eight (8) framers of the XRT86L34 framer can be enabled or disabled for interrupt generation. this selection is made by writing the appropriate 0 or 1 to bit 0 (intrup_en) of the "interrupt control reg- ister" corresponding to that framer, (see table 143.) t able 142: b lock i nterrupt e nable r egister r egister 322 b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 x nb01 b it f unction t ype d efault d escription -o peration 7 sa6_enb r/w 0 sa6 interrupt enable 6 lbcode_enb r/w 0 loopback code interrupt enable 5 rxclkloss r/w 0 rxlineclk loss interrupt enable 0 = disables interrupt 1 = enables interrupt 4 onesec_enb r/w 0 one second interrupt enable 0 = disables interrupt 1 = enables interrupt 3 hdlc_enb r/w 0 hdlc block interrupt enable 0 = disables all hdlc block interrupts 1 = enables hdlc block (for interrupt generation) at the block level 2 slip_enb r/w 0 slip buffer block interrupt enable 0 = disables all slip buffer block interrupts 1 = enables slip buffer block at the block level 1 alarm_enb r/w 0 alarm & error block interrupt enable 0 = disables all alarm & error block interrupts 1 = enables alarm & error block at the block level 0 t1/e1frame_enb r/w 0 t1/e1 frame block enable 0 = disables all frame block interrupts 1 = enables the frame block at the block level
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 126 setting this bit-field to "0" disables all interrupts within the framer. setting this bit-field to "1" enables the fram- er for interrupt generation (at the framer level). n ote : it is important to note that setting this bit-field to "1" does not enable all of the interrupts within the framer. a given interrupt must also be enabled at the block and source-level, before it is enabled for interrupt generation. 1.5.1.2 configuring the "interrupt status bits", within a given framer to be "reset-upon-read" or "write-to-clear". the XRT86L34 source-level interrupt status register bits can be configured to be either "reset-upon-read" or "write-to-clear". if the user configures the interrupt status registers to be "reset-upon-read", then when the mp/mc is reading the interrupt status register, the following will happen. 1. the contents of the source-level interrupt status register will automatically be reset to "0x00", following the read operation. 2. the interrupt request output pin (int ) will automatically toggle false (or "high") upon reading the interrupt status register containing the last activated interrupt status bit. if the user configures the interrupt status registers to be "write-to-clear", then when the mp/mc is reading the interrupt status register, the following will happen. 1. the contents of the source-level interrupt status register will not be cleared to "0x00", following the read operation. the mp/mc will have to write 0x00 to the interrupt status register in order to reset the contents of the register to 0x00. 2. reading the interrupt status register, which contains the activated bit(s) will not cause the "interrupt request output" pin (int ) to toggle false. the interrupt request output pin will not toggle false until the mp/mc has written 0x00 into this register. (hence, the interrupt service routine must include this write operation). the interrupt status register (associated with a given framer) can be configured to be either "reset-upon- read" or "write-to-clear" by writing the appropriate value into bit 2, within the interrupt control register as in- dicated in table 143. writing a "0" into this bit-field configures the interrupt status registers to be "reset-upon-read"(rur). con- versely, writing a "1" into this bit-field configures the interrupt status registers to be "write-to-clear". 1.5.1.3 automatic reset of interrupt enable bits occasionally, the user's system (which includes the framer ic), may experience a fault condition, such that a "framer interrupt condition" will continuously exist. if this particular interrupt has been enabled (within the framer), then the framer will generate an interrupt request to the mp/mc. afterwards, the mp/mc will attempt to service this interrupt by reading the appropriate block-level and source-level interrupt status register. ad- t able 143: i nterrupt c ontrol r egister r egister 26 i nterrupt c ontrol r egister (icr) h ex a ddress : 0 x n11a b it m ode f unction t ype d efault d escription -o peration 7-3 reserved - - reserved 2 int_wc_rur r/w 0 interrupt write-to-clear or reset-upon-read select configures interrupt status bits to either rur or write-to-clear 0=interrupt status bit rur 1=interrupt status bit write-to-clear 1enbclr r/w0 interrupt enable auto clear 0=interrupt enable bits are not cleared after status reading 1=interrupt enable bits are cleared after status reading 0 intrup_enb r/w 0 interrupt enable for framer_n enables framer n for interrupt generation. 0 = disables corresponding framer block for interrupt generation 1 = enables corresponding framer block for interrupt generation
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 127 ditionally, the local mp/mc will attempt to perform some "system-related" tasks in order to try to resolve these conditions causing the interrupt. after the local mc/mp has attempted all of these things, the framer ic will ne- gate the int output pin. however, because this system fault still remains, the condition causing the framer to issue this interrupt also exists. consequently, the framer ic will generate another interrupt request, which forc- es the mp/mc to once again attempt to service this interrupt. this phenomenon quickly results in the local mp/ mc being "tied up" in a continuous cycle of executing this one interrupt service routine. consequently, the mp/ mc (along with portions of the overall system) now becomes non-functional. in order to prevent this phenomenon from ever occurring, the framer ic can be configured to automatically re- set the "interrupt enable" bits, following their activation. this feature can be implemented by writing the appro- priate value to bit 1 of the "interrupt control register" as indicated in table 143. writing a "1" to this bit-field configures the framer to reset a given interrupt following activation. writing a "0" to this bit-field configures the framer to leave the interrupt enabled, following its activation.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 128 1.6 p rogramming the l ine i nterface u nit (liu s ection ) channel control registers t able 144: m icroprocessor r egister #335, b it d escription r egister a ddress 0 x 0f00 h 0 x 0f10 h 0 x 0f20 h 0 x 0f30 h 0 x 0f40 h 0 x 0f50 h 0 x 0f60 h 0 x 0f70 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved this bit is not used r/w 0 d6 reserved this bit is not used r/w d5 rxon_n receiver on: writing a 1 into this bit location turns on the receive section of channel n. writing a 0 shuts off the receiver section of channel n. r/w 0 d4 eqc4_n equalizer control bit 4: this bit together with eqc[3:0] are used for controlling transmit pulse shaping, transmit line build- out (lbo) and receive monitoring for either t1 or e1 modes of operation. see table 145. r/w 0 d3 eqc3_n equalizer control bit 3: see bit d4 description for function of this bit r/w 0 d2 eqc2_n equalizer control bit 2: see bit d4 description for function of this bit r/w 0 d1 eqc1_n equalizer control bit 1: see bit d4 description for function of this bit r/w 0 d0 eqc0_n equalizer control bit 0: see bit d4 description for function of this bit r/w 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 129 t able 145: e qualizer c ontrol and t ransmit l ine b uild o ut eqc[4:0] t1/e1 m ode /r eceive s ensitivity t ransmit lbo c able 0x00h t1 long haul/36db 0db 100 w tp 0x01h t1 long haul/36db -7.5db 100 w tp 0x02h t1 long haul/36db -15db 100 w tp 0x03h t1 long haul/36db -22.5db 100 w tp 0x04h t1 long haul/45db 0db 100 w tp 0x05h t1 long haul/45db -7.5db 100 w tp 0x06h t1 long haul/45db -15db 100 w tp 0x07h t1 long haul/45db -22.5db 100 w tp 0x08h t1 short haul/15db 0 to 133 feet (0.6db) 100 w tp 0x09h t1 short haul/15db 133 to 266 feet (1.2db) 100 w tp 0x0ah t1 short haul/15db 266 to 399 feet (1.8db) 100 w tp 0x0bh t1 short haul/15db 399 to 533 feet (2.4db) 100 w tp 0x0ch t1 short haul/15db 533 to 655 feet (3.0db) 100 w tp 0x0dh t1 short haul/15db arbitrary pulse 100 w tp 0x0eh t1 gain mode/29db 0 to 133 feet (0.6db) 100 w tp 0x0fh t1 gain mode/29db 133 to 266 feet (1.2db) 100 w tp 0x10h t1 gain mode/29db 266 to 399 feet (1.8db) 100 w tp 0x11h t1 gain mode/29db 399 to 533 feet (2.4db) 100 w tp 0x12h t1 gain mode/29db 533 to 655 feet (3.0db) 100 w tp 0x13h t1 gain mode/29db arbitrary pulse 100 w tp 0x14h t1 gain mode/29db 0db 100 w tp 0x15h t1 gain mode/29db -7.5db 100 w tp 0x16h t1 gain mode/29db -15db 100 w tp 0x17h t1 gain mode/29db -22.5db 100 w tp 0x18h e1 long haul/36db itu g.703 75 w coax 0x19h e1 long haul/36db itu g.703 120 w tp 0x1ah e1 long haul/45db itu g.703 75 w coax 0x1bh e1 long haul/45db itu g.703 120 w tp 0x1ch e1 short haul/15db itu g.703 75 w coax 0x1dh e1 short haul/15db itu g.703 120 w tp 0x1eh e1 gain mode/29db itu g.703 75 w coax 0x1fh e1 gain mode/29db itu g.703 120 w tp
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 130 t able 146: m icroprocessor r egister #336, b it d escription r egister a ddress 0 x 0f01 h 0 x 0f11 h 0 x 0f21 h 0 x 0f31 h 0 x 0f41 h 0 x 0f51 h 0 x 0f61 h 0 x 0f71 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 rxtsel_n receiver termination select: in host mode, this bit is used to select between the internal termination and high imped- ance modes for the receiver according to the following table; r/w 0 d6 txtsel_n transmit termination select: in host mode, this bit is used to select between the internal termination and high imped- ance modes for the transmitter according to the following table; r/w 0 d5 tersel1_n termination impedance select1: in host mode and in internal termination mode, (txtsel = 1 and rxtsel = 1) tersel[1:0] control the transmit and receive termination impedance according to the following table; in the internal termination mode, the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor. in the internal termination mode, the transmitter output should be ac coupled to the transformer. r/w 0 rxtsel rx termination 0 1 "high" impedance internal txtsel tx termination 0 1 "high" impedance internal tersel1 tersel0 0 0 0 1 1 0 1 1 termination 100 w 110 w 75 w 120 w
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 131 d4 tersel0_n termination impedance select bit 0: r/w 0 d3 rxjasel_n receive jitter attenuator enable the bit is used to enable the receive jitter attenuator. 0 = disabled 1 = enable the receive jitter attenuator r/w 0 d2 txjasel_n transmit jitter attenuator enable the bit is used to enable the transmit jitter attenuator. 0 = disabled 1 = enable the transmit jitter attenuator r/w 0 d1 jabw_n jitter attenuator bandwidth select: in e1 mode, set this bit to 1 to select a 1.5hz bandwidth for the jitter attenuator. the fifo length will be automatically set to 64 bits. set this bit to 0 to select 10hz bandwidth for the jitter attenuator in e1 mode. in t1 mode the jitter attenuator bandwidth is perma- nently set to 3hz, and the state of this bit has no effect on the bandwidth. r/w 0 d0 fifos_n fifo size select: see table of bit d1 above for the function of this bit. r/w 0 t able 147: m icroprocessor r egister #337, b it d escription r egister a ddress 0 x 0f02 h 0 x 0f12 h 0 x 0f22 h 0 x 0f32 h 0 x 0f42 h 0 x 0f52 h 0 x 0f62 h 0 x 0f72 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 invqrss_n invert qrss pattern: when tqrss is active, writing a 1 to this bit inverts the polarity of transmitted qrss pattern. writing a 0 sends the qrss pattern with no inversion. r/w 0 t able 146: m icroprocessor r egister #336, b it d escription 0 1 0 1 0 1 0 1 fifos_n bit d0 0 0 1 1 0 0 1 1 jabw bit d1 t1 t1 t1 t1 e1 e1 e1 e1 mode 32 64 32 64 32 64 64 64 fifo size 3 3 3 3 10 10 1.5 1.5 ja b-w hz
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 132 d6 txtest2_n transmit test pattern bit 2 : this bit together with txtest1 and txtest0 are used to generate and transmit test patterns according to the following table: tdqrss (transmit/detect quasi-random signal): this condition when activated enables quasi-random signal source generation and detection for the selected channel number n. in a t1 system qrss pattern is a 2 20 -1 pseudo- random bit sequence (prbs) with no more than 14 consecu- tive zeros. in a e1 system, qrss is a 2 15 -1 prbs pattern. taos (transmit all ones): activating this condition enables the transmission of an all ones pattern from the selected channel number n. tluc (transmit network loop-up code): activating this condition enables the network loop-up code of 00001 to be transmitted to the line for the selected channel number n. when network loop-up code is being transmitted, the XRT86L34 will ignore the automatic loop-code detection and remote loop-back activation (nlcde1 =1, nlcde0 =1, if activated) in order to avoid activating remote digital loop- back automatically when the remote terminal responds to the loop-back request. tldc (transmit network loop-down code): activating this condition enables the network loop-down code of 001 to be transmitted to the line for the selected channel number n. r/w 0 d5 txtest1_n transmit test pattern bit 1: see description of bit d6 for the function of this bit. r/w 0 d4 txtest0_n transmit test pattern bit 0: see description of bit d6 for the function of this bit. r/w 0 d3 txon_n transmitter on: writing a 1 into this bit location turns on the transmit section of channel n. writing a 0 shuts off the transmit section of channel n. in this mode, ttip_n and tring_n driver outputs will be tri-stated for power reduction or redundancy applications. r/w 0 t able 147: m icroprocessor r egister #337, b it d escription 0 0 0 1 1 0 1 1 1 1 1 1 x x 0 no pattern tdqrss taos tluc test pattern tldc txtest1 txtest0 txtest2
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 133 d2 loop2_n loop-back control bit 2: this bit together with the loop1 and loop0 bits control the loop-back modes of the liu sec- tion of the chip according to the following table: d1 loop1_n loop-back control bit 1: see description of bit d2 for the function of this bit. r/w 0 d0 loop0_n loop-back control bit 0: see description of bit d2 for the function of this bit. r/w 0 t able 148: m icroprocessor r egister #338, b it d escription r egister a ddress 0 x 0f03 h 0 x 0f13 h 0 x 0f23 h 0 x 0f33 h 0 x 0f43 h 0 x 0f53 h 0 x 0f63 h 0 x 0f73 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame t able 147: m icroprocessor r egister #337, b it d escription loop2 0 1 1 1 1 loop1 x 0 0 1 1 loop0 x 0 1 0 1 loop-back mode no loop-back dual loop-back analog loop-back remote loop-back digital loop-back
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 134 d7 nlcde1_n network loop code detection enable bit 1: this bit together with nlcde0_n control the loop-code detec- tion of each channel. when nlcde1 =0 and nlcde0 = 1 or nlcde1 = 1 and nlcde0 = 0, the chip is manually programmed to monitor the receive data for the loop-up or loop-down code respec- tively.when the presence of the 00001 or 001 pattern is detected for more than 5 seconds, the status of the nlcd bit is set to 1 and if the nlcd interrupt is enabled, an interrupt is initiated.the host has the option to control the loop-back function manually. setting the nlcde1 = 1 and nlcde0 = 1 enables the automatic loop-code detection and remote loop-back acti- vation mode. as this mode is initiated, the state of the nlcd interface bit is reset to 0 and the chip is programmed to mon- itor the receive data for the loop-up code. if the 00001 pat- tern is detected for longer than 5 seconds, the nlcd bit is set 1, remote loop-back is activated and the chip is automati- cally programmed to monitor the receive data for the loop- down code. the nlcd bit stays set even after the chip stops receiving the loop-up code. the remote loop-back condition is removed when the chip receives the loop-down code for more than 5 seconds or if the automatic loop-code detection mode is terminated. r/w 0 d6 nlcde0_n network loop code detection enable bit 0: see description of d7 for function of this bit. r/w 0 d5 reserved this bit is not used r/w 0 d4 rxres1_n receive external resistor control pin 1: in host mode, this bit along with the rxres0_n bit selects the value of the external receive fixed resistor according to the following table; r/w 0 d3 rxres0_n receive external resistor control pin 0: for function of this bit see description of d4 the rxres1_n bit. r/w 0 t able 148: m icroprocessor r egister #338, b it d escription nlcde1 nlcde0 0 0 0 1 1 0 1 1 function disable loop-code detection detect loop-up code in receive data detect loop-down code in receive data automatic loop-code detection rxres1_n 0 0 required fixed external rx resistor no external fixed resistor 240 w rxres0_n 0 1 1 1 210 w 150 w 0 1
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 135 d2 insbpv_n insert bipolar violation: when this bit transitions from 0 to 1, a bipolar violation is inserted in the transmitted data stream of the selected channel number n. bipolar violation can be inserted either in the qrss pattern, or input data when operating in single-rail mode. the state of this bit is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of a bipolar violation, a 0 should be written in this bit location before writing a 1. r/w 0 d1 insber_n insert bit error: with tdqrss enabled, when this bit transi- tions from 0 to 1, a bit error will be inserted in the transmit- ted qrss pattern of the selected channel number n. the state of this bit is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of bit error, a 0 should be written in this bit location before writing a 1. r/w 0 d0 reserved this bit is not used r/w 0 t able 149: m icroprocessor r egister #339, b it d escription r egister a ddress 0 x 0f04 h 0 x 0f14 h 0 x 0f24 h 0 x 0f34 h 0 x 0f44 h 0 x 0f54 h 0 x 0f64 h 0 x 0f74 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved this bit is not used ro 0 d6 dmoie_n dmo interrupt enable: writing a 1 to this bit enables dmo interrupt generation, writing a 0 masks it. r/w 0 d5 flsie_n fifo limit status interrupt enable: writing a 1 to this bit enables interrupt generation when the fifo limit is within to 3 bits, writing a 0 to masks it. r/w 0 d4 lcvie_n line code violation interrupt enable: writing a 1 to this bit enables line code violation interrupt generation, writing a 0 masks it. r/w 0 d3 nlcdie_n network loop-code detection interrupt enable: writing a 1 to this bit enables network loop-code detection interrupt generation, writing a 0 masks it. r/w 0 d2 aisdie_n ais interrupt enable: writing a 1 to this bit enables alarm indication signal detection interrupt generation, writing a 0 masks it. r/w 0 t able 148: m icroprocessor r egister #338, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 136 d1 rlosie_n receive loss of signal interrupt enable: writing a 1 to this bit enables loss of receive signal interrupt generation, writing a 0 masks it. r/w 0 d0 qrpdie_n qrss pattern detection interrupt enable: writing a 1 to this bit enables qrss pattern detection interrupt generation, writing a 0 masks it. r/w 0 t able 150: m icroprocessor r egister #340, b it d escription r egister a ddress 0 x 0f05 h 0 x 0f15 h 0 x 0f25 h 0 x 0f35 h 0 x 0f45 h 0 x 0f55 h 0 x 0f65 h 0 x 0f75 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved ro 0 d6 dmo_n driver monitor output: this bit is set to a 1 to indicate transmit driver failure is detected. the value of this bit is based on the current status of dmo for the corresponding channel. if the dmoie bit is enabled, any transition on this bit will gener- ate an interrupt. ro 0 d5 fls_n fifo limit status: this bit is set to a 1 to indicate that the jit- ter attenuator read/write fifo pointers are within +/- 3 bits. if the flsie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d4 lcv_n line code violation: this bit is set to a 1 to indicate that the receiver of channel n is currently detecting a line code viola- tion or an excessive number of zeros in the b8zs or hdb3 modes. if the lcvie bit is enabled, any transition on this bit will generate an interrupt. ro 0 t able 149: m icroprocessor r egister #339, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 137 d3 nlcd_n network loop-code detection: this bit operates differently in the manual or the automatic network loop-code detection modes. in the manual loop-code detection mode , (nlcde1 = 0 and nlcde0 = 1 or nlcde1 = 1 and nlcde0 = 0) this bit gets set to 1 as soon as the loop-up (00001) or loop- down (001) code is detected in the receive data for longer than 5 seconds. the nlcd bit stays in the 1 state for as long as the chip detects the presence of the loop-code in the receive data and it is reset to 0 as soon as it stops receiving it. in this mode, if the nlcd interrupt is enabled, the chip will initiate an interrupt on every transition of the nlcd. when the automatic loop-code detection mode, (nlcde1 = 1 and nlcde0 =1) is initiated, the state of the nlcd interface bit is reset to 0 and the chip is programmed to mon- itor the receive input data for the loop-up code. this bit is set to a 1 to indicate that the network loop code is detected for more than 5 seconds. simultaneously the remote loop-back condition is automatically activated and the chip is pro- grammed to monitor the receive data for the network loop down code. the nlcd bit stays in the 1 state for as long as the remote loop-back condition is in effect even if the chip stops receiving the loop-up code. remote loop-back is removed if the chip detects the 001 pattern for longer than 5 seconds in the receive data.detecting the 001 pattern also results in resetting the nlcd interface bit and initiating an interrupt provided the nlcd interrupt enable bit is active. when programmed in automatic detection mode, the nlcd interface bit stays high for the entire time the remote loop-back is active and initiate an interrupt anytime the status of the nlcd bit changes. in this mode, the host can monitor the state of the nlcd bit to determine if the remote loop- back is activated. ro 0 d2 aisd_n alarm indication signal detect: this bit is set to a 1 to indi- cate all ones signal is detected by the receiver. the value of this bit is based on the current status of alarm indication sig- nal detector of channel n. if the aisdie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d1 rlos_n receive loss of signal: this bit is set to a 1 to indicate that the receive input signal is lost. the value of this bit is based on the current status of the receive input signal of channel n. if the rlosie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d0 qrpd_n quasi-random pattern detection: this bit is set to a 1 to indicate the receiver is currently in synchronization with qrss pattern. the value of this bit is based on the current status of quasi-random pattern detector of channel n. if the qrpdie bit is enabled, any transition on this bit will generate an interrupt. ro 0 t able 150: m icroprocessor r egister #340, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 138 t able 151: m icroprocessor r egister #341, b it d escription r egister a ddress 0 x 0f06 h 0 x 0f16 h 0 x 0f26 h 0 x 0f36 h 0 x 0f46 h 0 x 0f56 h 0 x 0f66 h 0 x 0f76 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved ro 0 d6 dmois_n driver monitor output interrupt status: this bit is set to a 1 every time the dmo status has changed since last read. n ote : this bit is reset upon read. rur 0 d5 flsis_n fifo limit interrupt status: this bit is set to a 1 every time when fifo limit (read/write pointer with +/- 3 bits apart) sta- tus has changed since last read. n ote : this bit is reset upon read. rur 0 d4 lcvis_n line code violation interrupt status: this bit is set to a 1 every time when lcv status has changed since last read. n ote : this bit is reset upon read. rur 0 d3 nlcdis_n network loop-code detection interrupt status: this bit is set to a 1 every time when nlcd status has changed since last read. n ote : this bit is reset upon read. rur 0 d2 aisdis_n ais detection interrupt status: this bit is set to a 1 every time when aisd status has changed since last read. n ote : this bit is reset upon read. rur 0 d1 rlosis_n receive loss of signal interrupt status: this bit is set to a 1 every time rlos status has changed since last read. n ote : this bit is reset upon read. rur 0 d0 qrpdis_n quasi-random pattern detection interrupt status: this bit is set to a 1 every time when qrpd status has changed since last read. n ote : this bit is reset upon read. rur 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 139 t able 152: m icroprocessor r egister #342, b it d escription r egister a ddress 0 x 0f07 h 0 x 0f17 h 0 x 0f27 h 0 x 0f37 h 0 x 0f47 h 0 x 0f57 h 0 x 0f67 h 0 x 0f77 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved ro 0 d6 reserved ro 0 d5 clos5_n cable loss bit 5: clos[5:0]_n are the six bit receive selec- tive equalizer setting which is also a binary word that repre- sents the cable attenuation indication within 1db. clos5_n is the most significant bit (msb) and clos0_n is the least sig- nificant bit (lsb). ro 0 d4 clos4_n cable loss bit 4: see description of d5 for function of this bit. ro 0 d3 clos3_n cable loss bit 3: see description of d5 for function of this bit. ro 0 d2 clos2_n cable loss bit 2: see description of d5 for function of this bit. ro 0 d1 clos1_n cable loss bit 1: see description of d5 for function of this bit. ro 0 d0 clos0_n cable loss bit 0: see description of d5 for function of this bit. ro 0 t able 153: m icroprocessor r egister #343, b it d escription r egister a ddress 0 x 0f08 h 0 x 0f18 h 0 x 0f28 h 0 x 0f38 h 0 x 0f48 h 0 x 0f58 h 0 x 0f68 h 0 x 0f78 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 140 d7 reserved r/w 0 d6-d0 b6s1_n - b0s1_n arbitrary transmit pulse shape, segment 1: the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose com- bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the first time segment. b6s1_n- b0s1_n is in signed magnitude format with b6s1_n as the sign bit and b0s1_n as the least significant bit (lsb). r/w 0 t able 154: m icroprocessor r egister #344, b it d escription r egister a ddress 0 x 0f09 h 0 x 0f19 h 0 x 0f29 h 0 x 0f39 h 0 x 0f49 h 0 x 0f59 h 0 x 0f69 h 0 x 0f79 h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved r/w 0 d6-d0 b6s2_n - b0s2_n arbitrary transmit pulse shape, segment 2 the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the second time segment. b6s2_n- b0s2_n is in signed magnitude format with b6s2_n as the sign bit and b0s2_n as the least significant bit (lsb). r/w 0 t able 155: m icroprocessor r egister #345, b it d escription r egister a ddress 0 x 0f0a h 0 x 0f1a h 0 x 0f2a h 0 x 0f3a h 0 x 0f4a h 0 x 0f5a h 0 x 0f6a h 0 x 0f7a h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame t able 153: m icroprocessor r egister #343, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 141 d7 reserved r/w 0 d6-d0 b6s3_n - b0s3_n arbitrary transmit pulse shape, segment 3 the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the third time segment. b6s3_n- b0s3_n is in signed magnitude format with b6s3_n as the sign bit and b0s3_n as the least significant bit (lsb). r/w 0 t able 156: m icroprocessor r egister #346, b it d escription r egister a ddress 0 x 0f0b h 0 x 0f1b h 0 x 0f2b h 0 x 0f3b h 0 x 0f4b h 0 x 0f5b h 0 x 0f6b h 0 x 0f7b h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved r/w 0 d6-d0 b6s4_n - b0s4_n arbitrary transmit pulse shape, segment 4 the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the fourth time segment. b6s4_n- b0s4_n is in signed magnitude format with b6s4_n as the sign bit and b0s4_n as the least significant bit (lsb). r/w 0 t able 157: m icroprocessor r egister #347, b it d escription r egister a ddress 0 x 0f0c h 0 x 0f1c h 0 x 0f2c h 0 x 0f3c h 0 x 0f4c h 0 x 0f5c h 0 x 0f6c h 0 x 0f7c h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame t able 155: m icroprocessor r egister #345, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 142 d7 reserved r/w 0 d6-d0 b6s5_n - b0s5_n arbitrary transmit pulse shape, segment 5 the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the fifth time segment. b6s5_n- b0s5_n is in signed magnitude format with b6s5_n as the sign bit and b0s5_n as the least significant bit (lsb). r/w 0 t able 158: m icroprocessor r egister #348, b it d escription r egister a ddress 0 x 0f0d h 0 x 0f1d h 0 x 0f2d h 0 x 0f3d h 0 x 0f4d h 0 x 0f5d h 0 x 0f6d h 0 x 0f7d h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved r/w 0 d6-d0 b6s6_n - b0s6_n arbitrary transmit pulse shape, segment 6 the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the sixth time segment. b6s6_n- b0s6_n is in signed magnitude format with b6s6_n as the sign bit and b0s6_n as the least significant bit (lsb). r/w 0 t able 159: m icroprocessor r egister #349, b it d escription r egister a ddress 0 x 0f0e h 0 x 0f1e h 0 x 0f2e h 0 x 0f3e h 0 x 0f4e h 0 x 0f5e h 0 x 0f6e h 0 x 0f7e h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame t able 157: m icroprocessor r egister #347, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 143 d7 reserved r/w 0 d6-d0 b6s7_n - b0s7_n arbitrary transmit pulse shape, segment 7 the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the seventh time segment. b6s7_n-b0s7_n is in signed magnitude format with b6s7_n as the sign bit and b0s7_n as the least significant bit (lsb). r/w 0 t able 160: m icroprocessor r egister #350, b it d escription r egister a ddress 0 x 0f0f h 0 x 0f1f h 0 x 0f2f h 0 x 0f3f h 0 x 0f4f h 0 x 0f5f h 0 x 0f6f h 0 x 0f7f h c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 c hannel _4 c hannel _5 c hannel _6 c hannel _7 f unction r egister t ype r eset v alue b it #n ame d7 reserved r/w 0 d6-d0 b6s8_n - b0s8_n arbitrary transmit pulse shape, segment 8 the shape of each channel's transmitted pulse can be made independently user programmable by selecting arbitrary pulse mode. the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan- nel's arbitrary pulse during the eighth time segment. b6s8_n- b0s8_n is in signed magnitude format with b6s8_n as the sign bit and b0s8_n as the least significant bit (lsb). r/w 0 t able 159: m icroprocessor r egister #349, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 144 global control registers t able 161: m icroprocessor r egister #559, b it d escription r egister a ddress 0 x 0fe0 h n ame f unction r egister t ype r eset v alue b it # d7 reserved this bit is not used r/w 0 d6 ataos automatic transmit all ones upon rlos: writing a 1 to this bit enables the automatic transmission of all "ones" data to the line for the channel that detects an rlos condition. writing a 0 disables this feature. r/w 0 d5 reserved this bit is not used r/w 0 d4 reserved this bit is not used r/w 0 d3 reserved this bit is not used r/w 0 d2 reserved this bit is not used 0 d1 gie global interrupt enable: writing a 1 to this bit globally enables interrupt generation for all channels. writing a 0 disables interrupt generation. r/w 0 d0 sreset software reset m p registers: writing a 1 to this bit longer than 10s initiates a device reset through the microprocessor interface. all internal circuits are placed in the reset state with this bit set to a 1 except the microprocessor register bits. r/w 0 t able 162: m icroprocessor r egister #560, b it d escription r egister a ddress 0 x 0fe1 h n ame f unction r egister t ype r eset v alue b it # d7 reserved r/w 0 d6 reserved r/w 0 d5 d4 guage1 guage0 wire gauge selector bit 1: this bit together with bit d6 are used to select wire gauge size as shown in the table below. r/w 0 0 d3 reserved this bit is not used r/w 0 gauge1 0 1 1 0 gauge0 0 1 0 1 wire size 22 and 24 gauge 26 gauge 24 gauge 22 gauge
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 145 d2 rxmute receive output mute: writing a 1 to this bit, mutes receive outputs at the framer block to a 0 state for any channel that detects an rlos condition. n ote : the receive clock is not muted. r/w 0 d1 exlos extended los: writing a 1 to this bit extends the number of zeros at the receive input of each channel before rlos is declared to 4096 bits. writing a 0 reverts to the normal mode (175+75 bits for t1 and 32 bits for e1). r/w 0 d0 ict in-circuit-testing: writing a 1 to this bit configures all the output pins of the chip in high impedance mode for in-circuit- testing. r/w 0 t able 163: m icroprocessor r egister #561, b it d escription r egister a ddress 0 x 0fe2 h n ame f unction r egister t ype r eset v alue b it # d7 reserved this bit is not used r/w 0 d6 reserved this bit is not used r/w 0 d5-d0 reserved this bit is not used r/w 0 t able 164: m icroprocessor r egister #563, b it d escription r egister a ddress 0 x 0fe4 h n ame f unction r egister t ype r eset v alue b it # d7 d6 mclknt11 mclknt10 master t1 output clock reference these two bits are used to select the programmable output clock reference for t1mclknout. 00 = 1.544mhz 01 = 3.088mhz 10 = 6.176mhz 11 = 12.352mhz r/w 0 0 d5 d4 mclkne11 mclkne10 master e1 output clock reference these two bits are used to select the programmable output clock reference for e1mclknout. 00 = 2.048mhz 01 = 4.096mhz 10 = 8.192mhz 11 = 16.384mhz r/w 0 0 d3 reserved this bit is not used. r/w 0 d2 reserved this bit is not used. r/w 0 t able 162: m icroprocessor r egister #560, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 146 d1 reserved this bit is not used. r/w 0 d0 reserved this bit is not used. r/w 0 t able 165: m icroprocessor r egister #568, b it d escription r egister a ddress 0 x 0fe9 h n ame f unction r egister t ype r eset v alue b it # d7 reserved this bit is not used. r/w 0 d6 reserved this bit is not used. r/w 0 d5 reserved this bit is not used. r/w 0 d4 reserved this bit is not used. r/w 0 d3 d2 d1 d0 clksel3 clksel2 clksel1 clksel0 clock select input clksel[3:0] is used to select the input clock source to be used as the internal timing reference for mclkin. 0000 = 2.048mhz 0001 = 1.544mhz 0010 = 8khz 0011 = 16khz 0100 = 56khz 0101 = 64khz 0110 = 128khz 0111 = 256khz 1000 = 4.096mhz 1001 = 3.088mhz 1010 = 8.192mhz 1011 = 6.176mhz 1100 = 16.384mhz 1101 = 12.352mhz 1110 = 2.048mhz 1111 = 1.544mhz r/w 0 0 0 0 t able 166: m icroprocessor r egister #569, b it d escription r egister a ddress 0 x 0fea h n ame f unction r egister t ype r eset v alue b it # d7 gchis7 global channel 7 interrupt status indicator this bit indicates that a change in status on channel 7 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 t able 164: m icroprocessor r egister #563, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 147 d6 gchis6 global channel 6 interrupt status indicator this bit indicates that a change in status on channel 6 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 d5 gchis5 global channel 5 interrupt status indicator this bit indicates that a change in status on channel 5 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 d4 gchis4 global channel 4 interrupt status indicator this bit indicates that a change in status on channel 4 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 d3 gchis3 global channel 3 interrupt status indicator this bit indicates that a change in status on channel 3 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 d2 gchis2 global channel 2 interrupt status indicator this bit indicates that a change in status on channel 2 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 d1 gchis1 global channel 1 interrupt status indicator this bit indicates that a change in status on channel 1 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 d0 gchis0 global channel 0 interrupt status indicator this bit indicates that a change in status on channel 0 has occured regarding any interrupt generation that has been enabled. this register is reset upon read. rur 0 t able 166: m icroprocessor r egister #569, b it d escription
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 148 2.0 hdlc controllers and lapd the purpose of the hdlc controllers is to allow messages to be stored for transport in the outbound transmit framer block or extracted from the receive framer block through the lapd interface. each channel within the framer has 3 independent hdlc controllers. each hdlc controller has two 96-byte buffers for transmit and two 96-byte buffers for receive. the buffers are used to insert messages into the out going data stream for transmit or to extract messages from the incoming data stream from the receive path. total, there are twelve 96-byte buffers per channel. this allows multiple hdlc messages to be transported to and from exars fram- ing device. the following sections describe the procedure for transporting lapd messages using hdlc con- troller 1. hdlc controller 2 and hdlc controller 3 are implemented in the same manner, each having individ- ual control registers. see the register map/descriptions for more details. f igure 7. hdlc c ontrollers 2.1 ds1 t ransmit hdlc c ontroller b lock 2.1.1 description of the ds1 transmit hdlc controller block thre transmit framer block can insert data link information to outbound ds1 frames. the data link information in ds1 framing format can be inserted from: ? ds1 transmit overhead input interface block ? ds1 transmit hdlc controller ? ds1 transmit serial input interface the transmit data link source select [1:0] bits, within the transmit data link select register (tsdlsr) de- termine source of the data link bits (facility data link (fdl) bits in esf framing format mode, signaling fram- ing (fs) bits in slc?96 framing format mode and remote signaling (r) bits in t1dm framing format mode) to be inserted into the outgoing ds1 frames. buffer 0 buffer 1 transmit receive 96-bytes 96-bytes 96-bytes 96-bytes transmit receive 96-bytes 96-bytes 96-bytes 96-bytes transmit receive 96-bytes 96-bytes 96-bytes 96-bytes hdlc1 hdlc2 hdlc3 buffer 0 buffer 1 buffer 0 buffer 1 channel n
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 149 the table below shows configuration of the transmit data link source select [1:0] bits of the transmit data link select register (tsdlsr). if the transmit data link source select bits of the transmit data link select register are set to 00, the trans- mit hdlc controller block becomes input source of the data link bits in outgoing ds1 frames. each of the framers contains 3 ds1 transmit high-level data link controller (hdlc) blocks. the function of these blocks is to provide a serial data link channel in ds1 mode through the following: ? facility data link (fdl) bits in esf framing format mode ? signaling framing (fs) bits in slc?96 framing format mode ? remote signaling (r) bits in t1dm framing format mode ? d or e signaling timeslot channel data link bits are automatically inserted into the facility data link (fdl) bits in esf framing format mode, sig- naling framing (fs) bits in slc?96 framing format mode and remote signaling (r) bits in t1dm framing for- mat mode or forced to 1 by the framer. additionally, the user can define any one of the twenty-four ds0 timeslots to be d or e channel. we will discuss how to configure XRT86L34 to transmit data link information through d or e channels in a later section. each ds1 transmit hdlc controller block contains three major functional modules associated with ds1 fram- ing formats. they are the: ? slc?96 data link controller ? lapd controller ? bit-oriented signaling processor. there are two 96-byte transmit message buffers in shared memory for each of the 3 hdlc controllers to trans- mit data link information. when one message buffer is filled up, the transmit hdlc controller automatically switches to the next message buffer to load data link messages. these two message buffers ping-pong among each other for data link message transmission. the slc?96 enable bit and the lapd enable bit of the data link control register (dlcr) determines which one of the three functions is performed by the transmit hdlc controller block. the table below shows config- uration of the slc?96 enable bit of the data link control register (dlcr). transmit data link select register (tsdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 1-0 transmit data link source select [1:0] r/w 00 - the data link bits are inserted into the framer through the transmit hdlc control- ler/slc-96 fs bits. 01 - the data link bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. 10 - the data link bits are inserted into the framer through the transmit overhead input interface via the txoh_n pins. 11 - the data link bits are forced into 1. data link control register (dlcr) address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 7 slc?96 enable r/w 0 - in slc?96 framing mode, the data link transmission is disabled. the framer trans- mits the regular sf framing bits. in esf framing mode, the framer transmits regular esf framing bits and facility data link (fdl) bits. 1 - in slc?96 framing mode, the data link transmission is enabled. in esf framing mode, the framer transmits slc?96-like message in the facility data link bits.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 150 the table below shows configuration of the lapd enable bit of the data link control register (dlcr). 2.1.2 how to configure XRT86L34 to transmit data link information through d or e channels the XRT86L34 can configure any one or ones of the twenty-four ds0 channels to be d or e channels. d chan- nel is used primarily for data link applications. e channel is used primarily for signaling for circuit switching with multiple access configurations. the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of each channel determine whether that particular channel is configured as d or e channel. these bits also determine what type of data or signaling conditioning is applied to each channel. if the transmit data conditioning select [3:0] bits of the transmit channel control register of a particular timeslot are set to 1111, that timeslot is configured as a d or e timeslot. any d or e timeslot can be configured to take data link information from the following sources: ? ds1 transmit overhead output interface block ? ds1 transmit hdlc controller block ? ds1 transmit serial output interface block ? ds1 transmit fractional input interface block the transmit d or e channel source select [1:0] bits of the transmit data link select register (tsdlsr) de- termines which one of the above-mentioned modules to be input sources of d or e timeslot. the table below shows configuration of the transmit d or e channel source select [1:0] bits of the transmit data link select register (tsdlsr). for the transmit hdlc controller to be input source of d or e channel, the transmit d or e channel source select [1:0] bits of the transmit data link select register has to be set to 01. 2.1.3 transmit bos (bit oriented signaling) processor data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 0 lapd enable r/w 0 - the transmit hdlc controller will send out bit-oriented signaling (bos) message. 1 - the transmit hdlc controller will send out lapd protocol or so-called message- oriented signaling (mos) message. transmit channel control register (tccr) (address = 0xn300h - 0xn31fh) b it n umber b it n ame b it t ype b it d escription 3-0 transmit data conditioning select r/w 1111 - this channel is configured as d or e timeslot. transmit data link select register (tsdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 3-2 transmit d or e channel source select [1:0] r/w 00 - the data link bits are inserted into the d or e channel through the transmit serial data input interface via the txser_n pins. 01 - the data link bits are inserted into the d or e channel through the transmit hdlc controller. 10 - the data link bits are inserted into the d or e channel through the transmit serial data input interface via the txser_n pins. 11 - the data link bits are inserted into the d or e channel through the transmit frac- tional t1 input interface via the txfrt1_n pins.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 151 the transmit bos processor handles transmission of bos messages through the ds1 data link channel. it determines how many repetitions a certain bos message will be transmitted. it also inserts bos idle flag se- quence and abort sequence to be transmitted on the data link channel. in the later sections, we will discuss bos message format and how to transmit bos message. 2.1.3.1 description of bos bit-oriented signaling message is a sixteen-bit pattern carries the form of: (0d5d4d3d2d1d0011111111) where d5 is the msb and d0 is the lsb. the rightmost "1" is transmitted first. bit-oriented signaling message is classified into the following two groups: ? priority codeword message ? command and response information priority codeword message is preemptive and has the highest priority among all data link information. priority codeword information indicates a condition that is affecting the quality of service and thus shall be transmitted until the condition no longer exists. the duration of transmission should not be less than one second. priority codeword information may be interrupted by software for 100 milliseconds to send maintenance commands with a minimum interval of one second between interruptions. yellow alarm (00000000 11111111) is the only priority message defined in standard. command and response information is transmitted to perform various functions. the bos processor send command and response message by transmitting a minimum of 10 repetitions of the appropriate codeword pattern. command and response data transmission initiates action at the remote end, while the remote end will respond by sending bit-oriented response message to acknowledge the received commands. the activa- tion and deactivation of line loop-back and payload loop-back functions are this type of signal. 2.1.3.2 how to configure the bos processor block to transmit bos this section describes how to configure the bos processor block to transmit bos message in a step-by-step basis. 2.1.3.2.1 step 1: find out the next available transmit data link buffer to transmit a bit-oriented signal, a repeating message is sent of the form (0d5d4d3d2d1d001 1111111), where the "d5d4d3d2d1d0" represents a six-bit message. the user is recommended to read transmit data link byte count register for next available transmit data link buffer number. the table below shows how content of the buffer enable bit of the transmit data link byte count register (tdlbcr) determines what the next available transmit data link buffer number is. 2.1.3.2.2 step 2: write bos message into transmit data link buffer after finding out the next available transmit data link buffer, the user should write the eight bits message that are to be transmitted in the form (0d5d4d3d2d1d00) to the first location of the next available transmit data link buffer. the writing of these buffers is through the lapd buffer 0 indirect data registers and the lapd buffer1 indirect data registers. lapd buffer 0 and 1 indirect data registers have addresses 0xn600h and 0xn700h re- spectively. there is no indirect address register for transmit data link buffer 0 and 1. a microcontroller write access to the lapd buffer indirect data registers will access the transmit data link buffer and a microcontroller read will access the receive data link buffers. the very first write access to the lapd buffer indirect data register will always be direct to location 0 within the transmit data link buffer. transmit data link byte count register (tdlbcr) (address = 0xn114h) b it n umber b it n ame b it t ype b it d escription 7 buffer select r 0 - the next available transmit data link buffer for sending out bos or mos mes- sage is buffer 0. 1 - the next available transmit data link buffer for sending out bos or mos mes- sage is buffer 1.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 152 for example, if the bos message to be sent is (101011) and the next available transmit data link buffer of channel n is 1. the user should write pattern (01010110) into transmit data link buffer 1 of channel n. the fol- lowing microprocessor access to the framer should be done: wr n7h 56h 2.1.3.2.3 step 3: program bos message transmission repetitions the user should program the value of message transmission repetitions into the transmit data link byte count register. the framer will transmit the bos message the same number of times as was stored in the transmit data link byte count register (tdlbcr) before generating the transmit end of transfer (txeot) interrupts. if the value stored inside the transmit data link byte count register (tdlbcr) is set to 0, the message will be transmitted indefinitely and no transmit end of transfer interrupt will be generated. the table below shows configurations of the transmit data link byte count [6:0] bits the transmit data link byte count register (tdlbcr). 2.1.3.2.4 step 4: configure bos message transmission control bits configuration of the data link control register determines whether the bos processor will insert idle flag character or abort sequence to the data link channel. it also determines how the transition between mos mode to bos mode is done. if the idle insertion bit of the data link control register is set, repeated flags of value 0x7e are transmitted as soon as the current operation is finished (defined by the value in transmit data link byte count register). however, if the transmit data link byte count value is zero, the framer will not force a flag sequence on to the data link channel. the table below shows configurations of the idle insertion bit of the data link control register (dlcr). if the abort bit of the data link control register is set, a bos abort sequence (9 consecutive ones) is trans- mitted on the data link channel following by all-one transmission. in other words, all data link bits will be set to 1 after the transmission of the current message byte. transmit data link byte count register (tdlbcr) (address = 0xn114h) b it n umber b it n ame b it t ype b it d escription 6-0 transmit data link byte count [6:0] r/w value of these bits determines how many times a bos message pattern will be transmitted by the framer before generating the transmit end of transfer (txeot) interrupt. n ote : if these bits are set to 0, the bos message will be transmitted indefinitely and no transmit end of transfer interrupts will be generated. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 2 idle insertion r/w 0 - no flag sequence is sent on the data link channel. 1 - the framer forces a flag sequence of value 0x7e onto the data link channel.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 153 the table below shows configurations of the abort bit of the data link control register (dlcr). switching the data link channel from mos mode to bos mode while a message is being transmitted will inter- rupt the message after the octet in progress is transmitted. if the mos abort bit of the data link control reg- ister is set, a mos abort sequence (a zero followed by 7 ones) will be inserted before switching. switching the data link from bos to lapd will not take place until the current operation completes if transmit bos byte count is not set to zero initially. if the transmit bos byte count value is set to zero, the transition from bos mode to mos mode will take place right after finishing the current message octet. the table below shows configurations of the mos abort bit of the data link control register (dlcr). 2.1.3.2.5 step 5: enable transmit bos message interrupts the bos processor can generate a couple of interrupts indicating the status of bos message transmission to the microprocessor. these are the transmit start of transfer (txsot) interrupt and the transmit end of trans- fer (txeot) interrupt. to enable these interrupts, the transmit start of transfer enable bit and the transmit end of transfer enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the transmit start of transfer enable bit and the transmit end of transfer enable bit of the data link interrupt enable register. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 3 abort r/w 0 - no abort sequence is sent on the data link channel. 1 - the framer forces an abort sequence of pattern (111111111) onto the data link channel. all data link bits will be set to 1 after sending the abort sequence. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 6 mos abort r/w 0 - the framer forces an mos abort sequence of one zero and seven ones (01111111) onto the data link channel during the transition from mos mode to bos mode. 1 - no mos abort sequence is sent on the data link channel during the transi- tion from mos mode to bos mode. data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 6 transmit start of transfer enable r/w 0 - the transmit start of transfer interrupt is disabled. 1 - the transmit start of transfer interrupt is enabled. 4 transmit end of transfer enable r/w 0 - the transmit end of transfer interrupt is disabled. 1 - the transmit end of transfer interrupt is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 154 the table below shows configurations of the hdlc controller interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and the bos message is transmitted to the data link channel, the bos processor changes the transmit start of transfer and transmit end of transfer status bits of the data link status register (dlsr). these two status indicators are valid until the data link status register is read. reading these register clears the associated interrupt if reset upon read is selected in interrupt control reg- ister (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the transmit start of transfer and transmit end of transfer status bits of the data link status register. 2.1.3.2.6 step 6: bos message transmission a zero is then written into the lapd enable bit of data link control register, which sets the transmitter to bit- oriented mode and kicks off the transmission process. the lapd controller latches these control bits of the data link control register and send a transmit start of transfer interrupt (txsot) to the microprocessor to in- dicate that a bos message will be send. after the required number of times of bos message is sent, the lapd controller generates an transmit end of transfer interrupt (txeot) to the microprocessor to indicate that the bos message transmission comes to an end. the table below shows configurations of the lapd enable bit of the data link control register (dlcr). 2.1.4 transmit mos (message oriented signaling) or lapd controller the transmit lapd controller implements the message-oriented protocol based on itu recommendation q.921 link access procedures on the d-channel (lapd) type of protocol. it provides the following functions: ? zero stuffing ? t1/e1 transmitter interface block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 3 hdlc controller interrupt enable r/w 0 - every interrupt generated by the hdlc controller is disabled. 1 - every interrupt generated by the hdlc controller is enabled. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 6 transmit start of transfer rur / wc 0 - there is no data link message to be sent to the data link channel. 1 - the hdlc controller will send a data link message to the data link channel. 4 transmit end of transfer rur / wc 0 - no data link message was sent to the data link channel. 1 - the hdlc controller finished sending a data link message to the data link channel. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 0 lapd enable r/w 0 - the transmit hdlc controller will send out bit-oriented signaling (bos) message. 1 - the transmit hdlc controller will send out lapd protocol or so-called mes- sage-oriented signaling (mos) message.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 155 ? transmit message buffer access ? frame check sequence generation ? idle flag insertion ? abort sequence generation two 96-byte buffers in shared memory are allocated for lapd transmitter to reduce the frequency of micropro- cessor interrupts and alleviate the response time requirement for microprocessor to handle each interrupt. there are no restrictions on the length of the message. however the 96-byte buffer is deep enough to hold one entire lapd path or test signal identification message. figure 8 depicts the block diagram of both transmit and receive lapd controller. in the later sections, we will briefly discuss mos message format and how to configure the lapd controller to transmit mos message. 2.1.4.1 discussion of mos message-oriented signals (mos) sent by the transmit lapd controller are messages conforming to itu rec- ommendation q.921 lapd protocol as defined below. two types of message-oriented signals are defined. one is a periodic performance report generated by the source or sink t1/e1 terminals as defined by ansi t1.403. the other is a path or test signal identification mes- sage that may be optionally generated by a terminal or intermediate equipment on a t1/e1 circuit. message-oriented signals shall use the frame structure, field definitions and elements of procedure of the lapd protocol defined in itu recommendation q.921 except the address field. performance information is carried by message-oriented signal using lapd protocol. the message structures of the periodic performance f igure 8. lapd c ontroller
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 156 report and path or test signal identification message are shown in figure 9 in format a and format b respective- ly. 2.1.4.1.1 periodic performance report the ansi t1.403 standard requires that the status of the transmission quality be reported every one-second interval. the one-second timing may be derived from the ds1 signal or from a separate equally accurate (32ppm) source. the phase of the one-second periods with respect to the occurrence of error events is arbi- trary; that is, the one-second timing does not depend on the time of occurrence of any error event. a total of four seconds of information is transmitted so that recovery operations may be initiated in case an error corrupts a message. counts of events shall be accumulated in each contiguous one-second interval. at the end of each one-second interval, a modulo-4 counter shall be incremented, and the appropriate performance bits shall be set in bytes 5 and 6 in format a. these octets and the octets that carry the performance bits of the preceding three one-sec- ond intervals form the periodic performance report. the periodic performance report is made up of 14 bytes of data. bytes 1 to 4, 13, and 14 are the message header and bytes 5 to 12 contain data regarding the four most-recent one-second intervals. the periodic per- formance report message uses the sapi/tei value of 14. 2.1.4.1.2 transmission-error event occurrences of transmission-error events indicate the quality of transmission. the occurrences that shall be detected and reported are: ? crc error event: a crc-6 error event is the occurrence of a received crc code that is not identical to the corresponding locally calculated code. f igure 9. lapd f rame s tructure
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 157 ? severely errored framing event: a severely-errored-framing event is the occurrence of two or more framing- bit-pattern errors within a 3-ms period. contiguous 3-ms intervals shall be examined. the 3-ms period may coincide with the esf. the severely-errored-framing event, while similar in form to criteria for declaring a ter- minal has lost framing, is only designed as a performance indicator; existing terminal out-of-frame criteria will continue to serve as the basis for terminal alarms. ? frame-synchronization-bit error event: a frame-synchronization-bit-error event is the occurrence of a received framing-bit-pattern not meeting the severely-errored-framing event criteria. ? line-code violation event: a line-code violation event is a bipolar violation of the incoming data. a line-code violation event for an b8zs-coded signal is the occurrence of a received excessive zeros (exz) or a bipolar violation that is not part of a zero-substitution code. ? controlled slip event: a controlled-slip event is a replication, or deletion, of a t1 frame by the receiving ter- minal. a controlled slip may occur when there is a difference between the timing of a synchronous receiving terminal and the received signal. 2.1.4.1.3 path and test signal identification message the path identification message is used to identify the path between the source terminal and the sink terminal. the test signal identification message is used by test signal generating equipment. both identification messag- es are made up of 82 bytes of data. byte 1 to 4, 81 and 82 are the message header and bytes 5 to 80 contain six data elements. these messages use the sapi/tei value of 15 to differentiate themselves from the perfor- mance report message. 2.1.4.1.4 frame structure the message structure of message-oriented signal is shown in figure 9. two format types are shown in the figure: format a for frames which are sending performance report message and format b for frames which con- taining a path or test signal identification message. the following abbreviations are used: ? sapi: service access point identifier ? c/r: command or response ? ea: extended address ? tei: terminal endpoint identifier ? fcs: frame check sequence 2.1.4.1.5 flag sequence all frames shall start and end with the flag sequence consisting of one 0 bit followed by six contiguous 1 bits and one 0 bit. the flag preceding the address field is defined as the opening flag. the flag following the frame check sequence (fcs) field is defined as the closing flag. the closing flag may also serve as the opening flag of the next frame, in some applications. however, all receivers must be able to accommodate receipt of one or more consecutive flags. 2.1.4.1.6 address field the address field consists of two octets. a single octet address field is reserved for lapb operation in order to allow a single lapb data link connection to be multiplexed along with lapd data link connections. 2.1.4.1.7 address field extension bit (ea) the address field range is extended by reserving bit 1 of the address field octets to indicate the final octet of the address field. the presence of a 1 in bit 1 of an address field octet signals that it is the final octet of the ad- dress field. the double octet address field for lapd operation shall have bit 1 of the first octet set to a 0 and bit 1 of the second octet set to 1. 2.1.4.1.8 command or response bit (c/r) the command or response bit identifies a frame as either a command or a response. the user side shall send commands with the c/r bit set to 0, and responses with the c/r bit set to 1. the network side shall do the opposite; that is, commands are sent with c/r bit set to 1, and responses are sent with c/r bit set to 0. 2.1.4.1.9 service access point identifier (sapi) the service access point identifier identifies a point at which data link layer services are preceded by a data link layer entity type to a layer 3 or management entity. consequently, the sapi specifies a data link layer entity
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 158 type that should process a data link layer frame and also a layer 3 or management entity, which is to receive in- formation carried by the data link layer frame. the sapi allows 64 service access points to be specified, where bit 3 of the address field octet containing the sapi is the least significant binary digit and bit 8 is the most sig- nificant. sapi values are 14 and 15 for performance report message and path or test signal identification mes- sage respectively. 2.1.4.1.10 terminal endpoint identifier (tei) the tei sub-field allows 128 values where bit 2 of the address field octet containing the tei is the least signifi- cant binary digit and bit 8 is the most significant binary digit. the tei sub-field bit pattern 111 1111 (=127) is de- fined as the group tei. the group tei is assigned permanently to the broadcast data link connection associat- ed with the addressed service access point (sap). tei values other than 127 are used for the point-to-point data link connections associated with the addressed sap. non-automatic tei values (0-63) are selected by the user, and their allocation is the responsibility of the user. the network automatically selects and allocates tei values (64-126). 2.1.4.1.11 control field the control field identifies the type of frame which will be either a command or response. the control field shall consist of one or two octets. three types of control field formats are specified: 2-octet numbered information transfer (i format), 2-octet supervisory functions (s format), and single-octet unnumbered information transfers and control functions (u format). the control field for t1/e1 message is categorized as a single-octet unac- knowledged information transfer having the value 0x03. 2.1.4.1.12 frame check sequence (fcs) field the source of either the performance report or an identification message shall generate the frame check se- quence. the fcs field shall be a 16-bit sequence. it shall be the ones complement of the sum (modulo 2) of: ? the remainder of xk (x15 + x14 + x13 + x12 + x11 + x10 + x9 + x8 + x7 + x6 + x5 + x4 + x3 + x2 + x + 1) divided (modulo 2) by the generator polynomial x16 + x12 + x5 + 1, where k is the number of bits in the frame existing between, but not including, the final bit of the opening flag and the first bit of the fcs, excluding bits inserted for transparency, and ? the remainder of the division (modulo 2) by the generator polynomial x16 + x12 + x5 + 1, of the product of x16 by the content of the frame existing between, but not including, the final bit of the opening flag and the first bit of the fcs, excluding bits inserted for transparency. as a typical implementation at the transmitter, the initial content of the register of the device computing the re- mainder of the division is preset to all 1s and is then modified by division by the generator polynomial on the address, control and information fields; the ones complement of the resulting remainder is transmitted as the 16-bit fcs. as a typical implementation at the receiver, the initial content of the register of the device computing the re- mainder is preset to all 1s. the final remainder, after multiplication by x16 and then division (modulo 2) by the generator polynomial x16 + x12 + x5 + 1 of the serial incoming protected bits and the fcs, will be 0001110100001111 (x15 through x0, respectively) in the absence of transmission errors. 2.1.4.1.13 transparency (zero stuffing) a transmitting data link layer entity shall examine the frame content between the opening and closing flag se- quences, (address, control, information and fcs field) and shall insert a 0 bit after all sequences of five contig- uous 1 bits (including the last five bits of the fcs) to ensure that an idle flag or an abort sequence is not sim- ulated within the frame. a receiving data link layer entity shall examine the frame contents between the open- ing and closing flag sequences and shall discard any 0 bit which directly follows five contiguous 1 bits. 2.1.4.2 how to configure the transmit hdlc controller block to transmit mos this section describes how to configure the lapd controller block to transmit mos message in a step-by-step basis. 2.1.4.2.1 step 1: find out the next available transmit data link buffer to transmit mos message, the user is recommended to read transmit data link byte count register for next available transmit buffer number.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 159 the table below shows how contents of the buffer enable bit of the transmit data link byte count register (tdlbcr) determines what the next available transmit buffer number is. 2.1.4.2.2 step 2: write mos message into transmit data link buffer after finding out the next available transmit buffer, the user should write the entire message data to the avail- able transmit data link buffer via pio or dma access. the writing of these buffers is through the lapd buffer 0 indirect data registers and the lapd buffer1 indirect data registers. lapd buffer 0 and 1 indirect data registers have addresses 0xn600h and 0xn700h respectively. there is no indirect address register for transmit data link buffer 0 and 1. a microcontroller write access to the lapd buffer indirect data registers will access the transmit data link buffer and a microcontroller read will access the receive data link buffers. the very first write access to the lapd buffer indirect data register will always be direct to location 0 within the transmit data link buffer. the next write access to the lapd buffer indirect data register will be direct to location 1 within the transmit data link buffer and so on, until all 96 bytes of the transmit buffer is filled. for example, if the first byte of the mos message to be sent is (01010110) and the next available transmit data link buffer of channel n is 1. the user should write pattern (01010110) into transmit data link buffer 1 of chan- nel n. the following microprocessor access to the framer should be done: wr n7h 56h the first byte of mos message is written into location 0 of the transmit data link buffer. if the next byte of the mos message is (10100101), the user should perform another microprocessor write access: wr n7h a5h the second byte of mos message is written into location 1 of the transmit data link buffer. the write access should be repeated until the entire block of mos message is written into the transmit buffer or the transmit buff- er is completely filled. 2.1.4.2.3 step 3: program the transmit data link byte count register the user should program byte count of the mos message into the transmit data link byte count register af- ter the whole block of data is present in the buffer memory. the table below shows configurations of the transmit data link byte count [6:0] bits the transmit data link byte count register (tdlbcr). 2.1.4.2.4 step 4: configure mos message transmission control bits configuration of the data link control register determines whether the lapd controller will insert idle flag character, fcs or abort sequence to the data link channel. it also determines how the transition between mos mode to bos mode is done. transmit data link byte count register (tdlbcr) (address = 0xn114h) b it n umber b it n ame b it t ype b it d escription 7 buffer select r 0 - the next available transmit buffer for sending out bos or mos message is buffer 0. 1 - the next available transmit buffer for sending out bos or mos message is buffer 1. transmit data link byte count register (tdlbcr) (address = 0xn114h) b it n umber b it n ame b it t ype b it d escription 6-0 transmit data link byte count [6:0] r/w value of these bits determines length of the mos message pattern to be transmit- ted by the framer before generating the transmit end of transfer (txeot) inter- rupt.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 160 if the idle insertion bit of the data link control register is set, repeated flags of value 0x7e are transmitted as soon as the current operation is finished (defined by the value in transmit data link byte count register). the idle bit must be set to 1 at the last block of transfer to enable fcs and flag insertion for message completion. the table below shows configurations of the idle insertion bit of the data link control register (dlcr). n ote : if the entire message is longer than 96-byte in length or more than one full block of message has to be transmitted, the idle insertion bit should not be set to one until the last block of message has to be sent. if the fcs insertion bit of the data link control register (dlcr) is set to high, the lapd controller will calcu- late and insert the frame check sequence to the last block of the transmitted message. the table below shows configurations of the fcs insertion bit of the data link control register (dlcr). if the fcs is not enabled at the end of a message, the controller will return to sending idle flags immediately after the last octet is transmitted. this permits the use of a programmable fcs, which may be used for diag- nostic tests or other test applications. to abort a transmitting message, the lapd controller sets the abort bit in data link control register to 1. this bit is cleared after the lapd transmitter finishes sending the message octet in progress. the transmitter then transmit an abort sequence of one zero followed by seven ones (01111111) before goes to idle if the idle bit is set. the transmitter will keep transmitting idle flag characters until it is instructed otherwise. the table below shows configurations of the abort bit of the data link control register (dlcr). switching the data link channel from mos mode to bos mode while a message is being transmitted will inter- rupt the message after the octet in progress is transmitted. if the mos abort bit of the data link control reg- ister is set, a mos abort sequence (a zero followed by 7 ones) will be inserted before switching. switching the data link from bos to lapd will not take place until the current operation completes if transmit bos byte count is not set to zero initially. if the transmit bos byte count value is set to zero, the transition from bos mode to mos mode will take place right after finishing the current message octet. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 2 idle insertion r/w 0 - no flag sequence is sent on the data link channel. 1 - the framer forces a flag sequence of value 0x7e onto the data link channel. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 1 fcs insertion r/w 0 - no fcs will be inserted into the last block of the transmitted mos message. 1 - the lapd controller will calculate and insert the fcs into the last block of the transmitted mos message. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 3 abort r/w 0 - no abort sequence is sent on the data link channel. 1 - the framer forces an abort sequence of pattern (111111 10) onto the data link channel. idle flag pattern will be transmitted after the abort sequence is sent.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 161 the table below shows configurations of the mos abort bit of the data link control register (dlcr). 2.1.4.2.5 step 5: enable transmit mos message interrupts the lapd controller can generate a couple of interrupts indicating the status of mos message transmission to the microprocessor. these are the transmit start of transfer (txsot) interrupt and the transmit end of transfer (txeot) interrupt. to enable these interrupts, the transmit start of transfer enable bit and the transmit end of transfer enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the transmit start of transfer enable bit and the transmit end of transfer enable bit of the data link interrupt enable register. the table below shows configurations of the hdlc controller interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and the mos message is transmitted to the data link channel, the lapd controller changes the transmit start of transfer and transmit end of transfer status bits of the data link status register (dlsr). these two status indicators are valid until the data link status register is read. reading these register clears the associated interrupt if reset upon read is selected in interrupt control reg- ister (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 6 mos abort r/w 0 - the framer forces an mos abort sequence of one zero and seven ones [0111 1111] onto the data link channel during the trans ition from mos mode to bos mode. 1 - no mos abort sequence is sent on the data link channel during the transi- tion from mos mode to bos mode. data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 6 transmit start of transfer enable r/w 0 - the transmit start of transfer interrupt is disabled. 1 - the transmit start of transfer interrupt is enabled. 4 transmit end of transfer enable r/w 0 - the transmit end of transfer interrupt is disabled. 1 - the transmit end of transfer interrupt is enabled. block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 3 hdlc controller interrupt enable r/w 0 - every interrupt generated by the hdlc controller is disabled. 1 - every interrupt generated by the hdlc controller is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 162 the table below shows the transmit start of transfer and transmit end of transfer status bits of the data link status register. 2.1.4.2.6 step 6: mos message transmission a one is then written into the lapd enable bit of data link control register, which sets the transmitter to mes- sage-oriented mode and kicks off the transmission process. the lapd controller latches these control bits of the data link control register and send a transmit start of transfer interrupt (txsot) to the microprocessor to indicate that an mos message will be send. the lapd transmitter will then transmit the open flag character (01111110) in the data link bit position first fol- lowed by the entire message. if the message is longer than 96 bytes or more than one full block of data are to be transmitted, the alternating buffer usage approach will provide more adequate time to allow the writing of the message in the ping-pong buffers without overwriting good data in the transmitting buffer or repeating data because it was written too late. user must fill in data fast enough in ping-pong buffer concatenation scenario to avoid automatic flag insertion between two blocks of data that will cause far-end fcs errors. after the entire mos message is sent, the lapd controller generates the transmit end of transfer (txeot) interrupt to the microprocessor indicating that the mos message transmission is over. the table below shows configurations of the lapd enable bit of the data link control register (dlcr). 2.1.5 transmit slca96 data link controller the slc?96 t1 format is invented by at&t and is used between the digital switch and a slc?96 formatted remote terminal. the purpose of the slc?96 product is to provide standard telephone service or plain old telephone service (pots) in areas of high subscriber density but back-haul the traffic over t1 facilities. to support the slc?96 formatted remote terminal equipment, which is likely in an underground location, the t1s needed methods to: ? indicate equipment failures of the equipment to maintenance personal ? indicate failures of the pots lines ? test the pots lines ? provide redundancy on the t1s the slc?96 framing format is a d4 super-frame (sf) format with specialized data link information bits. these data link information bits take the position of the super-frame alignment (fs) bit positions. these bits consist of: data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 6 transmit start of transfer rur / wc 0 - there is no data link message to be sent to the data link channel. 1 - the hdlc controller will send a data link message to the data link channel. 4 transmit end of transfer rur / wc 0 - no data link message was sent to the data link channel. 1 - the hdlc controller finished sending a data link message to the data link channel. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 0 lapd enable r/w 0 - the transmit hdlc controller will send out bit-oriented signaling (bos) message. 1 - the transmit hdlc controller will send out lapd protocol or so-called mes- sage-oriented signaling (mos) message.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 163 ? concentrator bits (c, bit position 1 to 11) ? first spoiler bits (fs, bit position 12 to 14) ? maintenance bits (m, bit position 15 to 17) ? alarm bits (a, bit position 18 to 19) ? protection line switch bits (s, bit position 20 to 23) ? second spoiler bit (ss, bit position 24) ? resynchronization pattern (000111000111) in slca96 mode, six six-bit data will generate one 9-ms frame of the slca96 message format. the format of the data link message is given in bellcore tr-tsy-000008. to select this mode, the framing select bits of the framing select register (fsr) must be set to binary number 100. the table below shows configuration of the framing select bits of the framing select register (fsr). when slc?96 mode is enabled, the fs bit is replaced by the data link message read from memory at the be- ginning of each d4 super-frame. the XRT86L34 allocates two 6-byte buffers to provide the slc?96 data link controller an alternating access mechanism for information transmission. the bit ordering and usage is shown in the following table; and the lsb is sent first. note that these registers are memory-based storage and they need to be initialized. framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 2-0 t1 framing select r/w t1 framing select: these read/write bit-fields allow the user to select one of the five t1 framing formats supported by the framer. these framing formats include esf, slc ? 96, sf, n and t1dm mode. n ote : changing of framing format will automatically force the framer to resync. transmit slc ? 96 message registers b it b yte 543210 1011100 2c111100 3 c7c6c5c4c3c2 4 1 0 c11 c10 c9 c8 5 a2 a1m3m2m1 0 6 0 1 s4 s3 s2 s1 framing format bit 2 bit 1 bit 0 esf 0 x x slc?96 1 0 0 sf 1 0 1 n 1 1 0 t1dm 1 1 1
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 164 each register is read out of memory once every six sf super-frames. the memory holding these registers owns a shared memory structure that is used by multiple devices. these include ds1 transmit module, ds1 re- ceive module, transmit lapd controller, transmit slca96 data link controller, bit-oriented signaling proces- sor, receive lapd controller, receive slca96 data link controller, receive bit-oriented signaling proces- sor and microprocessor interface module. 2.1.5.1 how to configure the slc?96 data link controller to transmit slc?96 data link messages this section describes how to configure the slc?96 data link controller to transmit slc?96 data link mes- sage in a step-by-step basis. 2.1.5.1.1 step 1: find out the next available transmit data link buffer to transmit slc?96 data link message, the user is recommended to read transmit data link byte count register for next available transmit buffer number. the table below shows how contents of the buffer enable bit of the transmit data link byte count register (tdlbcr) determines what the next available transmit buffer number is. 2.1.5.1.2 step 2: write slc?96 data link message into transmit data link buffer after finding out the next available transmit buffer, the user should write the entire message data to the avail- able transmit data link buffer via pio or dma access. the writing of these buffers is through the lapd buffer 0 indirect data registers and the lapd buffer1 indirect data registers. lapd buffer 0 and 1 indirect data registers have addresses 0xn600h and 0xn700h respectively. there is no indirect address register for transmit data link buffer 0 and 1. a microcontroller write access to the lapd buffer indirect data registers will access the transmit data link buffer and a microcontroller read will access the receive data link buffers. the very first write access to the lapd buffer indirect data register will always be direct to location 0 within the transmit data link buffer. the next write access to the lapd buffer indirect data register will be direct to location 1 within the transmit data link buffer and so on, until all 96 bytes of the transmit buffer is filled. for example, if the first byte of the slc?96 data link message to be sent is (101011) and the next available transmit data link buffer of channel n is 1. the user should write pattern (00101011) into transmit data link buff- er 1 of channel n. the following microprocessor access to the framer should be done: wr n7h 2bh the first byte of the slc?96 data link message is written into location 0 of the transmit data link buffer. if the next byte of the data link message is (101001), the user should perform another microprocessor write ac- cess of pattern (00101001): wr n7h 29h the second byte of data link message is written into location 1 of the transmit data link buffer. the write ac- cess should be repeated until all six bytes of slc?96 data link message is written into the transmit buffer or the transmit buffer is completely filled. 2.1.5.1.3 step 3: enable transmit data link message interrupt the slc?96 data link controller can generate the transmit start of transfer (txsot) interrupt indicating the status of data link message transmission to the microprocessor. to enable this interrupt, the transmit start of transfer enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. transmit data link byte count register (tdlbcr) (address = 0xn114h) b it n umber b it n ame b it t ype b it d escription 7 buffer select r 0 - the next available transmit buffer for sending out bos or mos message is buffer 0. 1 - the next available transmit buffer for sending out bos or mos message is buffer 1.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 165 the table below shows configurations of the transmit start of transfer enable bit of the data link interrupt en- able register. the table below shows configurations of the hdlc controller interrupt enable bit of the block interrupt enable register. when this interrupt enable bit is set and the slc?96 data link message is transmitted to the data link chan- nel, the slc?96 data link controller changes the transmit start of transfer status bits of the data link status register (dlsr). this status indicator is valid until the data link status register is read. reading this register clears the associated interrupt if reset upon read is selected in interrupt control register (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indicators. the table below shows the transmit start of transfer and transmit end of transfer status bits of the data link status register. 2.1.5.1.4 step 4: program the data link control register to activate slc?96 data link transmission the slc?96 enable bit and the lapd enable bit of the data link control register (dlcr) determines which one of the three functions is performed by the transmit hdlc controller block. the table below shows config- uration of the slc?96 enable bit of the data link control register (dlcr). data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 6 transmit start of transfer enable r/w 0 - the transmit start of transfer interrupt is disabled. 1 - the transmit start of transfer interrupt is enabled. block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 3 hdlc controller interrupt enable r/w 0 - every interrupt generated by the hdlc controller is disabled. 1 - every interrupt generated by the hdlc controller is enabled. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 6 transmit start of transfer rur / wc 0 - there is no data link message to be sent to the data link channel. 1 - the slc?96 data link controller will send slc?96 data link message to the data link channel. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 7 slc?96 enable r/w 0 - in slc?96 framing mode, the data link transmission is disabled. the framer transmits the regular sf framing bits. in esf framing mode, the framer transmits regular esf framing bits and facility data link (fdl) bits. 1 - in slc?96 framing mode, the data link transmission is enabled. in esf framing mode, the framer transmits slc?96-like message in the facility data link bits.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 166 the table below shows configuration of the lapd enable bit of the data link control register (dlcr). to enable slc?96 data link transmission, the user has to set both of the slc?96 enable bit and the lapd enable bit of the data link control register to 1. without inputting new message, the data link controller will loop on the same message over and over again. to force the data link to output all ones is done by setting the abort bit in data link control register to 1. this operation takes place after the current message finishes transmitting. the table below shows configurations of the abort bit of the data link control register (dlcr). setting the slca96 bit low will switch the data link back to transfer normal framing bits after the current mes- sage transmit completes. 2.2 a utomatic p erformance r eport (apr) the apr feature allows the system to transmit pmon status within a lapd framing format a at one second intervals or within a single shot report. the data octets 5 through 12 within the lapd frame are replaced with the pmon status for the previous one second interval. t able 167: f raming f ormat for pmon s tatus i nserted within lapd by i nitiating apr data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 0 lapd enable r/w 0 - the transmit hdlc controller will send out bit-oriented signaling (bos) message. 1 - the transmit hdlc controller will send out lapd protocol or so-called mes- sage-oriented signaling (mos) message. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 3 abort r/w 0 - no abort sequence is sent on the data link channel. 1 - the framer forces an abort sequence of pattern (111111 10) onto the data link channel. octet number87654321time (s) 1 2 cr ea=0 3 ea=1 4 5 g3lvg4u1u2g5slg6 t 0 6 fe se lb g1 r g2 nm ni 7 g3lvg4u1u2g5slg6 t 0 - 1 8 fe se lb g1 r g2 nm ni 9 g3lvg4u1u2g5slg6 t 0 - 2 10 fe se lb g1 r g2 nm ni 11 g3 lv g4 u1 u2 g5 sl g6 t 0 - 3 12 fe se lb g1 r g2 nm ni 13 14 15 control = 00000011 = unacknowledged frame fcs flag = 01111110 flag = 01111110 sapi = 001110 tei = 0000000
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 167 n ote : the right most bit (bit 1) is transmitted first for all fields except for the two bytes of the fcs that are transmitted left most bit (bit 8) first. 2.2.1 bit value interpretation g1 = 1 if number of crc error events is equal to 1 g2 = 1 if number of crc error events is greater than 1 or equal to 5 g3 = 1 if number of crc error events is greater than 5 or equal to 10 g4 = 1 if number of crc error events is greater than 10 or equal to 100 g5 = 1 if number of crc error events is greater than 100 or equal to 319 g6 = 1 if number of crc error events is equal to 320 se = 1 if a severely errored framing event occurs (fe shall be 0) fe = 1 if a framing synchronization bit error event occurs (se shall be 0) lv = 1 if a line code violation event occurs sl = 1 if slip event within the slip buffer occurs lb = 1 if payload loopback is activated u1 = not used (default = 0) u2 = not used (default = 0) r = not used (default = 0) nmni = one second report module 4 count
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 168 2.3 ds1 r eceive hdlc c ontroller b lock 2.3.1 description of the ds1 receive hdlc controller block XRT86L34 allows user to extract data link information from incoming ds1 frames. the data link information in ds1raming format mode can be extracted to the following: ? ds1 receive overhead output interface block ? ds1 receive hdlc controller ? ds1 receive serial output interface the receive data link source select [1:0] bits, within the receive data link select register (rsdlsr) deter- mine destinations of the data link bits (facility data link (fdl) bits in esf framing format mode, signaling framing (fs) bits in slc?96 framing format mode and remote signaling (r) bits in t1dm framing format mode) extracted from the incoming ds1 frames. the table below shows configuration of the receive data link source select [1:0] bits of the receive data link select register (rsdlsr). if the receive data link source select bits of the receive data link select register are set to 00, the receive hdlc controller block becomes output destination of the data link bits in incoming ds1 frames. each of the four framers within the XRT86L34 device contains a ds1 receive high-level data link controller (hdlc) block. the function of this block is to establish a serial data link channel in ds1 mode through the fol- lowing: ? facility data link (fdl) bits in esf framing format mode ? signaling framing (fs) bits in slc?96 framing format mode ? remote signaling (r) bits in t1dm framing format mode ? d or e signaling timeslot channel data link bits are automatically inserted into the facility data link (fdl) bits in esf framing format mode, sig- naling framing (fs) bits in slc?96 framing format mode and remote signaling (r) bits in t1dm framing for- mat mode or forced to 1 by the framer. additionally, XRT86L34 allows the user to define any one of ones of the twenty-four ds0 timeslots to be d or e channel. we will discuss how to configure XRT86L34 to receive data link information through d or e channels in later section. the ds1 receive hdlc controller block contains three major functional modules associated with ds1 framing formats. they are the: ? slc?96 data link controller ? lapd controller ? bit-oriented signaling processor. there are two 96-byte receive message buffer in shared memory for each of the four framers to receive data link information. when one message buffer is filled up, the ds1 receive hdlc controller automatically switch- es to the next message buffer to store data link messages. these two message buffers ping-pong among each other for data link message storage. receive data link select register (rsdlsr) (address = 0xn10ch) b it n umber b it n ame b it t ype b it d escription 1-0 receive data link source select [1:0] r/w 00 - the data link bits extracted from the incoming ds1 frame are sent to the receive hdlc controller. 01 - the data link bits extracted from the incoming ds1 frame are sent to the receive serial data output interface via the rxser_n pins. 10 - the data link bits extracted from the incoming ds1 frame are sent to the receive overhead output interface via the rxoh_n pins. 11 - the data link bits are forced into 1.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 169 the slc?96 enable bit and the message type bit of the data link status register (dlsr) determines which one of the three messages is received and processed by the receive hdlc controller block. the table below shows configuration of the slc?96 enable bit of the data link control register (dlcr). the table below shows configuration of the message type bit of the data link status register (dlsr). 2.3.2 how to configure XRT86L34 to receive data link information through d or e channels the XRT86L34 can configure any one or ones of the twenty-four ds0 channels to be d or e channels. d chan- nel is used primarily for data link applications. e channel is used primarily for signaling for circuit switching with multiple access configurations. the receive conditioning select [3:0] bits of the receive channel control register (rccr) of each channel determine whether that particular channel is configured as d or e channel. these bits also determine what type of data or signaling conditioning is applied to each channel. if the receive conditioning select [3:0] bits of the receive channel control register of a particular timeslot are set to 1111, that timeslot is configured as a d or e timeslot. any d or e timeslot can be configured to direct data link information to the following destinations: ? ds1 receive overhead output interface block ? ds1 receive hdlc controller block ? ds1 receive serial output interface block ? ds1 receive fractional output interface block the receive d or e channel source select [1:0] bits of the receive data link select register (rsdlsr) de- termines which one of the above-mentioned modules to be output destinations of d or e timeslot. the table be- data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 7 slc?96 enable r/w 0 - in slc?96 framing mode, the data link transmission is disabled. the framer receives the regular sf framing bits. in esf framing mode, the framer receives regular esf framing bits and facility data link (fdl) bits. 1 - in slc?96 framing mode, the data link transmission is enabled. in esf framing mode, the framer receives slc?96-like message in the facility data link bits. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 7 message type rur / wc 0 - the receive hdlc controller receives and processes bit-oriented signaling (bos) message. 1 - the receive hdlc controller receives and processes lapd protocol or mes- sage-oriented signaling (mos) message. receive channel control register (rccr) (address = 0xn360h - 0xn37fh) b it n umber b it n ame b it t ype b it d escription 3-0 receive condition- ing select r/w 1111 - this channel is configured as d or e timeslot.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 170 low shows configuration of the receive d or e channel source select [1:0] bits of the receive data link se- lect register (rsdlsr). for the receive hdlc controller to be output destination of d or e channel, the receive d or e channel source select [1:0] bits of the receive data link select register has to be set to 01. 2.3.3 receive bos (bit oriented signaling) processor the receive bos processor handles receiving and processing of bos messages through the ds1 data link channel. it generates receive end of transfer (rxeot) interrupt each time a bos message is received and stores the bos message into the receive message buffer. in the later section, we will discuss how to configure the bos processor block to receive bos message. 2.3.3.1 how to configure the bos processor block to receive bos this section describes how to configure the bos processor block to receive bos message and how to read out the bos message. the operation of the receive bos processor is interrupt-driven. when a bos message is received, message octet is written to the next receive data link message buffer opposite to that last used. the receive bos processor generates interrupts to the microprocessor notifying it that a bos message is re- ceived. the bos message can then be extracted from the appropriate receive data link buffer. 2.3.3.1.1 step 1: enable receive bos message interrupts the bos processor can generate a couple of interrupts indicating the status of bos message received to the microprocessor. these are the receive start of transfer (rxsot) interrupt and the receive end of transfer (rxeot) interrupt. to enable these interrupts, the receive start of transfer enable bit and the receive end of transfer enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive start of transfer enable bit and the receive end of transfer enable bit of the data link interrupt enable register. receive data link select register (rsdlsr) (address = 0xn10ch) b it n umber b it n ame b it t ype b it d escription 3-2 receive d or e channel source select [1:0] r/w 00 - the data link bits extracted form the d or e channel of incoming ds1 frame are inserted into the receive serial data output interface via the rxser_n pins. 01 - the data link bits extracted form the d or e channel of incoming ds1 frame are inserted into the receive hdlc controller. 10 - the data link bits extracted form the d or e channel of incoming ds1 frame are inserted into the receive fractional t1 output interface via the rxfrt1_n pins. 11 - the data link bits extracted form the d or e channel of incoming ds1 frame are inserted into the receive serial data output interface via the rxser_n pins. data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 5 receive start of transfer enable r/w 0 - the receive start of transfer interrupt is disabled. 1 - the receive start of transfer interrupt is enabled. 3 receive end of transfer enable r/w 0 - the receive end of transfer interrupt is disabled. 1 - the receive end of transfer interrupt is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 171 the table below shows configurations of the hdlc controller interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and the bos message is received in the data link channel, the bos processor changes the receive start of transfer and receive end of transfer status bits of the data link sta- tus register (dlsr). these two status indicators are valid until the data link status register is read. reading these register clears the associated interrupt if reset upon read is selected in interrupt control register (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indicators. the table below shows the receive start of transfer and receive end of transfer status bits of the data link status register. the bos processor can also generate interrupts when either the bos abort sequence (nine consecutive ones) or the idle flag character (hexadecimal value of 0x7eh) is received in the data link channel to the mi- croprocessor. these are the receive abort sequence (rxabort) interrupt and the receive idle flag se- quence (rxidle) interrupt. to enable these interrupts, the receive abort sequence enable bit and the receive idle flag sequence enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive abort sequence enable bit and the receive idle flag sequence enable bit of the data link interrupt enable register. when these interrupt enable bits are set and the bos abort sequence or idle flag sequence is received in the data link channel, the bos processor changes the receive abort sequence and receive idle flag se- quence status bits of the data link status register (dlsr). these two status indicators are valid until the data link status register is read. reading these register clears the associated interrupt if reset upon read is se- block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 3 hdlc controller interrupt enable r/w 0 - every interrupt generated by the hdlc controller is disabled. 1 - every interrupt generated by the hdlc controller is enabled. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 5 receive start of transfer rur / wc 0 - there is no data link message in the data link channel. 1 - the hdlc controller began to receive a data link message in the data link channel. 3 receive end of transfer rur / wc 0 - no data link message was present in the data link channel. 1 - the hdlc controller finished receiving a data link message in the data link channel. data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 1 receive abort sequence enable r/w 0 - the receive abort sequence interrupt is disabled. 1 - the receive abort sequence interrupt is enabled. 0 receive idle flag sequence enable r/w 0 - the receive idle flag sequence interrupt is disabled. 1 - the receive idle flag sequence interrupt is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 172 lected in interrupt control register (icr). otherwise, a write-to-clear operation by the microprocessor is re- quired to reset these status indicators. the table below shows the receive abort sequence and receive idle flag sequence status bits of the da- ta link status register. 2.3.3.1.2 step 2: find out the next available receive data link buffer to transmit a bit-oriented signal, a repeating message is sent of the form (0d5d4d3d2d1d001 1111111), where the "d5d4d3d2d1d0" represents a six-bit message. when receiving a bos message, the received message octet is written to the next available receive data link buffer in the form of (0d5d4d3d2d1d00). the user is rec- ommended to read receive data link byte count register for next available receive data link buffer number. the table below shows how contents of the receive buffer pointer bit of the receive data link byte count register (rdlbcr) determines what the next available receive data link buffer number is. 2.3.3.1.3 step 3: program bos message receiving repetitions the user should program the value of message receiving repetitions into the receive data link byte count register. the framer will receive the bos message the same number of times as was stored in the receive data link byte count register (rdlbcr) before generating the receive end of transfer (rxeot) interrupts. if the value stored inside the receive data link byte count register (rdlbcr) is set to 0, the message will be received indefinitely and no receive end of transfer interrupt will be generated. the table below shows configurations of the receive data link byte count [6:0] bits the receive data link byte count register (rdlbcr). data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 1 receive abort sequence rur / wc 0 - there is no bos abort sequence received in the data link channel. 1 - the hdlc controller receives bos abort sequence in the data link chan- nel. 0 receive idle flag sequence rur / wc 0 - the message received in the data link channel is bos message. 1 - the message received in the data link channel is mos message. receive data link byte count register (rdlbcr) (address = 0xn115h) b it n umber b it n ame b it t ype b it d escription 7 receive buffer pointer r 0 - the next available receive data link buffer for reading out bos or mos mes- sage is buffer 0. 1 - the next available receive data link buffer for reading out bos or mos mes- sage is buffer 1. receive data link byte count register (rdlbcr) (address = 0xn115h) b it n umber b it n ame b it t ype b it d escription 6-0 receive data link byte count [6:0] r/w value of these bits determines how many times a bos message pattern will be received by the framer before generating the receive end of transfer (txeot) interrupt. n ote : if these bits are set to 0, the bos message will be received indefinitely and no receive end of transfer interrupts will be generated.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 173 2.3.3.1.4 step 4: read bos message from receive data link buffer upon detection of the receive end of transfer (rxeot) interrupt, the user should read the message type bit of the data link status register (dlsr) to find out what is the type of message received. the table below shows how contents of the message type bit of the data link status register (dlsr) deter- mines what the type of message received in the data link channel is. after determined that the received message is a bos one, the use should read eight bits message from the first location of the next available receive data link buffer. the reading of these buffers is through the lapd buffer 0 indirect data registers and the lapd buffer1 indirect data registers. lapd buffer 0 and 1 indirect data registers have addresses 0xn600h and 0xn700h respectively. there is no indirect address register for receive data link buffer 0 and 1. a microcontroller write access to the lapd buffer indirect data registers will access the receive data link buffer and a microcontroller read will access the receive data link buffers. the very first read access to the lapd buffer indirect data register will always be direct to location 0 within the receive data link buffer. for example, if the bos message to received is (101011) and the next available receive data link buffer of channel n is 1. the user should be able to read pattern (01010110) from receive data link buffer 1 of channel n. the following microprocessor access to the framer should be done: rd n7h the result of the read access should be 0x56h. 2.3.4 receive lapd controller the receive lapd controller implements the message-oriented protocol based on itu recommendation q.921 link access procedures on the d-channel (lapd) type of protocol. it provides the following functions: ? zero deletion ? pattern recognition for idle flag detection ? pattern recognition for abort sequence detection ? frame check sequence verification ? t1 receiver interface ? receive data link message buffer access two 96-byte buffers in shared memory are allocated for receive lapd controller to reduce the frequency of mi- croprocessor interrupts and alleviate the response time requirement for microprocessor to handle each inter- rupt. there are no restrictions on the length of the message received. however, the 96-byte buffer is deep enough to hold one entire lapd path or test signal identification message. the following section discuss how to configure the receive lapd controller to receive and extract mos mes- sages. 2.3.4.1 how to configure the receive hdlc controller block to receive mos message this section describes how to configure the lapd controller block to receive and extract mos message in a step-by-step basis. the operation of the receive lapd controller is interrupt-driven. when an mos message is receiving, mes- sage octets are written to the next receive data link message buffer opposite to that last used. each time the receiving data link message buffer is filled, a rxeot interrupt is issued if it is enabled. this process continues until an abort sequence is received or an idle flag is received. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 7 message type rur / wc 0 - there is no bos abort sequence received in the data link channel. 1 - the hdlc controller receives bos abort sequence in the data link chan- nel.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 174 an interrupt is issued when one of the following conditions occurs and the corresponding interrupt enable bit is set. ? the rxsot is set when the beginning of a data link message is received (the first non-flag message). ? the rxeot is set when the end of a data link block is received. ? the rxidle is set if an idle flag sequence (b01111110) is received on the data link after either an abort sequence is received or a complete message is received. ? the rxabort is set when an abort sequence is received. ? the fcs_err is issued when an erroneous frame check sequence is detected at the end of a message or an idle flag is received that is not octet aligned. 2.3.4.1.1 step 1: enable receive mos message interrupts the receive lapd controller can generate a couple of interrupts indicating the status of mos message re- ceived to the microprocessor. these are the receive start of transfer (rxsot) interrupt and the receive end of transfer (rxeot) interrupt. to enable these interrupts, the receive start of transfer enable bit and the receive end of transfer enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive start of transfer enable bit and the receive end of transfer enable bit of the data link interrupt enable register. the table below shows configurations of the hdlc controller interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and the mos message is received in the data link channel, the lapd controller changes the receive start of transfer and receive end of transfer status bits of the data link sta- tus register (dlsr). these two status indicators are valid until the data link status register is read. reading these register clears the associated interrupt if reset upon read is selected in interrupt control register (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indicators. data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 5 receive start of transfer enable r/w 0 - the receive start of transfer interrupt is disabled. 1 - the receive start of transfer interrupt is enabled. 3 receive end of transfer enable r/w 0 - the receive end of transfer interrupt is disabled. 1 - the receive end of transfer interrupt is enabled. block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 3 hdlc controller interrupt enable r/w 0 - every interrupt generated by the hdlc controller is disabled. 1 - every interrupt generated by the hdlc controller is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 175 the table below shows the receive start of transfer and receive end of transfer status bits of the data link status register. the lapd controller can also generate interrupts when either the mos abort sequence (seven consecutive ones) or the idle flag character (hexadecimal value of 0x7eh) is received in the data link channel to the mi- croprocessor. these are the receive abort sequence (rxabort) interrupt and the receive idle flag se- quence (rxidle) interrupt. to enable these interrupts, the receive abort sequence enable bit and the receive idle flag sequence enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive abort sequence enable bit and the receive idle flag sequence enable bit of the data link interrupt enable register. when these interrupt enable bits are set and the mos abort sequence or idle flag sequence is received in the data link channel, the lapd controller changes the receive abort sequence and receive idle flag sequence status bits of the data link status register (dlsr). these two status indicators are valid until the data link status register is read. reading these register clears the associated interrupt if reset upon read is selected in interrupt control register (icr). otherwise, a write-to-clear operation by the microprocessor is re- quired to reset these status indicators. the table below shows the receive abort sequence and receive idle flag sequence status bits of the da- ta link status register. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 5 receive start of transfer rur / wc 0 - there is no data link message in the data link channel. 1 - the hdlc controller began to receive a data link message in the data link channel. 3 receive end of transfer rur / wc 0 - no data link message was present in the data link channel. 1 - the hdlc controller finished receiving a data link message in the data link channel. data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 1 receive abort sequence enable r/w 0 - the receive abort sequence interrupt is disabled. 1 - the receive abort sequence interrupt is enabled. 0 receive idle flag sequence enable r/w 0 - the receive idle flag sequence interrupt is disabled. 1 - the receive idle flag sequence interrupt is enabled. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 1 receive abort sequence rur / wc 0 - there is no bos abort sequence received in the data link channel. 1 - the hdlc controller receives mos abort sequence in the data link chan- nel. 0 receive idle flag sequence rur / wc 0 - the message received in the data link channel is bos message. 1 - the message received in the data link channel is mos message.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 176 finally, the lapd controller generates frame check sequence error (fcs_err) interrupt when an erroneous frame check sequence is detected at the end of a message or an idle flag is received that is not octet aligned. to enable this interrupt, the frame check sequence error detection enable bit of the data link interrupt en- able register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block inter- rupt enable register (bier) needs to be one. the table below shows configurations of the frame check sequence error detection enable bit of the data link interrupt enable register. when the frame check sequence error detection interrupt enable bits is set and an erroneous frame check sequence is detected at the end of a message, the lapd controller changes the frame check sequence er- ror detection status bits of the data link status register (dlsr). this status indicator is valid until the data link status register is read. reading this register clears the associated interrupt if reset upon read is select- ed in interrupt control register (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset this status indicator. the table below shows the frame check sequence error detection status bits of the data link status regis- ter. 2.3.4.1.2 step 2: find out the next available receive data link buffer when the lapd controller is receiving mos message, the received message octets are written to the next available receive data link buffer. the user is recommended to read receive data link byte count register for next available receive data link buffer number. the table below shows how contents of the receive buffer pointer bit of the receive data link byte count register (rdlbcr) determines what the next available receive data link buffer number is. 2.3.4.1.3 step 3: reading the receive data link byte count register the user should read the length of mos message from the receive data link byte count register. the re- ceive lapd controller increments the receive data link byte count register value when each octet of mos data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 2 frame check sequence error detection enable r/w 0 - the frame check sequence error detection interrupt is disabled. 1 - the frame check sequence error detection interrupt is enabled. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 2 frame check sequence error detection rur / wc 0 - there is no fcs error detected in the data link channel. 1 - the hdlc controller receives an erroneous fcs in the data link channel. receive data link byte count register (rdlbcr) (address = 0xn115h) b it n umber b it n ame b it t ype b it d escription 7 receive buffer pointer r 0 - the next available receive data link buffer for reading out bos or mos mes- sage is buffer 0. 1 - the next available receive data link buffer for reading out bos or mos mes- sage is buffer 1.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 177 message is received. after the receive end of transfer (rxeot) interrupt is generated, the receive data link byte count register should contain the length of entire mos message. the table below shows configurations of the receive data link byte count [6:0] bits of the receive data link byte count register (rdlbcr). 2.3.4.1.4 step 4: read mos message from receive data link buffer upon detection of the receive end of transfer (rxeot) interrupt, the user should read the message type bit of the data link status register (dlsr) to find out what is the type of message received. the table below shows how contents of the message type bit of the data link status register (dlsr) deter- mines what the type of message received in the data link channel is. after determined that the received message is an mos one, the use should read the entire message from the available receive data link buffer. the reading of these buffers is through the lapd buffer 0 indirect data regis- ters and the lapd buffer1 indirect data registers. lapd buffer 0 and 1 indirect data registers have addresses 0xn600h and 0xn700h respectively. there is no indirect address register for receive data link buffer 0 and 1. a microcontroller write access to the lapd buffer indirect data registers will access the receive data link buffer and a microcontroller read will access the receive data link buffers. the very first read access to the lapd buffer indirect data register will always be direct to location 0 within the receive data link buffer. for example, if the first octet of the mos message received is (10101100) and the next available receive data link buffer of channel n is 1. the user should be able to read pattern (01010110) from receive data link buffer 1 of channel n. the following microprocessor access to the framer should be done: rd n700h the result of the read access should be 0xach. 2.3.5 receive slca96 data link controller this section describes how to configure the receive slc?96 data link controller block to receive slc?96 data link message and how to read out the message from the receive data link message buffer. the operation of the receive slc?96 data link controller is interrupt-driven. when a 36-bit slc?96 data link message is received, message octet is written to the next receive data link message buffer opposite to that last used. the receive slc?96 data link controller generates interrupts to the microprocessor notifying it that a message is received. the data link message can then be extracted from the appropriate receive data link buffer. in order to enable this mode of operation, the framing mode must be set to slc?96. the XRT86L34 allocates two 6-byte buffers to provide slc?96 data link controller an alternating access mechanism for information receive data link byte count register (rdlbcr) (address = 0xn115h) b it n umber b it n ame b it t ype b it d escription 6-0 receive data link byte count [6:0] r value of these bits determines how many times a bos message pattern will be received by the framer before generating the receive end of transfer (txeot) interrupt. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 7 message type rur / wc 0 - message received in the data link channel is bos. 1 - message received in the data link channel is mos.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 178 received. the bit ordering and usage is shown in the following table. the bits 7 and 6 are forced to 0 by the slc?96 data link controller. 2.3.5.1 how to configure the slc?96 data link controller to receive slc?96 data link messages this section describes how to configure the slc?96 data link controller to receive slc?96 data link mes- sage in a step-by-step basis. the operation of the receive slc?96 data link controller is interrupt-driven. when an slc?96 data link message is receiving, message octets are written to the next receive data link message buffer opposite to that last used. every time the slc?96 data link controller receives a 36-bit slc?96 data link message, an rxeot interrupt is issued if it is enabled. this process continues until an abort sequence is received. an interrupt is issued when one of the following conditions occurs and the corresponding interrupt enable bit is set. ? the rxsot is set when the beginning of a data link message is received. ? the rxeot is set when the end of a data link block is received. ? the rxabort is set when an abort sequence is received. 2.3.5.1.1 step 1: enable receive slc?96 data link message interrupts the receive slc?96 data link controller can generate a couple of interrupts indicating the status of slc?96 message received to the microprocessor. these are the receive start of transfer (rxsot) interrupt and the receive end of transfer (rxeot) interrupt. to enable these interrupts, the receive start of transfer enable bit and the receive end of transfer enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive start of transfer enable bit and the receive end of transfer enable bit of the data link interrupt enable register. receive slc ? 96 message registers b it b yte 76543210 1/7 00011100 2/8 00c111100 3/9 0 0 c7c6c5c4c3c2 4/10 0010c11c10c9c8 5/11 0 0 a2 a1 m3 m2 m1 0 6/12 0001s4s3s2s1 data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 5 receive start of transfer enable r/w 0 - the receive start of transfer interrupt is disabled. 1 - the receive start of transfer interrupt is enabled. 3 receive end of transfer enable r/w 0 - the receive end of transfer interrupt is disabled. 1 - the receive end of transfer interrupt is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 179 the table below shows configurations of the hdlc controller interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and the slc?96 message is received in the data link channel, the slc?96 data link controller changes the receive start of transfer and receive end of transfer status bits of the data link status register (dlsr). these two status indicators are valid until the data link status register is read. reading these register clears the associated interrupt if reset upon read is selected in interrupt con- trol register (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these sta- tus indicators. the table below shows the receive start of transfer and receive end of transfer status bits of the data link status register. the slc?96 data link controller can also generate interrupts when the abort sequence is received in the data link channel to the microprocessor. this is the receive abort sequence (rxabort). to enable this interrupt, the receive abort sequence enable bit of the data link interrupt enable register (dlier) have to be set. in addition, the hdlc controller interrupt enable bit of the block interrupt enable reg- ister (bier) needs to be one. the table below shows configurations of the receive abort sequence enable bit and the receive idle flag sequence enable bit of the data link interrupt enable register. when these interrupt enable bits are set and the slc?96 abort sequence is received in the data link chan- nel, the slc?96 data link controller changes the receive abort sequence status bit of the data link sta- tus register (dlsr). this status indicator is valid until the data link status register is read. reading the reg- ister clears the associated interrupt if reset upon read is selected in interrupt control register (icr). other- wise, a write-to-clear operation by the microprocessor is required to reset these status indicators. block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 3 hdlc controller interrupt enable r/w 0 - every interrupt generated by the hdlc controller is disabled. 1 - every interrupt generated by the hdlc controller is enabled. data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 5 receive start of transfer rur / wc 0 - there is no data link message in the data link channel. 1 - the slc?96 data link controller began to receive a data link message in the data link channel. 3 receive end of transfer rur / wc 0 - no data link message was present in the data link channel. 1 - the slc?96 data link controller finished receiving a data link message in the data link channel. data link interrupt enable register (dlier) (address = 0xnb07h) b it n umber b it n ame b it t ype b it d escription 1 receive abort sequence enable r/w 0 - the receive abort sequence interrupt is disabled. 1 - the receive abort sequence interrupt is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 180 the table below shows the receive abort sequence status bit of the data link status register. 2.3.5.1.2 step 2: find out the next available receive data link buffer when the slc?96 data link controller is receiving slc?96 message, the received message octets are writ- ten to the next available receive data link buffer. the user is recommended to read receive data link byte count register for next available receive data link buffer number. the table below shows how contents of the receive buffer pointer bit of the receive data link byte count register (rdlbcr) determines what the next available receive data link buffer number is. 2.3.5.1.3 step 3: read slc?96 data link message from receive data link buffer upon detection of the receive end of transfer (rxeot) interrupt, the use should read the entire slc?96 data link message from the available receive data link buffer. the reading of these buffers is through the lapd buffer 0 indirect data registers and the lapd buffer1 indirect data registers. lapd buffer 0 and 1 indirect data registers have addresses 0xn600h and 0xn700h respectively. there is no indirect address register for receive data link buffer 0 and 1. a microcontroller write access to the lapd buffer indirect data registers will access the receive data link buffer and a microcontroller read will access the receive data link buffers. the very first read access to the lapd buffer indirect data register will always be direct to location 0 within the receive data link buffer. for example, if the first octet of the slc?96 message received is (00101011) and the next available receive data link buffer of channel n is 1. the user should be able to read pattern (00101011) from receive data link buffer 1 of channel n. the following microprocessor access to the framer should be done: rd n700h the result of the read access should be 0x2bh. 2.4 ss7 (s ignaling s ystem n umber 7) to support ss7 specifications while receiving lapd messages, exars framer will generate an interrupt (if ss7 is enabled) once the hdlc controllers have received more than 276 bytes within two flag sequences (0x7e) of a lapd message. each hdlc controller supports ss7. for example: to enable ss7 for all hdlc controllers, registers 0xnb11 (lapd1), 0xnb19 (lapd2), 0xnb29 (lapd3) must be set to 0x01. 2.5 e1 t ransmit hdlc c ontroller b lock 2.5.1 description of the e1 transmit hdlc controller block XRT86L34 allows user to insert data link information to outbound e1 frames. the data link information in e1 framing format mode can be inserted from: ? e1 transmit overhead input interface block data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 1 receive abort sequence rur / wc 0 - there is no bos abort sequence received in the data link channel. 1 - the slc?96 data link controller receives abort sequence in the data link channel. receive data link byte count register (rdlbcr) (address = 0xn115h) b it n umber b it n ame b it t ype b it d escription 7 receive buffer pointer r 0 - the next available receive data link buffer for reading out data link message is buffer 0. 1 - the next available receive data link buffer for reading out data link message is buffer 1.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 181 ? e1 transmit hdlc controller ? e1 transmit serial input interface the transmit data link source select [1:0] bits, within the synchronization mux register (smr) determine source of the data link bits to be inserted into the outgoing e1 frames. the table below shows configuration of the transmit data link source select [1:0] bits of the synchronization mux register (smr). if the transmit data link source select bits of the transmit data link select register are set to 01, the trans- mit hdlc controller block becomes input source of the data link bits in outgoing e1 frames. each of the four framers within the XRT86L34 device contains an e1 transmit high-level data link controller (hdlc) block. the function of this block is to provide a serial data link channel in e1 mode through the follow- ing: ? the national bits (sa4 through sa8) of timeslot 0 of non-fas frame ? timeslot 16 octet when the framer is in common channel signaling mode ? d or e signaling timeslot channel we will discuss how to configure XRT86L34 to transmit data link information through each of these data link channels in later sections. the e1 transmit hdlc controller block contains two major functional modules associated with e1 framing for- mats. they are the lapd controller and the bit-oriented signaling processor. there are two 96-byte transmit message buffers in shared memory for each of the four framers to transmit data link information. when one message buffer is filled up, the transmit hdlc controller automatically switches to the next message buffer to load data link messages. these two message buffers ping-pong among each other for data link message transmission. the lapd enable bit of the data link control register (dlcr) determines whether the transmit hdlc con- troller block should perform as the lapd controller or the bos processor. the table below shows configuration of the lapd enable bit of the data link control register (dlcr). 2.5.2 how to configure XRT86L34 to transmit data link information through the national bits (sa4 through sa8) synchronization mux register (smr) (address = 0xn109h) b it n umber b it n ame b it t ype b it d escription 3-2 transmit data link source select [1:0] r/w 00 - the data link bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. 01 - the data link bits are inserted into the framer through the transmit hdlc controller. 10 - the data link bits are inserted into the framer through the transmit overhead input interface via the txoh_n pins. 11 - the data link bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. data link control register (dlcr) (address = 0xn113h) b it n umber b it n ame b it t ype b it d escription 0 lapd enable r/w 0 - the transmit hdlc controller will send out bit-oriented signaling (bos) message. 1 - the transmit hdlc controller will send out lapd protocol or so-called mes- sage-oriented signaling (mos) message.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 182 as mentioned in previous section, the national bits (sa4 through sa8) of timeslot 0 of non-fas frame can be used to transmit data link information in e1 mode. the XRT86L34 allows the user to decide on the following: ? whether the national bits will be used to carry the data link information bits. ? how many of the national bits will be used to carry the data link information bits. ? which of these national bits will be used to carry the data link information bits. the transmit signaling and data link control [2:0] bits of the transmit signaling and data link select register (tsdlsr) determines if the national bits will be used to carry data link information. the table below shows configuration of the transmit signaling and data link control [2:0] bits of the transmit signaling and data link select register (tsdlsr). if the transmit signaling and data link select [2:0] bits of the transmit signaling and data link select register is set to 000 or 001, the data link interface becomes source of the sa4 through sa8 national bits. the transmit sa data link select bits of the transmit signaling and data link select register (tsdlsr) de- termine which ones of the national bits are configured as data link bits in e1 framing format mode. depending upon the configuration of the transmit signaling and data link select register, either of the following cases may exists: ? none of the national bits are used to transport the data link information bits (that is, data link channel of XRT86L34 is inactive). ? any combination of between 1 and all 5 of the national bits can be selected to transport the data link infor- mation bits. the table below shows configuration of the transmit sa data link select bits of the transmit signaling and da- ta link select register (tsdlsr). transmit signaling and data link select register (tsdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 2-0 transmit signaling and data link select r/w 000 - the data link interface is source of the sa4 through sa8 nation bits. 001 - the data link interface is source of the sa4 through sa8 nation bits. 010 - the sa4 through sa8 nation bits are forced to 1. 011 - the sa4 through sa8 nation bits are forced to 1. 1xx - the sa4 through sa8 nation bits are forced to 1. transmit signaling and data link select register (tsdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 7 transmit sa8 data link select r/w 0 - source of the sa8 nation bit is not from the data link interface. 1 - source the sa8 national bit from the data link interface. 6 transmit sa7 data link select r/w 0 - source of the sa7 nation bit is not from the data link interface. 1 - source the sa7 national bit from the data link interface. 5 transmit sa6 data link select r/w 0 - source of the sa6 nation bit is not from the data link interface. 1 - source the sa6 national bit from the data link interface. 4 transmit sa5 data link select r/w 0 - source of the sa5 nation bit is not from the data link interface. 1 - source the sa5 national bit from the data link interface. 3 transmit sa4 data link select r/w 0 - source of the sa4 nation bit is not from the data link interface. 1 - source the sa4 national bit from the data link interface.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 183 2.5.3 how to configure XRT86L34 to transmit data link information through timeslot 16 octet in e1 mode, timeslot 16 octet can be configured to transmit the following: ? channel associated signaling (cas) bits a, b, c and d ? common channel signaling (ccs) bits the common channel signaling (ccs) messages are actually data link information applicable to all thirty-two timeslots of an e1 frame, thus the name common channel signaling. the transmit signaling and data link control [2:0] bits of the transmit signaling and data link select register (tsdlsr) determine if timeslot octet will be used to carry data link information or cas signals. the table below shows configuration of the transmit signaling and data link control [2:0] bits of the transmit signaling and data link select register (tsdlsr). if the transmit signaling and data link select [2:0] bits of the transmit signaling and data link select register are set to 1xx, the data link interface becomes source of the timeslot 16 octet. 2.5.4 how to configure XRT86L34 to transmit data link information through d or e channels the XRT86L34 can configure any one or ones of the thirty-two e1 channels to be d or e channels except for channel number 0. d channel is used primarily for data link applications. e channel is used primarily for signal- ing for circuit switching with multiple access configurations. the transmit conditioning select [3:0] bits of the transmit channel control register (tccr) of each channel determine whether that particular channel is configured as d or e channel. these bits also determine what type of data or signaling conditioning is applied to each channel. if the transmit conditioning select [3:0] bits of the transmit channel control register of a particular timeslot are set to 1111, that timeslot is configured as a d or e timeslot. n ote : timeslot 0 can never be configured as d or e timeslot. 2.5.5 transmit bos (bit oriented signaling) processor the transmit bos processor handles transmission of bos messages through the e1 data link channel. it de- termines how many repetitions a certain bos message will be transmitted. it also inserts bos idle flag se- quence and abort sequence to be transmitted on the data link channel. please see section ? for descrip- tions of bos message format and how to transmit bos message. 2.5.6 transmit mos (message oriented signaling) or lapd controller transmit signaling and data link select register (tsdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 2-0 transmit signaling and data link select r/w 000 - timeslot 16 octet is taken directly from the transmit serial input interface through the txser_n pin. 001 - timeslot 16 octet is taken directly from the transmit overhead input inter- face through the txoh_n pin or the transmit signaling control register of timeslot 16. 010 - timeslot 16 octet is taken directly from the transmit serial input interface through the txser_n pin. 011 - timeslot 16 octet is taken directly from the transmit overhead input inter- face through the txoh_n pin or the transmit signaling control register of timeslot 16. 1xx - timeslot 16 octet is taken from the data link interface. transmit channel control register (tccr) (address = 0xn300h - 0xn31fh) b it n umber b it n ame b it t ype b it d escription 3-0 transmit condition- ing select r/w 1111 - this channel is configured as d or e timeslot.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 184 the transmit lapd controller implements the message-oriented protocol based on itu recommendation q.921 link access procedures on the d-channel (lapd) type of protocol. it provides the following functions: ? zero stuffing ? t1/e1 transmitter interface ? transmit message buffer access ? frame check sequence generation ? idle flag insertion ? abort sequence generation two 96-byte buffers in shared memory are allocated for lapd transmitter to reduce the frequency of micropro- cessor interrupts and alleviate the response time requirement for microprocessor to handle each interrupt. there are no restrictions on the length of the message. however the 96-byte buffer is deep enough to hold one entire lapd path or test signal identification message. please see section ? for descriptions of mos message format and how to configure the lapd controller to transmit mos message.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 185 2.6 e1 r eceive hdlc c ontroller b lock 2.6.1 description of the e1 receive hdlc controller block XRT86L34 detects and extracts data link information from incoming e1 frames. the data link information in e1 framing format mode can be extracted to: ? e1 receive overhead output interface block ? e1 receive hdlc controller ? e1 receive serial output interface the extracted data link information is routed to the e1 receive overhead output interface and the e1 receive serial output interface no matter whether the e1 receive hdlc controller module is activated or not. each of the framers within the XRT86L34 device contains 3 e1 receive high-level data link controller (hdlc) blocks. the function of these blocks is to establish a serial data link channel in e1 mode through the following: ? the national bits (sa4 through sa8) of timeslot 0 of non-fas frame ? timeslot 16 octet when the framer is in common channel signaling mode ? d or e signaling timeslot channel we will discuss how to configure XRT86L34 to transmit data link information through each of these data link channels in later sections. the e1 transmit hdlc controller block contains two major functional modules associated with e1 framing for- mats. they are the lapd controller and the bit-oriented signaling processor. there are two 96-byte receive message buffer in shared memory for each of the four framers to receive data link information. when one message buffer is filled up, the e1 receive hdlc controller automatically switches to the next message buffer to store data link messages. these two message buffers ping-pong among each other for data link message storage. the message type bit of the data link status register (dlsr) determines which one of the three messages is received and processed by the receive hdlc controller block. the table below shows configuration of the message type bit of the data link status register (dlsr). 2.6.2 how to configure XRT86L34 to receive data link information through the national bits (sa4 through sa8) as mentioned in previous section, the national bits (sa4 through sa8) of timeslot 0 of non-fas frame can be used to receive data link information in e1 mode. the XRT86L34 allows the user to decide on the following: ? whether the national bits will be used to carry the data link information bits. ? how many of the national bits will be used to carry the data link information bits. ? which of these national bits will be used to carry the data link information bits. the receive signaling and data link control [2:0] bits of the receive signaling and data link select register (rsdlsr) determines if the national bits will be used to carry data link information. the table below shows data link status register (dlsr) (address = 0xnb06h) b it n umber b it n ame b it t ype b it d escription 7 message type rur / wc 0 - the receive hdlc controller receives and processes bit-oriented signaling (bos) message. 1 - the receive hdlc controller receives and processes lapd protocol or mes- sage-oriented signaling (mos) message.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 186 configuration of the receive signaling and data link control [2:0] bits of the receive signaling and data link select register (rsdlsr). if the receive signaling and data link select [2:0] bits of the receive signaling and data link select register are set to 000 or 001, the data link interface becomes destination of the sa4 through sa8 national bits. the receive sa data link select bits of the receive signaling and data link select register (rsdlsr) deter- mine which ones of the national bits are configured as data link bits in e1 framing format mode. depending upon the configuration of the receive signaling and data link select register, either of the following cases may exists: ? none of the national bits are used to transport the data link information bits (that is, data link channel of XRT86L34 is inactive). ? any combination of between 1 and all 5 of the national bits can be selected to transport the data link infor- mation bits. the table below shows configuration of the receive sa data link select bits of the receive signaling and da- ta link select register (rsdlsr). 2.6.3 how to configure XRT86L34 to receive data link information through timeslot 16 octet in e1 mode, timeslot 16 octet can be configured to receive the following: ? channel associated signaling (cas) bits a, b, c and d ? common channel signaling (ccs) bits the common channel signaling (ccs) messages are actually data link information applicable to all thirty-two timeslots of an e1 frame, thus the name common channel signaling. the receive signaling and data link control [2:0] bits of the receive signaling and data link select register (rsdlsr) determine if timeslot octet receive signaling and data link select register (rsdlsr) (address = 0xn10ch) b it n umber b it n ame b it t ype b it d escription 2-0 receive signaling and data link select r/w 000 - the data link interface is destination of the sa4 through sa8 nation bits. 001 - the data link interface is destination of the sa4 through sa8 nation bits. 010 - the sa4 through sa8 nation bits are forced to 1. 011 - the sa4 through sa8 nation bits are forced to 1. 1xx - the sa4 through sa8 nation bits are forced to 1. receive signaling and data link select register (rsdlsr) (address = 0xn10ch) b it n umber b it n ame b it t ype b it d escription 7 receive sa8 data link select r/w 0 - destination of the sa8 nation bit is not the data link interface. 1 - destination of the sa8 national bit is the data link interface. 6 receive sa7 data link select r/w 0 - destination of the sa7 nation bit is not the data link interface. 1 - destination of the sa7 national bit is the data link interface. 5 receive sa6 data link select r/w 0 - destination of the sa6 nation bit is not the data link interface. 1 - destination of the sa6 national bit is the data link interface. 4 receive sa5 data link select r/w 0 - destination of the sa5 nation bit is not the data link interface. 1 - destination of the sa5 national bit is the data link interface. 3 receive sa4 data link select r/w 0 - destination of the sa4 nation bit is not the data link interface. 1 - destination of the sa4 national bit is the data link interface.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 187 will be used to carry data link information or cas signals. the table below shows configuration of the receive signaling and data link control [2:0] bits of the receive signaling and data link select register (rsdlsr). if the receive signaling and data link select [2:0] bits of the receive signaling and data link select register are set to 1xx, the data link interface becomes destination of the timeslot 16 octet. 2.6.4 how to configure XRT86L34 to receive data link information through d or e channels the XRT86L34 can configure any one or ones of the thirty-two e1 channels to be d or e channels except for channel number 0. d channel is used primarily for data link applications. e channel is used primarily for signal- ing for circuit switching with multiple access configurations. the receive conditioning select [3:0] bits of the receive channel control register (rccr) of each channel determine whether that particular channel is configured as d or e channel. these bits also determine what type of data or signaling conditioning is applied to each channel. if the receive conditioning select [3:0] bits of the receive channel control register of a particular timeslot are set to 1111, that timeslot is configured as a d or e timeslot. n ote : timeslot 0 can never be configured as d or e timeslot. 2.6.5 receive bos (bit oriented signaling) processor the receive bos processor handles receiving and processing of bos messages through the e1 data link channel. it generates receive end of transfer (rxeot) interrupt each time a bos message is received and stores the bos message into the receive message buffer. please see section ? for how to configure the bos processor block to receive bos message. 2.6.6 receive lapd controller the receive lapd controller implements the message-oriented protocol based on itu recommendation q.921 link access procedures on the d-channel (lapd) type of protocol. it provides the following functions: ? zero deletion ? pattern recognition for idle flag detection ? pattern recognition for abort sequence detection ? frame check sequence verification receive signaling and data link select register (rsdlsr) (address = 0xn10ch) b it n umber b it n ame b it t ype b it d escription 2-0 receive signaling and data link select r/w 000 - timeslot 16 octet is extracted directly to the receive serial output interface through the rxser_n pin. 001 - timeslot 16 octet is extracted directly to the receive overhead output inter- face through the rxoh_n pin or the receive signaling control register of timeslot 16. 010 - timeslot 16 octet is extracted directly to the receive serial output interface through the rxser_n pin. 011 - timeslot 16 octet is extracted directly to the receive overhead output inter- face through the rxoh_n pin or the receive signaling control register of timeslot 16. 1xx - timeslot 16 octet is extracted to the data link interface. receive channel control register (rccr) (address = 0xn360h - 0xn37fh) b it n umber b it n ame b it t ype b it d escription 3-0 receive condition- ing select r/w 1111 - this channel is configured as d or e timeslot.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 188 ? t1 receiver interface ? receive data link message buffer access two 96-byte buffers in shared memory are allocated for receive lapd controller to reduce the frequency of mi- croprocessor interrupts and alleviate the response time requirement for microprocessor to handle each inter- rupt. there are no restrictions on the length of the message received. however, the 96-byte buffer is deep enough to hold one entire lapd path or test signal identification message.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 189 3.0 overhead interface block the XRT86L34 has the ability to extract or insert ds1 data link information from or into the following: ? facility data link (fdl) bits in esf framing format mode ? signaling framing (fs) bits in slc?96 and n framing format mode ? remote signaling (r) bits in t1dm framing format mode the source and destination of these inserted and extracted data link bits would be from either the internal hdlc controller or the external device accessible through ds1 overhead interface block. the operation of the transmit overhead input interface block and the receive overhead output interface block will be dis- cussed separately. 3.1 ds1 t ransmit o verhead i nput i nterface b lock 3.1.1 description of the ds1 transmit overhead input interface block the ds1 transmit overhead input interface block will allow an external device to be the provider of the facility data link (fdl) bits in esf framing format mode, signaling framing (fs) bits in the slc96 and n framing for- mat mode and remote signaling (r) bit in t1dm framing format mode. this interface provides interface sig- nals and required interface timing to shift in proper data link information at proper time. the transmit overhead input interface for a given framer consists of two signals. ? txohclk_n: the transmit overhead input interface clock output signal ? txoh_n: the transmit overhead input interface input signal. the transmit overhead input interface clock output pin (txohclk_n) generates a rising clock edge for each data link bit position according to configuration of the framer. the data link equipment interfaced to the trans- mit overhead input interface block should update the data link bits on the txoh_n line upon detection of the rising edge of txohclk_n. the transmit overhead input interface block will sample and latch the data link bits on the txoh_n line on the falling edge of txohclk_n. the data link bits will be included and transmitted via the outgoing ds1 frames. the figure below shows block diagram of the ds1 transmit overhead input interface of XRT86L34. 3.1.2 configure the ds1 transmit overhead input interface module as source of the facility data link (fdl) bits in esf framing format mode the fdl bits in esf framing format mode can be inserted from: ? ds1 transmit overhead input interface block ? ds1 transmit hdlc controller ? ds1 transmit serial input interface. f igure 10. b lock d iagram of the ds1 t ransmit o verhead i nput i nterface of the XRT86L34 transmit overhead input interface txoh_n txohclk_n to transmit framer block
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 190 the transmit data link source select bits of the transmit data link select register (tdlsr) controls the in- sertion of data link bits into the fdl bits in esf framing format mode. the table below shows configuration of the transmit data link source select bits of the transmit data link select register (tdlsr). if the transmit data link source select bits of the transmit data link select register are set to 10, the trans- mit overhead input interface block becomes input source of the fdl bits. the XRT86L34 allows the user to select bandwidth of the facility data link channel in esf framing format mode. the fdl can be either a 4khz or 2khz data link channel. the transmit data link bandwidth select bits of the transmit data link select register (tdlsr) determine the bandwidth of fdl channel in esf framing format mode. the table below shows configuration of the transmit data link bandwidth select bits of the transmit data link select register (tdlsr).) figure 11 below shows the timing diagram of the input and output signals associated with the ds1 transmit overhead input interface module in esf framing format mode. transmit data link select register (tdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 1-0 transmit data link source select r/w 00 - the facility data link bits are inserted into the framer through either the lapd controller or the slca96 buffer. 01 - the facility data link bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. 10 - the facility data link bits are inserted into the framer through the transmit overhead input interface via the txoh_n pins. 11 - the facility data link bits are forced to one by the framer. transmit data link select register (tdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 5-4 transmit data link bandwidth select r/w 00 - the facility data link is a 4khz channel. all available fdl bits (first bit of every other frame) are used as data link bits. 01 - the facility data link is a 2khz channel. only the odd fdl bits (first bit of frame 1, 5, 9) are used as data link bits. 10 - the facility data link is a 2khz channel. only the even fdl bits (first bit of frame 3, 7, 11) are used as data link bits.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 191 3.1.3 configure the ds1 transmit overhead input interface module as source of the signaling fram- ing (fs) bits in n or slc?96 framing format mode the fs bits in slc?96 and n framing format mode can be inserted from: ? ds1 transmit overhead input interface block ? ds1 transmit hdlc controller ? ds1 transmit serial input interface. the transmit data link source select bits of the transmit data link select register (tdlsr) controls the in- sertion of data link bits into the fs bits in n or slc?96 framing format mode. the table below shows configura- tion of the transmit data link source select bits of the transmit data link select register (tdlsr). if the transmit data link source select bits of the transmit data link select register are set to 10, the trans- mit overhead input interface block becomes input source of the fs bits. f igure 11. ds1 t ransmit o verhead i nput i nterface t iming in esf f raming f ormat mode transmit data link select register (tdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 1-0 transmit data link source select r/w 00 - the signaling framing bits are inserted into the framer through either the lapd controller or the slca96 buffer. 01 - the signaling framing bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. 10 - the signaling framing bits are inserted into the framer through the transmit overhead input interface via the txoh_n pins. 11 - the signaling framing bits are forced to one by the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 192 figure 12 below shows the timing diagram of the input and output signals associated with the ds1 transmit overhead input interface module in n or slc?96 framing format mode. 3.1.4 configure the ds1 transmit overhead input interface module as source of the remote signal- ing (r) bits in t1dm framing format mode the r bits in t1dm framing format mode can be inserted from: ? ds1 transmit overhead input interface block ? ds1 transmit hdlc controller ? ds1 transmit serial input interface. the transmit data link source select bits of the transmit data link select register (tdlsr) controls the in- sertion of data link bits into the r bits in t1dm framing format mode. the table below shows configuration of the transmit data link source select bits of the transmit data link select register (tdlsr). if the transmit data link source select bits of the transmit data link select register are set to 10, the trans- mit overhead input interface block becomes input source of the r bits. since r bit presents in timeslot 24 of every t1dm frame, therefore, bandwidth of t1dm data link channel is 8khz. figure 13 below shows the timing diagram of the input and output signals associated with the ds1 transmit overhead input interface module in t1dm framing format mode. 3.2 ds1 r eceive o verhead o utput i nterface b lock f igure 12. ds1 t ransmit o verhead i nput t iming in n or slc ?96 f raming f ormat m ode transmit data link select register (tdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 1-0 transmit data link source select r/w 00 - the remote signaling bits are inserted into the framer through either the lapd controller or the slca96 buffer. 01 - the remote signaling bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. 10 - the remote signaling bits are inserted into the framer through the transmit overhead input interface via the txoh_n pins. 11 - the remote signaling bits are forced to one by the framer. f igure 13. ds1 t ransmit o verhead i nput i nterface module in t1dm f raming f ormat mode
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 193 3.2.1 description of the ds1 receive overhead output interface block the ds1 receive overhead output interface block allows an external device to be the consumer of the facili- ty data link (fdl) bits in esf framing format mode, signaling framing (fs) bits in the slc96 and n framing format mode and remote signaling (r) bit in t1dm framing format mode this interface provides interface sig- nals and required interface timing to shift out proper data link information at proper time. the receive overhead output interface for a given framer consists of two signals. ? rxohclk_n: the receive overhead output interface clock output signal ? rxoh_n: the receive overhead output interface output signal. the receive overhead output interface clock output pin (rxohclk_n) generates a rising clock edge for each data link bit position according to configuration of the framer. the data link bits extracted from the incom- ing t1 frames are outputted from the receive overhead output interface output pin (rxoh_n) at the rising edge of rxohclk_n. the data link equipment should sample and latch the data link bits at the falling edge of rxohclk_n. the figure below shows block diagram of the receive overhead output interface of XRT86L34. 3.2.2 configure the ds1 receive overhead output interface module as destination of the facility data link (fdl) bits in esf framing format mode the fdl bits in esf framing format mode can be extracted to: ? ds1 receive overhead output interface block ? ds1 receive hdlc controller ? ds1 receive serial output interface. the receive data link source select bits of the receive data link select register (rdlsr) controls the ex- traction of fdl bits in esf framing format mode. the table below shows configuration of the receive data link source select bits of the receive data link select register (rdlsr). f igure 14. b lock d iagram of the ds1 r eceive o verhead o utput i nterface of XRT86L34 receive data link select register (tdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 1-0 receive data link destination select r/w 00 - the extracted facility data link bits are stored in either the lapd controller or the slca96 buffer. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 01 - the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 10 - the extracted facility data link bits are outputted from the framer through the receive overhead output interface via the rxoh_n pins. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 11 - the facility data link bits are forced to one by the framer. receive overhead output interface rxoh_n rxohclk_n from receive framer block
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 194 if the receive data link source select bits of the receive data link select register are set to 10, the receive overhead output interface block becomes output source of the fdl bits. the XRT86L34 allows the user to select bandwidth of the facility data link channel in esf framing format mode. the fdl can be either a 4khz or 2khz data link channel. the receive data link bandwidth select bits of the receive data link select register (rdlsr) determine the bandwidth of fdl channel in esf framing format mode. the table below shows configuration of the receive data link bandwidth select bits of the receive data link select register (tdlsr). figure 15 below shows the timing diagram of the output and output signals associated with the ds1 receive overhead output interface module in esf framing format mode. 3.2.3 configure the ds1 receive overhead output interface module as destination of the signaling framing (fs) bits in n or slc?96 framing format mode the fs bits in slc?96 and n framing format mode can be extracted to: ? ds1 receive overhead output interface block ? ds1 receive hdlc controller ? ds1 receive serial output interface. receive data link select register (tdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 5-4 receive data link bandwidth select r/w 00 - the facility data link is a 4khz channel. all available fdl bits (first bit of every other frame) are used as data link bits. 01 - the facility data link is a 2khz channel. only the odd fdl bits (first bit of frame 1, 5, 9) are used as data link bits. 10 - the facility data link is a 2khz channel. only the even fdl bits (first bit of frame 3, 7, 11) are used as data link bits. f igure 15. ds1 r eceive o verhead o utput i nterface module in esf framing format mode rxohclk (2khz,even) rxoh (2khz,even) rxoh (4khz) rxohclk (2khz,odd) rxoh (2khz,odd) frame # rxsync rxohclk (4khz) 12 6 45 789 10 11 12 13 14 15 16 17 18 19 20
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 195 the receive data link source select bits of the receive data link select register (rdlsr) controls the des- tination of fs bits in n or slc?96 framing format mode. the table below shows configuration of the receive data link source select bits of the receive data link select register (rdlsr). if the receive data link source select bits of the receive data link select register are set to 10, the receive overhead output interface block outputs fs bits extracted from the incoming t1 data stream. figure 16 below shows the timing diagram of the output signals associated with the ds1 receive overhead output interface module in n or slc?96 framing format mode. 3.2.4 configure the ds1 receive overhead output interface module as destination of the remote signaling (r) bits in t1dm framing format mode the r bits in t1dm framing format mode can be extracted to: ? ds1 receive overhead output interface block ? ds1 receive hdlc controller ? ds1 receive serial output interface. receive data link select register (tdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 1-0 receive data link source select r/w 00 - the extracted facility data link bits are stored in either the lapd controller or the slca96 buffer. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 01 - the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 10 - the extracted facility data link bits are outputted from the framer through the receive overhead output interface via the rxoh_n pins. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 11 - the facility data link bits are forced to one by the framer. f igure 16. ds1 r eceive o verhead o utput i nterface t iming in n or slc?96 f raming f ormat mode
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 196 the receive data link source select bits of the receive data link select register (rdlsr) controls the des- tination of r bits in t1dm framing format mode. the table below shows configuration of the receive data link source select bits of the receive data link select register (rdlsr). if the receive data link source select bits of the receive data link select register are set to 10, the receive overhead output interface block outputs the r bits extracted from the incoming t1 data stream. since r bit presents in timeslot 24 of every t1dm frame, therefore, bandwidth of t1dm data link channel is 8khz. figure 17 below shows the timing diagram of the output signals associated with the ds1 receive overhead output interface module in t1dm framing format mode. 3.3 e1 o verhead i nterface b lock the XRT86L34 has the ability to extract or insert e1 data link information from or into the e1 national bit se- quence. the source and destination of these inserted and extracted data link bits would be from either the in- ternal hdlc controller or the external device accessible through e1 overhead interface block. the operation of the transmit overhead input interface block and the receive overhead output interface block will be dis- cussed separately. 3.4 e1 t ransmit o verhead i nput i nterface b lock 3.4.1 description of the e1 transmit overhead input interface block the e1 transmit overhead input interface block will allow an external device to be the provider of the e1 na- tional bit sequence. this interface provides interface signals and required interface timing to shift in proper da- ta link information at proper time. receive data link select register (rdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 1-0 receive data link source select r/w 00 - the extracted facility data link bits are stored in either the lapd controller or the slc ? 96 buffer. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 01 - the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 10 - the extracted facility data link bits are outputted from the framer through the receive overhead output interface via the rxoh_n pins. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 11 - the facility data link bits are forced to one by the framer. f igure 17. ds1 r eceive o verhead o utput i nterface t iming in t1dm f raming f ormat mode
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 197 the transmit overhead input interface for a given framer consists of two signals. ? txohclk_n: the transmit overhead input interface clock output signal ? txoh_n: the transmit overhead input interface input signal. the transmit overhead input interface clock output pin (txohclk_n) generates a rising clock edge for each national bit that is configured to carry data link information according to setting of the framer. the data link equipment interfaced to the transmit overhead input interface should update the data link bits on the txoh_n line upon detection of the rising edge of txohclk_n. the transmit overhead input interface block will sample and latch the data link bits on the txoh_n line on the falling edge of txohclk_n. the data link bits will be in- cluded in and transmitted via the outgoing e1 frames. the figure below shows block diagram of the ds1 transmit overhead input interface of XRT86L34. 3.4.2 configure the e1 transmit overhead input interface module as source of the national bit sequence in e1 framing format mode the national bit sequence in e1 framing format mode can be inserted from: ? e1 transmit overhead input interface block ? e1 transmit hdlc controller ? e1 transmit serial input interface the purpose of the transmit overhead input interface is to permit data link equipment direct access to the sa4 through sa8 national bits that are to be transported via the outbound frames. the transmit data link source select [1:0] bits, within the synchronization mux register (smr) determine source of the sa4 through sa8 national bits to be inserted into the outgoing e1 frames. the table below shows configuration of the transmit data link source select [1:0] bits of the synchronization mux register (smr). if the transmit data link source select bits of the transmit data link select register are set to 10, the trans- mit overhead input interface block becomes input source of the fdl bits. the XRT86L34 allows the user to decide on the following: ? how many of the national bits will be used to carry the data link information bits f igure 18. b lock d iagram of the e1 t ransmit o verhead i nput i nterface of XRT86L34 synchronization mux register (smr) (address = 0xn109h) b it n umber b it n ame b it t ype b it d escription 3-2 transmit data link source select [1:0] r/w 00 - the sa4 through sa8 national bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. 01 - the sa4 through sa8 national bits are inserted into the framer through the transmit lapd controller. 10 - the sa4 through sa8 national bits are inserted into the framer through the transmit overhead input interface via the txoh_n pins. 11 - the sa4 through sa8 national bits are inserted into the framer through the transmit serial data input interface via the txser_n pins. transmit overhead input interface txoh_n txohclk_n to transmit framer block
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 198 ? which of these national bits will be used to carry the data link information bits. the transmit sa data link select bits of the transmit signaling and data link select register (tsdlsr) de- termine which ones of the national bits are configured as data link bits in e1 framing format mode. depending upon the configuration of the transmit signaling and data link select register, either of the following cases may exists: ? none of the national bits are used to transport the data link information bits (that is, data link channel of XRT86L34 is inactive). ? any combination of between 1 and all 5 of the national bits can be selected to transport the data link infor- mation bits. the table below shows configuration of the transmit sa data link select bits of the transmit signaling and da- ta link select register (tsdlsr). for every sa bit that is selected to carry data link information, the transmit overhead input interface will sup- ply a clock pulse, via the txohclk_n output pin, such that: ? the data link equipment interfaced to the transmit overhead input interface should update the data on the txoh_n line upon detection of the rising edge of txohclk_n. ? the transmit overhead input interface will sample and latch the data on the txoh_n line on the falling edge of txohclk_n. transmit signaling and data link select register (tsdlsr) (address = 0xn10ah) b it n umber b it n ame b it t ype b it d escription 7 transmit sa8 data link select r/w 0 - source of the sa8 nation bit is not from the data link interface. 1 - source the sa8 national bit from the data link interface. 6 transmit sa7 data link select r/w 0 - source of the sa7 nation bit is not from the data link interface. 1 - source the sa7 national bit from the data link interface. 5 transmit sa6 data link select r/w 0 - source of the sa6 nation bit is not from the data link interface. 1 - source the sa6 national bit from the data link interface. 4 transmit sa5 data link select r/w 0 - source of the sa5 nation bit is not from the data link interface. 1 - source the sa5 national bit from the data link interface. 3 transmit sa4 data link select r/w 0 - source of the sa4 nation bit is not from the data link interface. 1 - source the sa4 national bit from the data link interface.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 199 figure 19 below shows the timing diagram of the input and output signals associated with the e1 transmit overhead input interface module in e1 framing format mode. 3.5 e1 r eceive o verhead i nterface 3.5.1 description of the e1 receive overhead output interface block the e1 receive overhead output interface block will allow an external device to be the consumer of the e1 national bit sequence. this interface provides interface signals and required interface timing to shift out proper data link information at proper time. the receive overhead output interface for a given framer consists of two signals. ? rxohclk_n: the receive overhead output interface clock output signal ? rxoh_n: the receive overhead output interface output signal. the receive overhead output interface clock output pin (rxohclk_n) generates a rising clock edge for each national bit that is configured to carry data link information according to setting of the framer. the data link bits extracted from the incoming e1 frames are outputted from the receive overhead output interface output pin (rxoh_n) before the rising edge of rxohclk_n. the data link equipment should sample and latch the data link bits at the rising edge of rxohclk_n. the figure below shows block diagram of the receive overhead output interface of XRT86L34. f igure 19. e1 t ransmit o verhead i nput i nterface t iming f igure 20. b lock d iagram of the e1 r eceive o verhead o utput i nterface of XRT86L34 receive overhead output interface rxoh_n rxohclk_n from receive framer block
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 200 3.5.2 configure the e1 receive overhead output interface module as source of the national bit sequence in e1 framing format mode the national bit sequence in e1 framing format mode can be extracted and directed to: ? e1 receive overhead output interface block ? e1 receive hdlc controller ? e1 receive serial output interface the purpose of the receive overhead output interface is to permit data link equipment to have direct access to the sa4 through sa8 national bits that are extracted from the incoming e1 frames. independent of the avail- ability of the e1 receive hdlc controller module, the XRT86L34 always output the received national bits through the receive overhead output interface block. the XRT86L34 allows the user to decide on the following: ? how many of the national bits is used to carry the data link information bits ? which of these national bits is used to carry the data link information bits. the receive sa data link select bits of the receive signaling and data link select register (tsdlsr) deter- mine which ones of the national bits are configured as data link bits in e1 framing format mode. depending upon the configuration of the receive signaling and data link select register, either of the following cases may exists: ? none of the received national bits are used to transport the data link information bits (that is, data link channel of XRT86L34 is inactive). ? any combination of between 1 and all 5 of the received national bits are used to transport the data link information bits. the table below shows configuration of the receive sa data link select bits of the receive signaling and da- ta link select register (rsdlsr). for every received sa bit that is determined to carry data link information, the receive overhead output inter- face will supply a clock pulse, via the rxohclk_n output pin, such that: ? the receive overhead output interface should update the data on the rxoh_n line before the rising edge of rxohclk_n. ? the external data link equipment interfaced to the receive overhead output interface will sample and latch the data on the rxoh_n line on the rising edge of rxohclk_n. receive signaling and data link select register (rsdlsr) (address = 0xn10ch) b it n umber b it n ame b it t ype b it d escription 7 receive sa8 data link select r/w 0 - the received sa8 nation bit is not extracted to the data link interface. 1 - the received sa8 nation bit is extracted to the data link interface. 6 receive sa7 data link select r/w 0 - the received sa7 nation bit is not extracted to the data link interface. 1 - the received sa7 nation bit is extracted to the data link interface. 5 receive sa6 data link select r/w 0 - the received sa6 nation bit is not extracted to the data link interface. 1 - the received sa6 nation bit is extracted to the data link interface. 4 receive sa5 data link select r/w 0 - the received sa5 nation bit is not extracted to the data link interface. 1 - the received sa5 nation bit is extracted to the data link interface. 3 receive sa4 data link select r/w 0 - the received sa4 nation bit is not extracted to the data link interface. 1 - the received sa4 nation bit is extracted to the data link interface.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 201 figure 21 below shows the timing diagram of the output signals associated with the e1 receive overhead out- put interface module in e1 framing format mode. f igure 21. e1 r eceive o verhead o utput i nterface t iming
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 202
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 203 4.0 the e1 transmit section 4.1 t he e1 t ransmit p ayload d ata i nput i nterface b lock 4.1.1 description of the transmit payload data input interface block each of the four framers within the XRT86L34 device includes a transmit payload data input interface block. the function of this block is to provide an interface to the local terminal equipment (for example, a central of- fice or switching equipment) that has data to send to a "far end" terminal over a ds1 or e1 transport medium. the payload data input interface module (also known as the back-plane interface module) supports payload data to be taken from or presented to the system. in ds1 mode, supported data rates are 1.544mbit/s, mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 12.352mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. in e1 mode, supported data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the transmit payload data input interface block supplies or accepts the following signals to the local terminal equipment circuitry: ? transmit serial data input (txser_n) ? transmit serial clock (txserclk_n) ? transmit single-frame synchronization signal (txsync_n) ? transmit multi-frame synchronization signal (txmsync_n) ? transmit time-slot indicator clock (txtsclk_n) ? transmit time-slot indication bits (txtsb[4:0]_n) the transmit serial data is an input pin carrying payload, signaling and sometimes data link data supplied by the local terminal equipment to the XRT86L34 device. the transmit serial clock is an input or output signal used by the transmit payload data input interface block to latch in incoming serial data from the local terminal equipment. the transmit clock inversion bit of the transmit interface control register (ticr) determines at which edge of the transmit serial clock would data transition on the transmit serial data pin occur. the table below shows configurations of the transmit clock inversion bit of the transmit interface control reg- ister (ticr). throughout the discussion of this datasheet, we assume that serial data transition happens on rising edge of the transmit serial clock unless stated otherwise. the transmit single-frame synchronization signal is either input or output. when configure as input, it indi- cates beginning of an e1 frame. when configure as output, it indicates end of an e1 frame. the transmit multi-frame synchronization signal is either input or output. when configure as input, it indicates beginning of an e1 multi-frame. when configure as output, it indicates end of an e1 multi-frame. the transmit input clock signal is multiplexed into the transmit multi-frame synchronization pin (txmsync_n) of XRT86L34 device. when the framer is running at high-speed back-plane interface mode, the transmit input clock functions as the timing source for the high-speed back-plane interface. by connecting these signals with the local terminal equipment, the transmit payload data input interface ac- cepts payload data from the terminal equipment and routes it to the transmit framer module inside the de- vice. 4.1.2 brief discussion of the transmit payload data input interface block operating at xrt84v24 compatible 2.048mbit/s mode transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 3 transmit clock inversion r/w 0 - serial data transition happens on rising edge of the transmit serial clock. 1 - serial data transition happens on falling edge of the transmit serial clock.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 204 if the framer is operating in normal 2.048mbit/s back-plane interface mode for e1, timing source of the transmit section can be one of the three clocks: ? transmit serial input clock ? oscclk driven divided clock ? recovered receive line clock the transmit timing source select [1:0] bits of the clock select register (csr) determine which clock is used as the timing source. the following table shows configurations of the transmit timing source select [1:0] bits of the clock select register. the transmit serial clock (txserclk_n), transmit single-frame synchronization signal (txsync_n) and trans- mit multi-frame synchronization signal (txmsync_n) can be either inputs or outputs depend on the timing source of the transmit section of the framer. with the oscclk driven divided clock or the recovered receive line clock being the timing source of the transmit section, the transmit serial clock (txserclk_n), transmit single-frame synchronization signal (txsync_n) and transmit multi-frame synchronization signal (txmsync_n) are all outputs. with the timing source of the transmit section being the transmit serial input clock, the transmit serial clock (txserclk_n), transmit single-frame synchronization signal (txsync_n) and transmit multi-frame synchroni- zation signal (txmsync_n) are all inputs. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 1-0 transmit timing source select r/w transmit timing source select: these two read/write bit-fields permit the user to select the timing source of trans- mit section of the framer. when the transmit back-plane interface is operating at a clock rate of 2.048mhz for e1, these two read/write bit-fields also determine the direction of single frame syn- chronization pulse (txsync), multi-frame synchronization pulse (txmsync) and trans- mit serial clock input (txserclk). when the framer is operating at other back-plane mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all inputs. 00 - the recovered receive line clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 2.048mhz back-plane interface mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all outputs. upon losing of the recovered receiver line clock, the oscclk driven divided clock is automati- cally chosen to be the timing source of the transmit section of the framer. 01 - the transmit serial clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 2.048mhz back-plane interface mode, the sin- gle frame synchronization pulse (txsync), multi-frame synchronization pulse (txm- sync) and transmit serial clock input (txserclk) are all inputs. 10 - the oscclk driven divided clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 2.048mhz back-plane interface mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all outputs. upon losing of the recovered receiver line clock, the oscclk driven divided clock is automati- cally chosen to be the timing source of the transmit section of the framer. 11 - the recovered receive line clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 2.048mhz back-plane interface mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all outputs. upon losing of the recovered receiver line clock, the oscclk driven divided clock is automati- cally chosen to be the timing source of the transmit section of the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 205 the following table illustrates the input and output nature of these signals for different transmit timing sources. the transmit time-slot indication bits (txtsb[4:0]_n) are multiplexed i/o pins. the functionality of these pins is governed by the value of transmit fractional e1 input enable bit of the transmit interface control register (ticr). the following table illustrates the configurations of the transmit fractional e1 input enable bit. when configured to operate in normal condition (that is, when the transmit fractional e1 input enable bit is equal to zero), these bits reflect the five-bit binary value of the time slot number (0-31) being accepted and processed by the transmit payload data input interface block of the framer. txtsb[4] represents the msb of the binary value and txtsb[0] represents the lsb. when the transmit fractional e1 input enable bit is equal to one, the txtsb[0]_n bit becomes the transmit fractional e1 input signal (txfrtd_n). this input pin carries fractional e1 input data to be inserted into the outbound e1 data stream. the fraction e1 input interface allows certain time-slots of outbound e1 data stream to have a different source other than the local terminal equipment. function of the fractional e1 input signal will be discussed in details in later sections. when the transmit fractional e1 input enable bit is equal to one, the txtsb[1]_n bit becomes the transmit signaling data input signal (txsig_n). these input pins can be used to insert robbed-bit signaling data into the outbound e1 frame. function of the transmit signaling data input signal will be discussed in details in later sections. when the transmit fractional e1 input enable bit is equal to one, the txtsb[2]_n bit serially outputs all five-bit binary values of the time slot number (0-31) being accepted and processed by the transmit payload data in- put interface block of the framer. msb of the binary value is presented first and the lsb is presented last. t ransmit t iming s ource t x s er c lk _ n t x s ync _ n t x ms ync _ n terminal equipment driven txserclk input input input oscclk driven divided clock output output output recovered receive line clock output output output transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 4 transmit fractional e1 input enable r/w 0 - the transmit time-slot indication bits (txtsb[4:0] are outputting five-bit binary values of time-slot number (0-31) being accepted and processed by the transmit pay- load data input interface block of the framer. the transmit time-slot indicator clock signal (txtsclk_n) is a 256khz clock that pulses high for one e1 bit period whenever the transmit payload data input interface block is accepting the lsb of each of the twenty-four time slots. 1 - the txtsb[0]_n bit becomes the transmit fractional e1 input signal (txfrtd_n) which carries fractional e1 payload data into the framer. the txtsb[1]_n bit becomes the transmit signaling data input signal (txsig_n) which is used to insert robbed-bit signaling data into the outbound e1 frame. the txtsb[2]_n bit serially outputs all five-bit binary values of the time slot number (0-31) being accepted and processed by the transmit payload data input interface block of the framer. the txtsb[3]_n bit becomes the transmit overhead synchronization pulse (txohsync_n) which is used to output an overhead synchronization pulse that indi- cates the first bit of each e1multi-frame. the txtsclk_n will output gaped fractional e1 clock that can be used by terminal equipment to clock out fractional e1 payload data at rising edge of the clock. or, the txtsclk_n pin will be a clock enable signal to transmit fractional e1 input signal (txfrtd_n) when the un-gaped transmit serail input clock (txserclk_n) is used to clock in fractional e1 payload data into the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 206 when the transmit fractional e1 input enable bit is equal to one, the txtsb[3]_n bit becomes the transmit overhead synchronization pulse (txohsync_n). these pins can be used to output an overhead synchroniza- tion pulse that indicates the first bit of each e1multi-frame. function of the transmit overhead synchronization output signal will be discussed in details in later sections. the txtsb[4]_n bit is not multiplexed. the table below shows functionality of the txtsb[3:0] bits when the transmit fractional e1 input bit is set to different values. the transmit time-slot indicator clock signal (txtsclk_n) is a multi-function output pin. when configured to operate in normal condition (that is, when the transmit fractional e1 input enable bit is equal to zero), the txtsclk_n is a 256khz clock that pulses high for one e1 bit period whenever the transmit payload data in- put interface block is accepting the lsb of each of the twenty-four time slots. the local terminal equipment should use this clock signal to sample the txtsb[0] through txtsb[4] bits and identify the time-slot being pro- cessed via the transmit section of the framer. when the transmit fractional e1 input enable bit is equal to one, the txtsclk_n will output gaped fractional e1 clock at time-slots where fractional e1 input data is present. this clock can be used by terminal equip- ment to clock out fractional e1 payload data at rising edge of the clock. the framer will then input fractional e1 payload data using falling edge of the clock. otherwise, this pin can be configured as a clock enable signal to transmit fractional e1 input signal (txfrtd_n) if the framer is set accordingly. in this way, fractional e1 payload data is clocked into the framer using un-gaped transmit serail input clock (txserclk_n). a detailed discussion of the fractional e1 payload data input interface can be found in later sections. both the transmit time-slot indicator clock (txtsclk_n) and the transmit time-slot indication bits (txts- bb[4:0]_n) are output signals in normal 2.048mbit/s back-plane mode regardless of the timing source of the transmit section of framer. a detailed discussion of how to connect the transmit payload data input interface block to the local terminal equipment using different timing sources can be found in the later sections. 4.1.2.1 connect the transmit payload data input interface block to the local terminal equipment if transmit timing source = txserclk_n by setting the transmit timing source [1:0] bits of the clock select register to 01, the txserclk_n input signal is configured to be the timing source for the transmit section of the framer. the terminal equipment should supply an external free-running clock with frequency of 2.048mhz to the txserclk_n input pin. the transmit single-frame synchronization signal and the transmit multi-frame synchronization signal are inputs to the framer. the transmit single-frame synchronization signal should pulse high for one e1 bit period (488ns) at the first bit position of each e1 frame. by sampling the high pulse on the transmit single-frame synchronization sig- nal, the framer can position the beginning of an e1 frame. the transmit multi-frame synchronization signal should pulse high for one e1 bit period (488ns) at the first bit position of the first frame of an e1 multi-frame. by sampling the high pulse on the transmit multi-frame syn- chronization signal, the framer can position the beginning of an e1 super-frame. it is the responsibility of the terminal equipment to provide serial input data through the txser_n pin aligned with the transmit single-frame synchronization signal and the transmit multi-frame synchronization signal. t ransmit f ractional e1 i nput b it = 0 t ransmit f ractional e1 i nput b it = 1 txtsb[0] output txfrtd input txtsb[1] output txsig input txtsb[2] output txts output txtsb[3] output txohsync output
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 207 see figure 22 below for how to connect the transmit payload data input interface block to the local terminal equipment with the transmit serial clock being the timing source of transmit section. f igure 22. i nterfacing XRT86L34 to local terminal equipment with t x s er c lk _ n as t ransmit t iming s ource txserclk_0 txser_0 txmsync_0 txsync_0 txtsclk_0 txtsb[4:0]_0 txserclk_3 txser_3 txmsync_3 txsync_3 txtsclk_3 txtsb[4:0]_3 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 208 the following figure 23 shows waveforms of the signals (txserclk_n, txser_n, txsync_n, txtsclk_n and txtsb[4:0]_n) that connecting the transmit payload data input interface block to the local terminal equipment with the transmit serial clock being the timing source of transmit section. 4.1.2.2 connect the transmit payload data input interface block to the local terminal equipment if the transmit timing source = oscclk by setting the transmit timing source [1:0] bits of the clock select register (csr) to 10, the oscclk driven divided clock is configured to be the timing source for the transmit section of the framer. a free-running clock should apply to the oscclk input pin with frequencies of 16.384mhz, 32.768mhz and 65.536mhz depending on the setting of oscclk frequency select [1:0] bits of the clock select register (csr). the free-running oscclk is divided inside the XRT86L34 and routed to all four framers. this oscclk driven divided clock has to be 16.384mhz in frequency. when these bits are set to 00, the framer will internally divide the incoming oscclk by one. therefore, the external oscillator clock applied to the oscclk pin should be 16.384mhz. when these bits are set to 01, the framer will internally divide the incoming oscclk by two. therefore, the external oscillator clock applied to the oscclk pin should be 32.768mhz. when these bits are set to 10, the framer will internally divide the incoming oscclk by four. therefore, the external oscillator clock applied to the oscclk pin should be 65.536mhz. f igure 23. w aveforms of the signals that connect the t ransmit p ayload d ata i nput i nterface b lock to the local t erminal e quipment with the t ransmit s erial clock being the timing source of the t ransmit s ection c txserclk txserclk (inv) txser txsync(input) txsync(output) txchclk txchn[4:0] txchn[0]/txsig txtsb[4:0] txtsclk txchn[1]/txfrtd f c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data input data signaling input data timeslot #1 timeslot #15 timeslot #16 timeslot #32 timeslot 32 timeslot 1 timeslot 15 timeslot 16 a b d c a b d c a b d c a b d
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 209 the following table shows configurations of the oscclk frequency select [1:0] bits of the clock select reg- ister. the transmit serial clock signal pin (txserclk_n) is output from the framer. the framer outputs a 2.048mhz clock through this pin to the local terminal equipment. the transmit single-frame synchronization signal and the transmit multi-frame synchronization signal are also automatically configured to be output signals. the transmit single-frame synchronization signal should pulse high for one e1 bit period (488ns) at the last bit position of each e1 frame. by triggering on the high pulse on the transmit single-frame synchronization signal, the local terminal equipment can identify the end of an e1 frame and should start inserting payload da- ta of the next e1 frame to the framer. the transmit multi-frame synchronization signal should pulse high for one e1 bit period (488ns) at the last bit position of the last frame of an e1 multi-frame. by triggering on the high pulse on the transmit multi-frame synchronization signal, the local terminal equipment can identify the end of an e1 super-frame and should start inserting payload data of the next e1 multi-frame into the framer. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 3-2 oscclk frequency select r/w these two read/write bit-fields permit the user to select internal clock dividing logic of the framer depending on the frequency of incoming oscillator clock (oscclk). the frequency of internal clock used by the framer should be 16.384mhz. 00 - the framer will internally divide the incoming oscclk by one. therefore, the external oscillator clock applied to the oscclk pin should be 16.384mhz. 01 - the framer will internally divide the incoming oscclk by two. therefore, the external oscillator clock applied to the oscclk pin should be 32.768mhz. 10 - the framer will internally divide the incoming oscclk by four. therefore, the external oscillator clock applied to the oscclk pin should be 65.536mhz.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 210 see figure 24 for how to connect the transmit payload data input interface block to the local terminal equip- ment with the oscclk driven divided clock as the timing source of transmit section. f igure 24. i nterfacing XRT86L34 to local terminal equipment with oscclk driven divided clock as transmit timing source txserclk_0 txser_0 txmsync_0 txsync_0 txtsclk_0 txtsb[4:0]_0 txserclk_3 txser_3 txmsync_3 txsync_3 txtsclk_3 txtsb[4:0]_3 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 oscclk oscclk driven divided clock
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 211 the following figure 25 shows waveforms of the signals (txserclk_n, txser_n, txsync_n, txtsclk_n and txtsb[4:0]_n) that connecting the transmit payload data input interface block to the local terminal equipment with the oscclk driven divided clock as the timing source of transmit section. 4.1.2.3 connect the transmit payload data input interface block to the local terminal equipment for loop-timing applications if the transmit timing source [1:0] bits of the clock select register are set to 00 or 11, the recovered receive line clock is configured to be the timing source for the transmit section of the framer. this is also known as the loop-timing mode. if the clock loss detection enable bit of the clock select register is set to one, and if the recovered receive line clock from the liu is lost, the framer will automatically begin to use the oscclk driven divided clock as transmit timing source until the liu is able to regain clock recovery. f igure 25. w averforms of the signals connecting the t ransmit p ayload d ata i nput i nterface block to the local t erminal e quipment with the oscclk driven divided clock as the timing source of the t ransmit s ection c txserclk txserclk (inv) txser txsync(output) txchclk txchn[4:0] txchn[0]/txsig txchclk txchn[1]/txfrtd f c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data signaling input data timeslot #1 timeslot #15 timeslot #16 timeslot #32 timeslot 32 timeslot 1 timeslot 15 timeslot 16 a b d c a b d c a b d c a b d txchn[0]/txsig input data
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 212 the following table shows configuration of the clock loss detection enable bit of the clock select register (csr). the transmit serial clock signal pin (txserclk_n) is output from the framer. the XRT86L34 device routes the recovered receive line clock internally across the framer and output through the transmit serial clock signal pin to the local terminal equipment. the transmit single-frame synchronization signal and the transmit multi- frame synchronization signal are automatically configured to be output signals. the transmit single-frame synchronization signal should pulse high for one e1 bit period (488ns) at the last bit position of each e1 frame. by triggering on the high pulse on the transmit single-frame synchronization signal, the local terminal equipment can identify the end of an e1 frame and should start inserting payload da- ta of the next e1 frame to the framer. the transmit multi-frame synchronization signal should pulse high for one e1 bit period (488ns) at the last bit position of the last frame of an e1 multi-frame. by triggering on the high pulse on the transmit multi-frame synchronization signal, the local terminal equipment can identify the end of an e1 super-frame and should start inserting payload data of the next e1 multi-frame into the framer. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 4 clock loss detection enable r/w this read/write bit-field permits the user to enable the clock loss detection logic for the framer when the recovered receive line clock is used as transmit timing source of the framer. 0 - the framer disables the clock loss detection logic. 1 - the framer enables the clock loss detection logic. if the recovered receive line clock is used as transmit timing source of the framer, and if clock recovered from the liu is lost, the framer can detect loss of the recovered receive line clock. upon detecting of this occurrence, the framer will automatically begin to use the oscclk driven divided clock as transmit timing source until the liu is able to regain clock recovery. n ote : this bit-field is ignored if the txserclk or the oscclk driven divided clock is chosen to be the timing source of transmit section of the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 213 see figure 26 for how to connect the transmit payload data input interface block to the local terminal equip- ment with the recovered receive line clock being the timing source of transmit section. f igure 26. i nterfacing XRT86L34 to local terminal equipment with recovered receive line clock as transmit timing source txserclk_0 txser_0 txmsync_0 txsync_0 txtsclk_0 txtsb[4:0]_0 txserclk_3 txser_3 txmsync_3 txsync_3 txtsclk_3 txtsb[4:0]_3 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 rxlineclk_0 rxlineclk_7
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 214 the following figure 27 shows waveforms of the signals (txserclk_n, txser_n, txsync_n, txtsclk_n and txtsb[4:0]_n) that connecting the transmit payload data input interface block to the local terminal equipment with the recovered receive line clock being the timing source of transmit section. 4.2 t ransmit h igh -s peed b ack -p lane i nterface the high-speed back-plane interface supports payload data to be taken from or presented to the terminal equipment at different data rates. in e1 mode, supported high-speed data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the transmit multiplex enable bit and the transmit interface mode select [1:0] bits of the transmit interface control register (ticr) determine the transmit back-plane interface data rate. the following table shows configurations of the transmit multiplex enable bit and the transmit interface mode select [1:0] bits of the transmit interface control register (ticr). f igure 27. w averforms of the signals connecting the t ransmit p ayload d ata input interface block to the local t erminal e quipment with the r ecovered r eceive l ine c lock being the timing source of transmit section transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 2 transmit multiplex enable r/w 0 - the transmit back-plane interface block is configured to non-channel-multiplexed mode 1 - the transmit back-plane interface block is configured to channel-multiplexed mode 1-0 transmit interface mode select r/w when combined with the transmit multiplex enable bit, these bits determine the trans- mit back-plane interface data rate. c txserclk txserclk (inv) txser txsync(output) txchclk txchn[4:0] txchn[0]/txsig txchclk txchn[1]/txfrtd f c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data signaling input data timeslot #1 timeslot #15 timeslot #16 timeslot #32 timeslot 32 timeslot 1 timeslot 15 timeslot 16 a b d c a b d c a b d c a b d txchn[0]/txsig input data
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 215 the table below shows the combinations of transmit multiplex enable bit and transmit interface mode select [1:0] bits and the resulting transmit back-plane interface data rates. when the transmit multiplex enable bit is set to zero, the framer is configured in non-channel-multiplexed mode. the possible data rates are xrt84v24 compatible 2.048mbit/s, mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s. in non-channel-multiplexed mode, payload data of each channel are taken from the terminal equipment separately. each channel uses its own transmit serial clock, transmit serial data, transmit sin- gle-frame synchronization signal and transmit multi-frame synchronization signal as interface between the framer and the terminal equipment. section 1.1.2.1, 1.1.2.2 and 1.1.2.3 provide details on how to connect the transmit payload data interface block with the terminal equipment when the back-plane interface data rate is 1.544mbit/s. when the back-plane interface data rate is mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s, the transmit seri- al clock, transmit serial data, transmit single-frame synchronization signal and transmit multi-frame syn- chronization signal are all configured as inputs. the transmit serial clock is always an input clock with fre- quency of 2.048 mhz for all data rates. the txmsync_n signal is configured as the transmit input clock with frequencies of 2.048 mhz, 4.096 mhz and 8.192 mhz respectively. it serves as the primary clock source for the high-speed back-plane interface. the table below summaries the clock frequencies of txserclk_n and txinclk_n inputs when the framer is op- erating in non-multiplexed high-speed back-plane mode. when the transmit multiplex enable bit is set to one, the framer is configured in channel-multiplexed mode. the possible data rates are bit-multiplexed 16.384mbit/s, hmvip 16.384mbit/s and h.100 16.384mbit/s. in channel-multiplexed mode, every four channels share the transmit serial data and transmit single-frame synchronization signal of one channel as interface between the framer and the local terminal equipment. the txmsync_n signal of one channel is configured as the transmit input clock with frequencies of 16.384 mhz. it serves as the primary clock source for the high-speed back-plane interface. t ransmit m ultiplex e nable b it t ransmit i nterface m ode s elect b it 1 t ransmit i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate 0 0 0 xrt84v24 compatible 2.048mbit/s 0 0 1 mvip 2.048mbit/s 0 1 0 4.096mbit/s 0 1 1 8.192mbit/s 100 - 1 0 1 bit multiplexed 16.384mbit/s 1 1 0 hmvip 16.384mbit/s 1 1 1 h.100 16.384mbit/s transmit multiplex enable bit = 0 t ransmit i nterface m ode s elect b it 1 t ransmit i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate t x s er c lk t x ms ync /t x i n c lk 0 0 2.048mbit/s 2.048 mhz - 0 1 mvip 2.048mbit/s 2.048 mhz 2.048 mhz 1 0 4.096mbit/s 2.048 mhz 4.096 mhz 1 1 8.192mbit/s 2.048 mhz 8.192 mhz
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 216 payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. the transmit single-frame synchronization signal of channel 0 pulses high at the beginning of the frame with da- ta from channel 0-3 multiplexed together. the transmit single-frame synchronization signal of channel 4 pulses high at the beginning of the frame with data from channel 4-7 multiplexed together. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchro- nization pulse. additionally, each channel requires the local terminal equipment to provide a free-running 2.048 mhz clock into the transmit serial clock input. the table below summaries the clock frequencies of txserclk_n and txinclk_n inputs when the framer is op- erating in multiplexed high-speed back-plane mode. the transmit serial clock is always running at 1.544mhz for all the high-speed back-plane interface modes. it is automatically the timing source of the transmit section of the framer in high-speed back-plane interface mode. the transmit single-frame synchronization signal should pulse high or low for one bit period at the first bit position of each e1 frame. length of the bit period depends on data rate of the high-speed back-plane inter- face. the transmit synchronization pulse low bit of the transmit interface control register (ticr) determines whether the transmit single-frame synchronization signal is high active or low active. the table below shows configurations of the transmit synchronization pulse low bit of the transmit interface control register (ticr). throughout the discussion of this datasheet, we assume that the transmit single-frame synchronization signal pulses high unless stated otherwise. the txmsync_n signal, which is a multiplexed i/o pin, no longer functions as the transmit multi-frame syn- chronization signal. indeed, it becomes the transmit input clock signal (txinclk) of the high-speed back- plane interface of the framer. the local terminal equipment should provide a free-running clock with the same frequency as the high-speed back-plane interface to this input pin. the following sections discuss details of how to operate the framer in different back-plane interface speed mode and how to connect the transmit payload data input interface block to the local terminal equipment. 4.2.0.1 e1 transmit input interface - mvip 2.048 mhz transmit multiplex enable bit = 1 t ransmit i nterface m ode s elect b it 1 t ransmit i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate t x s er c lk t x ms ync /t x c lk 00--- 0 1 bit-multiplexed 16.384mbit/s 2.048 mhz 16.384 mhz 1 0 hmvip 16.384mbit/s 2.048 mhz 16.384 mhz 1 1 h.100 16.384mbit/s 2.048 mhz 16.384 mhz transmit interface control register (ticr)(address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 3transmit synchronization pulse low r/w 0 - the transmit single-frame synchronization signal will pulse high indicating the beginning of an e1 frame when the high-speed back-plane interface is running at a mode other than the xrt84v24 compatible 2.048mbit/s. 1 - the transmit single-frame synchronization signal will pulse low indicating the beginning of an e1 frame when the high-speed back-plane interface is running at a mode other than the xrt84v24 compatible 2.048mbit/s.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 217 when the transmit multiplex enable bit is set to zero and the transmit interface mode select [1:0] bits are set to 01, the transmit back-plane interface of framer is running at a data rate of 2.048mbit/s. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_n at 2.048mbit/s. the local terminal equipment supplies a free-running 2.048mhz clock to he transmit input clock pin of the framer. the local ter- minal equipment also provides synchronized payload data at rising edge of the clock. the transmit high- speed back-plane interface of the framer then latches incoming serial data at falling edge of the transmit input clock. the transmit single-frame synchronization input signal (txsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse on the transmit single-frame synchro- nization signal, the framer can position the beginning of an e1 frame. it is responsibility of the local terminal equipment to align the transmit single-frame synchronization signal with serial data stream going into the framer. see figure 28 below for how to interface the local terminal equipment with the transmit payload data input interface block of the framer in mvip 2.048mbit/s mode. f igure 28. i nterfacing XRT86L34 to local terminal equipment using mvip 2.048m bit / s data bus txserclk_0 txser_0 txinclk_0 (2.048mhz) txsync_0 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 txserclk_3 txser_3 txinclk_3 (2.048mhz) txsync_3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 218 the timing diagram of input signals to the framer when running at mvip 2.048mbit/s mode is shown in figure 29. 4.2.0.2 e1 transmit input interface - 4.096 mhz (this interface mode is the same as running at 2.048 mhz. the only difference is that the transmit input clock runs two times faster at 4.096 mhz) when the transmit multiplex enable bit is set to zero and the transmit interface mode select [1:0] bits are set to 10, the transmit back-plane interface of framer is running at a clock rate of 4.096mhz. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is still accepting data through txser_n at an e1 equivalent data rate of 2.048mbit/s. however, the local terminal equipment supplies a free-running 4.096mhz clock to the transmit input clock pin of the framer. the local terminal equipment provides synchronized payload data at every other rising edge of the transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at every other falling edge of the clock. transmit single-frame synchronization input signal (txsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse on the transmit single-frame synchro- nization signal, the framer can position the beginning of an e1 frame. it is responsibility of the local terminal equipment to align the transmit single-frame synchronization signal with serial data stream going into the framer. f igure 29. t iming diagram of input signals to the framer when running at mvip 2.048m bit / s txserclk txserclk (inv) txser txsync(input) txsync(input) mvip mode txchclk txchn[0]/txsig txsyncfrd=0 txchn[1]/txfrtd 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txchn[1]/txfrtd txchclk txsyncfrd=1 don't care
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 219 see figure 30 below for how to interface the local terminal equipment with the transmit payload data input interface block of the framer in 4.096mbit/s mode. the timing diagram of input signals to the framer when running at 4.096mbit/s mode is shown in figure 31. 4.2.0.3 e1 transmit input interface - 8.192 mhz (this interface mode is the same as running at 2.048 mhz. the only difference is that the transmit input clock runs four times faster at 8.192mhz) when the transmit multiplex enable bit is set to zero and the transmit interface mode select [1:0] bits are set to 11, the transmit back-plane interface of framer is running at a clock rate of 8.192mhz. the interface consists of the following pins: f igure 30. i nterfacing XRT86L34 to local terminal equipment using 4.096m bit / s data bus f igure 31. t iming diagram of input signals to the framer when running at 4.096m bit / s mode txserclk_0 txser_0 txinclk_0 (4.096mhz) txsync_0 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 txserclk_3 txser_3 txinclk_3 (4.096mhz) txsync_3 txserclk (2mhz) txserclk (inv) txser txsync(input) txchclk(inv) txchn[0]/txsig txchn[1]/txfrtd 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txserclk (4mhz) don't care don't care
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 220 ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is still accepting data through txser_n at an e1 equivalent data rate of 2.048mbit/s. however, the local terminal equipment supplies a free-running 8.192mhz clock to the transmit input clock pin of the framer. the local terminal equipment provides synchronized payload data at every other four rising edge of the transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at every other four falling edge of the clock. the transmit single-frame synchronization input signal (txsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse on the transmit single-frame synchro- nization signal, the framer can position the beginning of an e1 frame. it is responsibility of the local terminal equipment to align the transmit single-frame synchronization signal with serial data stream going into the framer. see figure 32 below for how to interface the local terminal equipment with the transmit payload data input interface block of the framer in 8.192mbit/s mode. f igure 32. i nterfacing XRT86L34 to local terminal equipment using 8.192m bit / s data bus txserclk_0 txser_0 txinclk_0 (8.192mhz) txsync_0 transmit payload data input interface chn 0 transmit payload data input interface chn 7 terminal equipment XRT86L34 txserclk_3 txser_3 txinclk_3 (8.192mhz) txsync_3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 221 the timing diagram of input signals to the framer when running at 8.192mbit/s mode is shown in figure 33. 4.2.0.4 e1 transmit input interface - bit-multiplexed 16.384mbit/s when the transmit multiplex enable bit is set to one and the transmit interface mode select [1:0] bits are set to 01, the transmit back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_0 or txser_4 pins at 16.384mbit/s. the lo- cal terminal equipment multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. free-running clocks of 16.384mhz is supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at rising edge of this transmit in- put clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the clock. the local terminal equipment maps four 2.048mbit/s e1 data streams into this 16.384mbit/s data stream as described below: 1. payload data of four channels are repeated and grouped together in a bit-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of channel 3 is sent last. f igure 33. t iming diagram of input signals to the framer when running at 8.192m bit / s mode txserclk (2mhz) txserclk (inv) txser txsync(input) txchclk(inv) txchn[0]/txsig txchn[1]/txfrtd 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txserclk (8mhz) don't care don't care
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 222 after the first bits of timeslot 0 of all four channels are sent, it comes the second bit of timeslot 0 of chan- nel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y 2. the local terminal equipment also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the terminal equipment is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth payload bit of a particular channels is followed by the signaling bit b of that channel; the seventh payload bit is followed by the signal- ing bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 second octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3 fifth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 sixth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 seventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 223 x y : the xth payload bit of channel y a y : the signaling bit a of channel y 3. after the first octet of all four channels are sent, the local terminal equipment start sending the second octets following the same rules of step 1 and 2. the transmit single-frame synchronization signal of channel 0 pulses high for one clock cycle at the first bit position of the data stream with data from channel 0-3 multiplexed together. the transmit single-frame syn- chronization signal of channel 4 pulses high for one clock cycle at the first bit position of the data stream with data from channel 4-7 multiplexed together. by sampling the high pulse on the transmit single-frame syn- chronization signal, the framer can position the beginning of the multiplexed e1 frame. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchroniza- tion pulse. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are de-multiplexed inside the XRT86L34 device and send to each individual channel. these data will be pro- cessed by each individual framer and send to liu interface. the local terminal equipment provides a free-run- ning 1.544mhz clock to the transmit serial input clock of each channel. the framer will use this clock to carry the processed payload and signaling data to the transmit section of the device. see figure 34 below for how to interface the local terminal equipment with the transmit payload data input interface block of the framer in bit-multiplexed 16.384mbit/s mode. eighth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 224 the input signal timing is shown in figure 35 below when the framer is running at bit-multiplexed 16.384mbit/s mode. 4.2.0.5 e1 transmit input interface - hmvip 16.384mbit/s when the transmit multiplex enable bit is set to one and the transmit interface mode select [1:0] bits are set to 10, the transmit back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) f igure 34. i nterfacing XRT86L34 to local terminal equipment using 16.384m bit / s data bus f igure 35. iming signal when the framer is running at b it -m ultiplexed 16.384m bit / s mode txser_0 txinclk_0 (16.384mhz) txsync_0 txserclk_0 (1.544mhz) transmit payload data input interface chn 0 terminal equipment XRT86L34 chn 1 chn 2 chn 3 txserclk_1 (1.544mhz) txserclk_2 (1.544mhz) txserclk_3 (1.544mhz) txserclk (16.384mhz) txserclk (inv) txser txsync(input) 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 56 cycles
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 225 ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_0 or txser_4 pins at 16.384mbit/s. the lo- cal terminal equipment multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. free-running clocks of 16.384mhz is supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at rising edge of this transmit in- put clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the clock. the local terminal equipment maps four 2.048mbit/s e1 data streams into this 16.384mbit/s data stream as described below: 1. payload data of four channels are repeated and grouped together in a byte-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the terminal equipment will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y 2. the local terminal equipment also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 third octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 fifth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 seventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 226 when the terminal equipment is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth payload bit of a particular channels is followed by the signaling bit b of that channel; the seventh payload bit is followed by the signal- ing bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 3. after the first octet of all four channels are sent, the local terminal equipment start sending the second octets following the same rules of step 1 and 2. the transmit single-frame synchronization signal should pulse high for four clock cycles (the last two bit po- sitions of the previous multiplexed frame and the first two bits of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the transmit single-frame synchronization signal of channel 0 puls- es high to identify the start of multiplexed data stream of channel 0-3. the transmit single-frame synchroni- zation signal of channel 4 pulses high to identify the start of multiplexed data stream of channel 4-7. by sam- pling the high pulse on the transmit single-frame synchronization signal, the framer can position the begin- ning of the multiplexed e1 frame. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchronization pulse. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are de-multiplexed inside the XRT86L34 device and send to each individual channel. these data will be pro- cessed by each individual framer and send to liu interface. the local terminal equipment provides a free-run- second octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0 fourth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 sixth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2 eighth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 227 ning 2.048mhz clock to the transmit serial input clock of each channel. the framer will use this clock to carry the processed payload and signaling data to the transmit section of the device. see figure 36 below for how to interface the local terminal equipment with the transmit payload data input interface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 37 below when the framer is running at hmvip 16.384mbit/s mode. f igure 36. i nterfacing XRT86L34 to local terminal equipment using 16.384m bit / s data bus f igure 37. t iming s ignal when the framer is running at hmvip 16.384m bit / s mode txser_0 txinclk_0 (16.384mhz) txsync_0 txserclk_0 (1.544mhz) transmit payload data input interface chn 0 terminal equipment XRT86L34 chn 1 chn 2 chn 3 txserclk_1 (1.544mhz) txserclk_2 (1.544mhz) txserclk_3 (1.544mhz) txserclk (16.384mhz) txserclk (inv) txser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 txsig txsync(input) hmvip, negative sync txsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number txsync(input) h.100, negative sync txsync(input) h.100, positive sync delayer h.100 txsync(input) h.100, negative sync txsync(input) h.100, positive sync
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 228 4.2.0.6 e1 transmit input interface - h.100 16.384mbit/s when the transmit multiplex enable bit is set to one and the transmit interface mode select [1:0] bits are set to 11, the transmit back-plane interface of framer is running at h.100 16.384mbit/s mode. (the hmvip mode and the h.100 mode are essential the same except for the high pulse position of the transmit single-frame synchronization signal) the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_0 or txser_4 pins at 16.384mbit/s. the lo- cal terminal equipment multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. free-running clocks of 16.384mhz is supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at rising edge of this transmit in- put clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the clock. the local terminal equipment maps four 2.048mbit/s e1 data streams into this 16.384mbit/s data stream as described below: 1. payload data of four channels are repeated and grouped together in a byte-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the terminal equipment will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 third octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 229 x y : the xth payload bit of channel y 2. the local terminal equipment also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the terminal equipment is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth payload bit of a particular channels is followed by the signaling bit b of that channel; the seventh payload bit is followed by the signal- ing bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. fifth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 seventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3 second octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0 fourth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 sixth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 230 x y : the xth payload bit of channel y a y : the signaling bit a of channel y 3. after the first octet of all four channels are sent, the local terminal equipment start sending the second octets following the same rules of step 1 and 2. the transmit single-frame synchronization signal should pulse high for two clock cycles (the last bit position of the previous multiplexed frame and the first bit position of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the transmit single-frame synchronization signal of channel 0 puls- es high to identify the start of multiplexed data stream of channel 0-3. the transmit single-frame synchroni- zation signal of channel 4 pulses high to identify the start of multiplexed data stream of channel 4-7. by sam- pling the high pulse on the transmit single-frame synchronization signal, the framer can position the begin- ning of the multiplexed e1 frame. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchronization pulse. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are de-multiplexed inside the XRT86L34 device and send to each individual channel. these data will be pro- cessed by each individual framer and send to liu interface. the local terminal equipment provides a free-run- ning 2.048mhz clock to the transmit serial input clock of each channel. the framer will use this clock to carry the processed payload and signaling data to the transmit section of the device. eighth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 231 see figure 38 below for how to interface the local terminal equipment with the transmit payload data input interface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 39 below when the framer is running at h.100 16.384mbit/s mode. 4.3 e1 t ransmit f ramer b lock f igure 38. i nterfacing XRT86L34 to local terminal equipment using 16.384m bit / s data bus f igure 39. t iming signal when the framer is running at h.100 16.384m bit / s mode txser_0 txinclk_0 (16.384mhz) txsync_0 txserclk_0 (1.544mhz) transmit payload data input interface chn 0 terminal equipment XRT86L34 chn 1 chn 2 chn 3 txserclk_1 (1.544mhz) txserclk_2 (1.544mhz) txserclk_3 (1.544mhz) txserclk (16.384mhz) txserclk (inv) txser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 txsig txsync(input) hmvip, negative sync txsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number txsync(input) h.100, negative sync txsync(input) h.100, positive sync delayer h.100 txsync(input) h.100, negative sync txsync(input) h.100, positive sync
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 232 4.3.1 how to configure XRT86L34 to operate in e1 mode the XRT86L34 octal t1/e1/j1 framer supports ds1, j1 or e1 framing modes. since j1 standard is very sim- ilar to ds1 standard with a few minor changes, the j1 framing mode is included as a sub-set of the ds1 fram- ing mode. all four framers within the XRT86L34 silicon can be individually configured to support ds1, j1 or e1 framing modes. n ote : if transmitting section of one framer is configured to support either one of the framing modes, the receiving section is automatically configured to support the same framing modes. the t1/e1 select bit of the clock select register (csr) controls which framing mode, that is, t1/j1 or e1, supported by the framer. the table below illustrates configurations of the t1/e1 select bit of the clock select register (csr). the purpose of the e1 transmit framer block is to embed and encode user payload data into frames and to route this e1 frame data to the transmit e1 liu interface block. please note that the XRT86L34 has four (4) in- dividual e1 transmit framer blocks. hence, the following description applies to all four of these individual transmit e1 framer blocks. the purpose of the e1 transmit framer block is: ? to encode user data, inputted from the terminal equipment into a standard framing format. ? to provide individual data control and signaling conditioning of each ds0 channel. ? to support the transmission of hdlc messages, from the local transmitting terminal, to the remote receiving terminal. ? to transmit indications that the local receive framer has received error frames from the remote terminal. ? to transmit alarm condition indicators to the remote terminal. the following sections discuss the functionalities of e1 transmit framer block in detail. we will also describe how to configure the XRT86L34 to transmit e1 frames according to system requirement of users. 4.3.2 how to configure the framer to transmit and receive data in e1 framing format the XRT86L34 octal t1/e1/j1 framer is designed to meet the requirement of itu-t recommendation g.704. the e1 framer supports the following: ? frame alignment signal (fas) ? crc-4 multi-frame the itu-t recommendation g.704 also specifies two forms of signaling that can be supported by the e1 transport medium: ? channel associated signaling (cas) ? common channel signaling (ccs) the XRT86L34 framer supports both cas, ccs signaling format together with clear channel without signal- ing. 4.3.3 how to configure the framer to choose fas searching algorithm the XRT86L34 framer can use two algorithms to search for fas pattern and thus declare fas alignment syn- chronization. the fas selection bit of the framing select register (fsr) allows the user to choose which one of the two algorithms for searching fas frame alignment. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 6 t1/e1 select r/w 0 - the XRT86L34 framer is running in e1 mode. 1 - the XRT86L34 framer is running in t1 mode.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 233 the table below shows configurations of the fas selection bit of the framing select register (fsr). 4.3.4 how to configure the framer to enable crc-4 multi-frame alignment and select the locking cri- teria the crc-4 selection [1:0] bits of the framing select register (fsr) enable the framer to search for crc-4 multi-frame alignment and select the criteria for locking the crc-4 multi-frame alignment. the table below shows configurations of the crc-4 selection [1:0] bit of the framing select register (fsr). 4.3.5 how to configure the framer to enable cas multi-frame alignment the XRT86L34 framer can use two algorithms to search for cas multi-frame alignment pattern. upon detect- ing of cas multi-frame alignment pattern, the framer will declare cas multi-frame alignment synchronization and generate the receive cas multi-frame synchronization pulse (rxcasmsync_n). the cas selection [1:0] bits of the framing select register (fsr) enable the framer to search for cas multi-frame alignment. framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 0 fas selection bit r/w this read/write bit field allows the user to determine which algorithm is used for searching fas frame alignment pattern. when an fas alignment pattern is found and locked, the XRT86L34 will generate receive synchronization (rxsync_n) pulse. 0 - algorithm 1 is selected for searching fas frame alignment pattern. 1 - algorithm 2 is selected for searching fas frame alignment pattern. framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 3-2 crc-4 selection bit r/w theses read/write bit fields allow the user to enable searching of crc-4 multi- frame alignment and determine what criteria are used for locking the crc-4 multi-frame alignment pattern. 00 - searching of crc-4 multi-frame alignment is disabled. the XRT86L34 framer will not search for crc-4 multi-frame alignment and thus will not declare crc-4 multi-frame synchronization. no receive crc-4 multi-frame synchroni- zation (rxcrcmsync_n) pulse will be generated by the framer. 01 - searching of crc-4 multi-frame alignment is enabled. the XRT86L34 will search for and declare crc-4 multi-frame synchronization if:at least one valid crc-4 multi-frame alignment signal is observed within 8 ms. 10 - searching of crc-4 multi-frame alignment is enabled. the XRT86L34 will search for and declare crc-4 multi-frame synchronization if:at least two valid crc-4 multi-frame alignment signals are observed within 8 ms. the time separat- ing two crc-4 multi-frame alignment signals is multiple of 2 ms. 11 - searching of crc-4 multi-frame alignment is enabled. the XRT86L34 will search for and declare crc-4 multi-frame synchronization if:at least three valid crc-4 multi-frame alignment signals are observed within 8 ms. the time separat- ing two crc-4 multi-frame alignment signals is multiple of 2 ms.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 234 the table below shows configurations of the cas selection [1:0] bit of the framing select register (fsr). 4.3.6 how to configure the framer to input the framing alignment bits from different sources in e1 mode, the frame alignment signal (fas) pattern of "0011011" contained in bit 2 to 8 of every other frame (called fas frame) are used to identify the frame boundaries. in addition, bit 2 of the non-fas frames is fixed to "1" to prevent simulation of the fas frames. in the non-fas frames, bit 1 is used to transmit the 6-bit crc-4 multi-frame alignment signal of "001011" and two e bits. the 6-bit crc-4 multi-frame alignment signal is used to identify the crc-4 multi-frame boundaries. the a bit at bit 3 of non-fas frame is used as remote yellow alarm indication. when the a bit is "0", it denotes undistributed operation of the framer. when the a bit is "1", it denotes yellow alarm condition. the framing alignment bits include the fas pattern, the crc-4 multi-frame alignment bits and the a bit. under default condition, the XRT86L34 can generate these framing alignment bits internally. at the same time, the users can generate the framing alignment bits externally and insert them into the framer through the transmit serial data input interface block via the txser_n pin. it is the user's responsibility to maintain the accuracy and integrity of the framing alignment bits. the user also has to make sure that the fram- ing alignment bits are inserted into the framer at right position and right timing. however, this option is only available when the XRT86L34 is configured to run at a normal back-plane rate of 2.048mbit/s in e1 mode. the framing bit source select bit of the synchronization mux register (smr) controls source of the framing alignment bit. the table below shows configurations of the framing bit source select bit of the synchroniza- tion mux register (smr). framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 5-4 cas selection bit r/w these read/write bit fields allow the user to enable searching of cas multi- frame alignment and determine which algorithm of the two are used for locking the cas multi-frame alignment pattern. 00 - searching of cas multi-frame alignment is disabled. the XRT86L34 framer will not search for cas multi-frame alignment and thus will not declare cas multi-frame synchronization. no receive cas multi-frame synchronization (rxcrcmsync_n) pulse will be generated by the framer. 01 - searching of cas multi-frame alignment is enabled. the XRT86L34 will search for and declare cas multi-frame synchronization using algorithm 1. 10 - searching of cas multi-frame alignment is enabled. the XRT86L34 will search for and declare cas multi-frame synchronization using algorithm 2 (g.732). 11 - searching of cas multi-frame alignment is disabled. the XRT86L34 framer will not search for cas multi-frame alignment and thus will not declare cas multi-frame synchronization. no receive cas multi-frame synchronization (rxcrcmsync_n) pulse will be generated by the framer. synchronization mux register (smr) (address = 0xn109h) b it n umber b it n ame b it t ype b it d escription 0 framing bit source r/w this read/write bit-field permits the user to determine where the framing alignment bits should be inserted. 0 - the framing alignment bits are generated and inserted by the framer internally. 1 - if the framer is operating in normal 2.048mbit/s mode, the framing alignment bits are passed through from the transmit serial data input interface block via the txser_n pin.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 235 4.3.7 how to configure the framer to input crc-4 bits from different sources each e1 crc-4 multi-frame is divided into two sub-multi-frames. each sub-multi-frame consists of 8 e1 frames. if the framer is configured to operate in crc-4 multi-frame format, bit 1 of the fas frames are used as cyclic redundancy check (crc-4) code of the last crc-4 sub- multi-frame. the crc-4 bits are an indicator of the link quality and could be monitored by the user to establish error performance report. the XRT86L34 can generate the crc-4 bits internally by calculating the crc check-sum of all the payload bits in each e1 sub-multi-frame. at the same time, the users can generate the crc-4 bits externally and insert them into the framer through the transmit serial data input interface block via the txser_n pin. it is the user's responsibility to correctly com- pute the crc-4 bits according to e1 algorithm. also, the user has to make sure that the crc-4 bits are insert- ed into the framer at right position and right timing. however, this option is only available when the XRT86L34 is configured to run at a normal back-plane rate of 2.048mbit/s. the crc-4 source select bit of the synchronization mux register (smr) controls from where to input crc-4 bits into the framer. the table below shows configurations of the crc-4 source select bit of the synchroniza- tion mux register (smr). 4.3.8 how to configure the framer to input e bits from different sources each e1 crc-4 multi-frame is divided into two sub-multi-frames. each sub-multi-frame consists of 8 e1 frames, 4 of them are fas frames and the other 4 are non-fas frames. of the second crc-4 sub-multi-frame, bit 1 of the last 2 non-fas frames is called e bit. the e bits are used to indicate that the previous received sub-multi-frame is error-ed. when a sub-multi-frame is received, the framer calculated the crc-4 bits of the received sub-multi-frame. the frame then compares the calculated crc-4 bits with the received crc-4 bits. if they are the same, the framer will set e bit to "1" and transmit it to the remote terminal. if the calculated crc-4 bits and the receive crc-4 bits are different, the framer will set e bit to "0" and transmit it out. the first e bit indicates error of the first crc-4 sub-multi-frame while the second e bit indicates error of the second crc-4 sub-multi-frame. the delay between the detection of an error-ed crc-4 sub-multi-frame and the setting of the corresponding e bit that represents the error state should not be more than one second. if the e bits are not used, they should be set to "1". n ote : the e bits will always be taken into account even if the sub-multi-frame which contains them is error-ed. under default condition, the XRT86L34 generate the e bits internally by calculating the crc check-sum of all the payload bits in each received e1 sub-multi-frame and compare them against the received crc-4 bits. at the same time, the users can force the e bits to either "0" or "1". source of the e bits can also be the internal hdlc controller such that the e bits can be used to transmit data link message. synchronization mux register (smr) (address = 0xn109h) b it n umber b it n ame b it t ype b it d escription 1 crc-4 source select r/w this read/write bit-field permits the user to determine where the crc-4 bits should be inserted. 0 - the crc-4 bits are generated and inserted by the framer internally. 1 - if the framer is operating in normal 2.048mbit/s mode, the crc-4 bits are gen- erated by external equipment and passed through from the transmit serial data input interface block via the txser_n pin.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 236 the e bit source select bit of the synchronization mux register (smr) controls from where to input e bits into the framer. the table below shows configurations of the e bit source select bit of the synchronization mux register (smr). 4.3.9 how to configure the framer to apply data and signaling conditioning to e1 payload data on a per-channel basis the XRT86L34 t1/j1/e1 octal framer provides individual control of each of the thirty two ds0 channels. the user can apply data and signaling conditioning to raw e1 payload data coming from the terminal equipment on a per-channel basis. the XRT86L34 framer can apply the following changes to raw e1 pcm data coming from the terminal equip- ment on a per-channel basis: ? all 8 bits of the input pcm data are inverted ? the even bits of the input pcm data are inverted ? the odd bits of the input pcm data are inverted ? the msb of the input pcm data is inverted ? all input pcm data except the msb are inverted configuration of the XRT86L34 framer to apply the above-mentioned changes to raw e1 pcm data are con- trolled by the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of each ds0 channel. the XRT86L34 framer can also replace the incoming raw e1 pcm data from the terminal equipment with pre- defined or user-defined codes. the XRT86L34 supports the following conditioning substitutions: ? busy code - an octet with hexadecimal value of 0x7f ? busy_ts code - an octet of pattern "111xxxxx" where "xxxxx" represents the timeslot number ? vacant code - an octet with hexadecimal value of 0xff ? a-law digital milliwatt code ? u-law digital milliwatt code ? idle code - an octet defined by the value stored in the user idle code register (ucr) ? moof code - mux-out-of-frame code with hexadecimal value of 0x1a ? prbs code - an octet generated by the pseudo-random bit sequence (prbs) generator block of the framer once again, configuration of the XRT86L34 framer to replace raw e1 pcm data with the above-mentioned coding schemes are controlled by the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of each ds0 channel. finally, the XRT86L34 framer can configure any one or ones of the thirty two ds0 channels to be d or e chan- nels. d channel is used primarily for data link applications. e channel is used primarily for signaling for circuit switching with multiple access configurations. synchronization mux register (smr) (address = 0xn109h) b it n umber b it n ame b it t ype b it d escription 7-6 e bit source select r/w these read/write bit-fields permits the user to determine where the e bits should be inserted and what the e bits should be. 00 - the e bits are generated and inserted by the framer internally. 01 - the e bits are forced to be "0" and are inserted by the framer internally. 10 - the e bits are forced to be "1" and are inserted by the framer internally. 11 - source of the e bits is hdlc controller of the framer. the e bits are used to carry data link messages.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 237 the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of each channel determine whether that particular channel is configured as d or e channel. the table below illustrates configurations of the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr). when the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of a particular ds0 channel are set to 0100, input e1 pcm data of this ds0 channel are replaced by the octet stored in user idle code register (ucr). the table below shows contents of the user idle code register. 4.3.10 how to configure the XRT86L34 framer to transmit signaling information each 256-bit e1 frame is divided into 32 octets or time slots numbered 0 to 31. each time slot is a 64kbits/s channel carrying voice or data information. the time slot 0 is used for frame and multi-frame synchronization, crc-4 error detection, yellow alarm transmission and data link transmission. the time slot 1 to time slot 15 and time slot 17 to time slot 31 are used to carry a pcm encoded voice band signal or data. the remaining 64kbits/s channel time slot 16 may be used for signaling. the XRT86L34 t1/j1/e1 octal framer supports the following signaling formats to interconnect to cept channelized service functions: transmit channel control register (tccr) (address = 0xn300h - 0xn31fh) b it n umber b it n ame b it t ype b it d escription 3-0 transmit conditioning select r/w 0000 - the input e1 pcm data of this ds0 channel is unchanged. 0001 - all 8 bits of the input e1 pcm data of this ds0 channel are inverted. 0010 - the even bits of the input e1 pcm data of this ds0 channel are inverted. 0011 - the odd bits of the input e1 pcm data of this ds0 channel are inverted. 0100 - the input e1 pcm data of this ds0 channel are replaced by the octet stored in user idle code register (ucr). 0101 - the input e1 pcm data of this ds0 channel are replaced by busy code (0x7f). 0110 - the input e1 pcm data of this ds0 channel are replaced by vacant code (0xff). 0111 - the input e1 pcm data of this ds0 channel are replaced by busy_ts code (111xxxxx). 1000 - the input e1 pcm data of this ds0 channel are replaced by mux-out-of- frame (moof) code with value 0x1a. 1001 - the input e1 pcm data of this ds0 channel are replaced by the a-law dig- ital milliwatt pattern. 1010 - the input e1 pcm data of this ds0 channel are replaced by the u-law dig- ital milliwatt pattern. 1011 - the msb bit of the input e1 pcm data of this ds0 channel is inverted. 1100 - all bits of the input e1 pcm data of this ds0 channel except msb bit are inverted. 1101 - the input e1 pcm data of this ds0 channel are replaced by prbs pattern created by the internal prbs generator of XRT86L34 framer. 1110 - the input e1 pcm data of this ds0 channel is unchanged. 1111 - this channel is configured as d or e timeslot. user idle code register (ucr) (address = 0xn320h - 0xn33fh) b it n umber b it n ame b it t ype b it d escription 7-0 user idle code r/w these read/write bit-fields permits the user store any value of idle code into the framer. when the transmit data conditioning select [3:0] bits of tccr register of a particular ds0 channel are set to 0100, the input e1 pcm data are replaced by contents of this register and sent to the transmit liu interface.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 238 ? common channel signaling (ccs) ? channel associated signaling (cas) ? primary rate isdn message oriented signaling (isdn-pri) the XRT86L34 t1/j1/e1 octal framer supports insertion of various types of signaling information into the timeslot 16 of an outgoing e1 frame. it also supports extraction and substitution of signaling information from the incoming e1 frame. the following section provides a brief overview of common channel signaling, chan- nel associated signaling in e1 mode. n ote : the time slot 16 can also be configured to carry pcm encoded voice or data if neither ccs nor cas signaling is used. the XRT86L34 framer allows the user to choose which one of the ccs, cas, isdn-pri message or pcm data to be carries on the time slot 16. 4.3.11 brief discussion of common channel signaling in e1 framing format as the name referred, common channel signaling is signaling information common to all thirty voice or data channels of an e1 trunk. the time slot 16 may be used to carry common channel signaling data of up to a rate of 64kbits/s. the national bits of time slot 0 may also be used for common channel signaling. since there are five national bits of time slot 0 per every two e1 frames, the total bandwidth of the national bits is 20kbits/s. the common channel signaling is essentially data link information that provides performance monitoring and transmission quality report. 4.3.12 brief discussion of channel associated signaling in e1 framing format signaling is required when dealing with voice and dial-up data services in e1 applications. traditionally, signal- ing is provided on a dial-up telephone line, across the talk-path. signaling is used to tell the receiver where the call or route is destined. the signal is sent through switches along the route to a distant end. common types of signals are: ? on hook ? off hook ? dial tone ? dialed digits ? ringing cycle ? busy tone a signal is consists of four bits namely a, b, c and d. these bits define the state of the call for a particular time slot. the time slot 16 octet of each e1 frame can carry cas signals for two e1 voice or data channels. there- fore, sixteen e1 frames are needed to carry cas signals for all 32 e1 channels. the sixteen e1 frames then forms a cas multi-frame. the time slot 16 of frame number 0 of an e1 cas multi-frame carries the pattern of "0000 xyxx". the time slot 16 of frame number 1 carries signals of channel 1 and channel 17. the time slot 16 of frame number 2 carries signals of channel 2 and channel 18, and so on. the following table shows the bit allocations of chan- nel associated signaling in e1 framing format. t ime slot 16 of f rame 0t ime slot 16 of f rame 1t ime slot 16 of f rame 2t ime slot 16 of f rame 3 0000 xyxx abcd of ch. 1 abcd of ch. 17 abcd of ch. 2 abcd of ch. 18 abcd of ch. 3 abcd of ch. 19 t ime slot 16 of f rame 4t ime slot 16 of f rame 5t ime slot 16 of f rame 6t ime slot 16 of f rame 7 abcd of ch. 4 abcd of ch. 20 abcd of ch. 5 abcd of ch. 21 abcd of ch. 6 abcd of ch. 22 abcd of ch. 7 abcd of ch. 23
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 239 the four zeros pattern is the multi-frame alignment signal that indicates the beginning of an e1 cas multi- frame. the XRT86L34 framer, upon detection of the four zeros pattern in the time slot 16, declares cas multi- frame synchronization and would pulse the receive cas multi-frame synchronization pulse (rxcasmsync_n) high for one clock period. the user, triggering on the receive cas multi-frame synchronization pulse, would thus identify the received cas multi-frame boundary. the x in xyxx pattern located in the time slot 16 of frame number 0 should be fixed to "1" and can be used to prevent mimicking of cas multi-frame alignment pattern. the y in xyxx pattern is used for alarm indication of time slot 16 to the remote terminal. if signals of time slot 16 is transmitted and received correctly, the y bit is set to "0". in an alarm condition, the y bit is set to "1". therefore, y bit is also known as cas multi-frame yellow alarm. 4.3.13 configure the framer to transmit channel associated signaling the XRT86L34 framer supports transmission of common channel signaling and channel associated signal- ing according to itu-t recommendation g.704. as discussed briefly before, channel associated signaling in- cludes the signaling bits, the cas multi-frame alignment pattern and the x and y bits. signaling bits can be inserted into the outgoing e1 frame through the following: ? signaling data is inserted from the transmit signaling control registers (tscr) of each timeslot. ? signaling data is inserted from txsig_n pin. ? signaling data is inserted from txoh-n pin. ? signaling data is embedded into the input pcm data coming from the terminal equipment. the cas multi-frame alignment pattern of four zeros can be inserted into the outgoing e1 frame by using the following method: ? cas multi-frame alignment pattern is inserted from thetransmit signaling control registers (tscr). ? cas multi-frame alignment pattern is inserted from txsig_n pin. ? cas multi-frame alignment pattern is inserted from txoh-n pin. ? cas multi-frame alignment pattern is embedded into the input pcm data coming from the terminal equip- ment. the cas multi-frame yellow alarm y bit and the x bits can be inserted into the outgoing e1 frame by using the following method: ? the x and y bits are inserted from the transmit signaling control register (tscr). ? the x and y bits are inserted from txsig_n pin. ? the x and y bits are inserted from txoh-n pin. ? the x and y bits are embedded into the input pcm data coming from the terminal equipment. t ime slot 16 of f rame 8t ime slot 16 of f rame 9t ime slot 16 of f rame 10 t ime slot 16 of f rame 11 abcd of ch. 8 abcd of ch. 24 abcd of ch. 9 abcd of ch. 25 abcd of ch. 10 abcd of ch. 26 abcd of ch. 11 abcd of ch. 27 t ime slot 16 of f rame 12 t ime slot 16 of f rame 13 t ime slot 16 of f rame 14 t ime slot 16 of f rame 15 abcd of ch. 12 abcd of ch. 28 abcd of ch. 13 abcd of ch. 29 abcd of ch. 14 abcd of ch. 30 abcd of ch. 15 abcd of ch. 31
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 240 ? the x bit is inserted from the transmit signaling control register (tscr) and y bit is generated by the XRT86L34 framer according to operating condition of the e1 link. 4.3.13.1 insert signaling bits from tscr register the four most significant bits of the transmit signaling control register (tscr) of each time slot can be used to store outgoing signaling data. the user can program these bits through microprocessor access. if the XRT86L34 framer is configure to insert signaling bits from tscr registers, the e1 transmit framer block will fill up the time slot 16 octet with the signaling bits stored inside the tscr registers. the insertion of signaling bit into pcm data is done on a per-channel basis. the most significant bit (bit 7) of tscr register is used to store signaling bit a. bit 6 is used to hold signaling bit b. bit 5 is used to hold signaling bit c. bit 4 is used to hold signaling bit d. the table below shows the four most significant bits of the transmit signaling control register. 4.3.13.2 insert signaling bits from txsig_n pin the XRT86L34 framer can be configure to insert signaling bits provided by external equipment through the txsig_n pins. this pin is a multiplexed i/o pin with two functions: ? txtsb[0]_n - transmit timeslot number bit [0] output pin ? txsig_n - transmit signaling input pin when the transmit fractional e1 bit of the transmit interface control register (ticr) is set to 0, this pin is configured as txtsb[0]_n pin, it outputs bit 0 of the timeslot number of the e1 pcm data that is transmitting. when the transmit fractional e1 bit of the transmit interface control register (ticr) is set to 1, this pin is configured as txsig_n pin, it acts as an input source for the signaling bits to be transmitted in the outbound e1 frames. figure 40 below is a timing diagram of the txsig_n input pin. please note that the signaling bit a of a certain channel coincides with bit 5 of the pcm data of that channel; signaling bit b coincides with bit 6 of the pcm data; signaling bit c coincides with bit 7 of the pcm data and signaling bit d coincides with bit 8 (lsb) of the pcm data. transmit signaling control register (tscr) (address = 0xn340h - 0xn35fh) b it n umber b it n ame b it t ype b it d escription 7 signaling bit a r/w this bit is used to store signaling bit a. 6 signaling bit b r/w this bit is used to store signaling bit b. 5 signaling bit c r/w this bit is used to store signaling bit c. 4 signaling bit d r/w this bit is used to store signaling bit d. f igure 40. t iming d iagram of the t x s ig _ n i nput
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 241 the table below shows configurations of the transmit fractional e1 bit of the transmit interface control regis- ter (ticr). 4.3.13.3 insert signaling bits from txoh_n pin the XRT86L34 framer can be configure to insert signaling bits provided by external equipment through the transmit overhead txoh_n input pins. the txoh_n pin can acts as an input source for the signaling bits to be transmitted in the outbound e1 frames. when this pin is chosen as the input source for the signaling bits, any data presents on this pin in time slot 16 would be taken into the framer directly. the time slot 16 octet of the outbound e1 frame will be replaced by da- ta inputted from this pin in time slot 16. please note that the signaling bit a of channel 1-15 coincides with bit 1 of the pcm data; signaling bit b chan- nel 1-15 coincides with bit 2 of the pcm data; signaling bit c channel 1-15 coincides with bit 3 of the pcm; signaling bit d channel 1-15 coincides with bit 4 of the pcm data. similarly, the signaling bit a of channel 17-31 coincides with bit 5 of the pcm data; signaling bit b channel 17-31 coincides with bit 6 of the pcm data; signaling bit c channel 17-31 coincides with bit 7 of the pcm; sig- naling bit d channel 17-31 coincides with bit 8 of the pcm data. 4.3.13.4 insert signaling data from txser_n pin depends on applications, the terminal equipment can embed signaling information into the e1 pcm data and then send the data to the XRT86L34 framer device. in this case, the user should configure the framer not to in- sert any signaling data. the input e1 pcm data will then be directed to the transmit liu interface without any modifications. 4.3.13.5 enable channel associated signaling and signaling data source control the transmit signaling control register (tscr) of each channel selects source of signaling data to be insert- ed into the outgoing e1 frame and enables channel associated signaling. as we mentioned before, the signal- ing data can be inserted from transmit signaling control registers (tscr) of each timeslot, from the txsig_n input pin, from the txoh_n input pin or from the txser_n input pin. the transmit signaling data source select [1:0] bits of the transmit signaling control register (tscr) determines from which sources the signaling data is inserted from. transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 4transmit fractional e1 r/w this read/write bit-field permits the user to determine which one of the two functions the multiplexed i/o pin of txtsb[0]_n/txsig_n is spotting. 0 - this pin is configured as txtsb[0]_n pin, it outputs bit 0 of the timeslot num- ber of the e1 pcm data that is transmitting. 1 - this pin is configured as txsig_n pin, it acts as an input source for the signal- ing bits to be transmitted in the outbound e1 frames
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 242 the table below shows configurations of the transmit signaling data source select [1:0] bits of the transmit signaling control register (tscr). 4.3.14 how to configure the XRT86L34 framer to generate and transmit alarms and error indica- tions to remote terminal the XRT86L34 t1/j1/e1 octal framer can be configured to monitor quality of received e1 frames. it can gen- erate error indications if the local receive framer has received error frames from the remote terminal. if corre- sponding interrupt is enabled, the local microprocessor operation is interrupted by these error conditions. upon microprocessor interruption, the user can intervene by looking into the error conditions. at the same time, the user can configure the XRT86L34 framer to transmit alarms and error indications to re- mote terminal. different alarms and error indications will be transmitted depending on the error condition. the section below gives a brief discussion of the error conditions and appropriate alarms that should be generated and transmitted by the XRT86L34 framer. 4.3.15 brief discussion of alarms and error conditions as defined in e1 specification, alarm conditions are created from defects. defects are momentary impairments present on the e1 trunk. if a defect is present for a sufficient amount of time (called the integration time), then the defect becomes an alarm. once an alarm is declared, the alarm is present until after the defect clears for a sufficient period of time. the time it takes to clear an alarm is called the de-integration time. alarms are used to detect and warn maintenance personnel of problems on the e1 trunk. there are three types of alarms: ? red alarm or service alarm indication (sai) signal ? blue alarm or alarm indication signal (ais) ? yellow alarm or remote alarm indication (rai) signal to explain the error conditions and generation of different alarms, let us create a simple e1 system model. in this model, an e1 signal is sourced from the central office (co) through a repeater to the customer premises transmit signaling control register (tscr) (address = 0xn340h - 0xn357h) b it n umber b it n ame b it t ype b it d escription 1-0 transmit signaling source select r/w 00 - none of the signaling data, the cas multi-frame alignment pattern, the x bit or the cas multi-frame yellow alarm bit y is inserted into the outgoing e1 pcm data by the framer. however, the user can embed the signaling data, the cas multi-frame alignment pattern, the x bit or the cas multi-frame yellow alarm bit y into e1 pcm data before routing the pcm data into the framer. 01 - the signaling data, the cas multi-frame alignment pattern, the x bit or the cas multi-frame yellow alarm bit y is inserted into the outgoing e1 pcm data from tscr register of each timeslot. 10 - if the XRT86L34 framer is operating in e1 2.048mbit/s mode and if the txfr2048 bit of the transmit interface control register (ticr) is set to zero: the signaling data, the cas multi-frame alignment pattern, the x bit or the cas multi-frame yellow alarm bit y is inserted into the outgoing e1 pcm data from the txoh_n input pin. if the XRT86L34 framer is operating in e1 2.048mbit/s mode and if the txfr2048 bit of the transmit interface control register (ticr) is set to one: the signaling data, the cas multi-frame alignment pattern, the x bit or the cas multi-frame yellow alarm bit y is inserted into the outgoing e1 pcm data from the txsig_n input pin. 11 - no signaling data or the cas multi-frame alignment pattern is inserted into the input e1 pcm data by the framer. however, the user can embed signaling data into e1 pcm data before routing the pcm data into the framer. the x bit is inserted into the outgoing e1 pcm data from tscr register. the cas multi-frame yellow alarm y bit is generated by the XRT86L34 framer depends on operating condition of the e1 link.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 243 equipment (cpe). at the same time, an e1 signal is routed from the cpe to the repeater and back to the cen- tral office. figure 41 below shows the simple e1 system model. when the e1 system runs normally, that is, when there is no loss of signal (los) or loss of frame (lof) de- tected in the line, no alarm will be generated. sometimes, intermittent outburst of electrical noises on the line might result in bipolar violation or bit errors in the incoming signals, but these errors in general will not trigger the equipment to generate alarms. they will, depending on the system requirements, trigger the framer to gen- erate interrupts that would cause the local microprocessor to create performance reports of the line. now, consider a case in which the e1 line from the co to the repeater is broken or interrupted, resulting in completely loss of incoming data or severely impaired signal quality. upon detection of loss of signal (los) or loss of frame (lof) condition, the repeater will generate an internal red alarm, also known as the service alarm indication. this alarm will normally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. when the repeater is in the red alarm state, it will transmit the yellow alarm to the co indicating the loss of an incoming signal or loss of frame synchronization. this yellow alarm informs the repeater that there is a f igure 41. s imple d iagram of e1 system model e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe simple e1 system model
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 244 problem further down the line and its transmission is not being received at the repeater. figure 42 below illus- trates the scenario in which the e1 connection from the co to the repeater is broken. the repeater will also transmit a blue alarm, also known as alarm indication signal (ais) to the cpe. blue alarm is an all ones pattern indicating that the equipment is functioning but unable to offer service due to fail- ures originated from remote side. it is sent such that the equipment downstream will not lose clock synchroni- f igure 42. g eneration of y ellow a larm by the r epeater upon detection of line failure e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the e1 line is broken repeater declares red alarm internally yellow alarm repeater generates yellow alarm to co
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 245 zation even though no meaningful data is received. figure 43 below illustrates this scenario in which the re- peater is sending an ais to the cpe upon detection of line failure from the co. now, the cpe uses the ais signal sent by the repeater to recover received clock and remain in synchroniza- tion with the system. upon detecting the incoming ais signal, the cpe will generate a yellow alarm automati- cally to the repeater to indicate the loss of incoming data. figure 44 below illustrates this scenario in which the repeater is sending an ais to the cpe and the cpe is sending a yellow alarm back to the repeater. f igure 43. g eneration of ais by the r epeater upon detection of line failure e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the e1 line is broken repeater declares red alarm internally yellow alarm repeater generates yellow alarm to co repeater generates ais to cpe ais
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 246 next, let us consider the scenario in which the signaling and data link channel (the time slot 16) of an e1 line between a far-end terminal (for example, the co) and a near-end terminal (for example, the repeater) is im- paired. in this case, the cas signaling data received by the repeater is corrupted. the repeater will then send an all ones pattern in time slot 16 (ais16 pattern) downstream to the cpe. the repeater will also generate a cas multi-frame yellow alarm upstream to the co to indicate the loss of cas multi-frame synchronization. f igure 44. g eneration of y ellow a larm by the cpe upon detection of ais originated by the r epeater e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the e1 line is broken repeater declares red alarm internally yellow alarm repeater generates yellow alarm to co repeater generates ais to cpe ais yellow alarm cpe detects ais and generates yellow alarm to repeater
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 247 figure 45 below illustrates this scenario in which the repeater is sending an "ais16" pattern to the cpe while sending a cas multi-frame yellow alarm to the co. f igure 45. g eneration of cas m ulti - frame y ellow a larm and ais16 by the r epeater e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the timeslot 16 of an e1 line is iimpaired repeater generates cas multi-frame yellow alarm to co repeater generates ais16 to cpe ais16 cas multi- frame yellow alarm
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 248 the cpe, upon detecting the incoming ais16 signal, will generate a cas multi-frame yellow alarm to the re- peater to indicate the loss of cas multi-frame synchronization. figure 46 below illustrates the cpe sending a cas multi-frame yellow alarm back to the repeater in summary, ais or blue alarm is sent by a piece of e1 equipment downstream indicating that the incoming signal from upstream is lost. yellow alarm is sent by a piece of e1 equipment upstream upon detection of loss of signal, loss of frame or when it is receiving ais. similarly, an "ais16" pattern is sent by a piece of e1 equipment downstream indicating that the incoming data link channel from upstream is damaged. the cas multi-frame yellow alarm is sent by a piece of e1 equipment upstream upon detection of loss of cas multi-frame synchronization or when it is receiving an "ais16" pat- tern. 4.3.16 how to configure the framer to transmit ais as we discussed in the previous section, alarm indication signal (ais) or blue alarm is transmitted by the in- termediate node to indicate that the equipment is still functioning but unable to offer services. it is an all ones (except for framing bits) pattern which can be used by the equipment further down the line to maintain clock re- covery and timing synchronization. the XRT86L34 framer can generate three types of ais when it is running in e1 format: ? framed ais ? unframed ais ? ais16 unframed ais is an all ones pattern. if unframed ais is sent, the equipment further down the line will be able to maintain timing synchronization and be able to recover clock from the received ais signal. however, due to the lack of framing bits, the equipment farther down the line will not be able to maintain frame synchronization and will declare loss of frame (lof). f igure 46. g eneration of cas m ulti - fram y ellow a larm by the cpe upon detection of ais16 pat - tern sent by the r epeater e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the timeslot 16 of an e1 line is iimpaired repeater generates cas multi-frame yellow alarm to co repeater generates ais16 to cpe ais16 cas multi- frame yellow alarm cpe detects ais16 and generates cas multi-frame yellow alarm to repeater cas multi- frame yellow alarm
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 249 on the other hand, the payload portion of a framed ais pattern is all ones. however, a framed ais pattern still has correct framing bits. therefore, the equipment further down the line can still maintain frame synchroniza- tion as well as timing synchronization. in this case, no lof or red alarm will be declared. "ais16" is an ais alarm that only supported in e1 framing format. it is an all ones pattern in time slot 16 of each e1 frame. as we mentioned before, time slot 16 is usually used for signaling and data link in e1, therefore, an "ais16" alarm is transmitted by the intermediate node to indicate that the data link channel is having a prob- lem. since all the other thirty one time slots are still transmitting normal data (that is, framing information and pcm data), therefore, the equipment further down the line can still maintain frame synchronization, timing syn- chronization as well as receiving pcm data. in this case, no lof or red alarm will be declared by the equip- ments further down the line. however, a cas multi-frame yellow alarm will be sent by the equipment further down the line to indicate the loss of cas multi-frame alignment. the transmit alarm indication signal select [1:0] bits of the alarm generation register (agr) enable the three types of ais transmission that are supported by the XRT86L34 framer. the table below shows configurations of the transmit alarm indication signal select [1:0] bits of the alarm generation register (agr). 4.3.17 how to configure the framer to generate red alarm upon detection of loss of signal (los) or loss of frame (lof) condition, the repeater will generate an inter- nal red alarm when enabled. this alarm will normally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. the loss of frame declaration enable bit of the alarm generation register (agr) enable the generation of red alarm. the table below shows configurations of the of frame declaration enable bit of the alarm genera- tion register (agr). 4.3.18 how to configure the framer to transmit yellow alarm the XRT86L34 framer supports transmission of both yellow alarm and cas multi-frame yellow alarm in e1 mode. alarm generation register (agr) (address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 3-2 transmit ais select r/w these read/write bit-fields allows the user to choose which one of the three ais pattern supported by the XRT86L34 framer will be transmitted. 00 - no ais alarm is generated. 01 - enable unframed ais alarm of all ones pattern. 11 - ais16 pattern is generated. only time slot 16 is carrying the all ones pattern. the other time slots still carry framing and pcm data. 11 - enable framed ais alarm of all ones pattern except for framing bits. alarm generation register (agr) (address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 6 loss of frame dec- laration enable r/w this read/write bit-field permits the framer to declare red alarm in case of loss of frame alignment (lof). when receiver module of the framer detects loss of frame alignment in the incoming data stream, it will generate a red alarm. the framer will also generate an rxlofs interrupt to notify the microprocessor that an lof condition is occurred. a yellow alarm is then returned to the remote transmitter to report that the local receiver detects lof. 0 - red alarm declaration is disabled. 1 - red alarm declaration is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 250 upon detection of loss of signal (los) or loss of frame (lof) condition, the receiver will transmit the yellow alarm back to the source indicating the loss of an incoming signal. this yellow alarm informs the source that there is a problem further down the line and its transmission is not being received at the destination. on the other hand, upon detection of loss of cas multi-frame alignment pattern, the receiver section of the XRT86L34 framer will transmit a cas multi-frame yellow alarm back to the source indicating the loss of cas multi-frame synchronization. the yellow alarm generation select [1:0] bits of the alarm generation register (agr) enable transmission of different types of yellow alarm that are supported by the XRT86L34 framer. 4.3.18.1 transmit yellow alarm the yellow alarm bits are located at bit 3 of time slot 0 of non-fas frames. a logic one of this bit denotes the yellow alarm and a logic zero of this bit denotes normal operation. the XRT86L34 supports transmission of yellow alarm automatically or manually. when the yellow alarm generation select [1:0] bits of the alarm generation register are set to 01, the yellow alarm bit is transmitted by echoing the received fas alignment pattern. if the correct fas alignment is re- ceived, the yellow alarm bit is set to zero. if the fas alignment pattern is missing or corrupted, the yellow alarm bit is set to one while loss of frame synchronization is declared. when the yellow alarm generation select [1:0] bits of the alarm generation register are set to 10, the yellow alarm bit is transmitted as zero. when the yellow alarm generation select [1:0] bits of the alarm generation register are set to 11, the yellow alarm bit is transmitted as one. 4.3.18.2 transmit cas multi-frame yellow alarm within the sixteen-frame cas multi-frame, the cas multi-frame yellow alarm bits are located at bit 6 of time slot 16 of frame number 0. a logic one of this bit denotes the cas multi-frame yellow alarm and a logic zero of this bit denotes normal operation. the XRT86L34 supports transmission of cas multi-frame yellow alarm au- tomatically or manually. when the cas multi-frame yellow alarm generation select [1:0] bits of the alarm generation register are set to 01, the cas multi-frame yellow alarm bit is transmitted by echoing the received cas multi-frame alignment pattern (the four zeros pattern). if the correct cas multi-frame alignment is received, the cas multi-frame yel- low alarm bit is set to zero. if the cas multi-frame alignment pattern is missing or corrupted, the cas multi- frame yellow alarm bit is set to one while loss of cas multi-frame synchronization is declared. when the cas multi-frame yellow alarm generation select [1:0] bits of the alarm generation register are set to 10, the cas multi-frame yellow alarm bit is transmitted as zero. when the cas multi-frame yellow alarm generation select [1:0] bits of the alarm generation register are set to 11, the cas multi-frame yellow alarm bit is transmitted as one.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 251 the table below shows configurations of the yellow alarm generation select [1:0] bits of the alarm generation register (agr). alarm generation register (agr) (address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 5-4 yellow alarm gen- eration select r/w these read/write bit-fields allows the user to choose how the XRT86L34 would generate yellow alarm and cas multi-frame yellow alarm. 00 - transmission of yellow alarm and cas multi-frame yellow alarm is dis- abled. 01 - the yellow alarm bit is transmitted by echoing the received fas alignment pattern. if the correct fas alignment is received, the yellow alarm bit is set to zero. if the fas alignment pattern is missing or corrupted, the yellow alarm bit is set to one. the cas multi-frame yellow alarm bit is transmitted by echoing the received cas multi-frame alignment pattern (the four zeros pattern). if the correct cas multi-frame alignment is received, the cas multi-frame yellow alarm bit is set to zero. if the cas multi-frame alignment pattern is missing or corrupted, the cas multi-frame yellow alarm bit is set to one. 10 - the yellow alarm and cas multi-frame yellow alarms are transmitted as zero. 11 - the yellow alarm and cas multi-frame yellow alarms are transmitted as one.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 252
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 253 5.0 the ds1 transmit section 5.1 t he ds1 t ransmit p ayload d ata i nput i nterface b lock 5.1.1 description of the transmit payload data input interface block each of the four framers within the XRT86L34 includes a transmit payload data input interface block. the func- tion of this block is to provide an interface to the local terminal equipment (for example, a central office or switching equipment) that has data to send to a far end terminal over a ds1 or e1 transport medium. the payload data input interface module (also known as the back-plane interface module) supports payload da- ta to be taken from or presented to the system. in ds1 mode, supported data rates are 1.544mbit/s, mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 12.352mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. in e1 mode, supported data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multi- plexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the transmit payload data input interface block supplies or accepts the following signals to the local terminal equipment circuitry: ? transmit serial data input (txser) ? transmit serial clock (txserclk) ? transmit single-frame synchronization signal (txsync) ? transmit multi-frame synchronization signal (txmsync) ? transmit time-slot indicator clock (txchclk) ? transmit time-slot indication bits (txchn[4:0]) the transmit serial data is an input pin carrying payload, signaling and sometimes data link data supplied by the local terminal equipment to the XRT86L34. the transmit serial clock is an input or output signal used by the transmit payload data input interface block to latch in incoming serial data from the local terminal equipment. the transmit clock inversion bit of the transmit interface control register (ticr) determines at which edge of the transmit serial clock data transition on txs- er. the table below shows configurations of the transmit clock inversion bit of the transmit interface control regis- ter (ticr). throughout the discussion of this datasheet, we assume that serial data transition happens on the rising edge of the transmit serial clock unless stated otherwise. the transmit single-frame synchronization signal (txsync) is either input or output. when configured as input, it indicates the beginning of a ds1 frame. when configured as output, it indicates the end of a ds1 frame. the transmit multi-frame synchronization signal is either input or output. when configured as input, it indicates the beginning of a ds1 multi-frame. when configured as output, it indicates the end of a ds1 multi-frame. the transmit input clock signal is multiplexed into the transmit multi-frame synchronization pin (txmsync_n) of XRT86L34. when the framer is running at high-speed back-plane interface mode, the transmit input clock func- tions as the timing source for the high-speed back-plane interface. by connecting these signals with the local terminal equipment, the transmit payload data input interface ac- cepts payload data from the terminal equipment and routes it to the transmit framer module inside the device. 5.1.2 brief discussion of the transmit payload data input interface block operating at 1.544mbit/s mode transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 3 transmit clock inversion r/w 0 - serial data transition happens on rising edge of the transmit serial clock. 1 - serial data transition happens on falling edge of the transmit serial clock.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 254 if the framer is operating in normal 1.544mbit/s back-plane interface mode for ds1, timing source of the transmit section can be one of the three clocks: ? transmit serial input clock ? oscclk driven divided clock ? recovered receive line clock the transmit timing source select [1:0] bits of the clock select register (csr) determine which clock is used as the timing source. the following table shows configurations of the transmit timing source select [1:0] bits of the clock select register. the transmit serial clock (txserclk_n), transmit single-frame synchronization signal (txsync_n) and transmit multi-frame synchronization signal (txmsync_n) can be either inputs or outputs depend on the timing source of the transmit section of the framer. with the oscclk driven divided clock or the recovered receive line clock being the timing source of the transmit section, the transmit serial clock (txserclk_n), transmit single-frame synchronization signal (txsync_n) and transmit multi-frame synchronization signal (txmsync_n) are all outputs. with the timing source of the transmit section being the transmit serial input clock, the transmit serial clock (txserclk_n), transmit single-frame synchronization signal (txsync_n) and transmit multi-frame synchroniza- tion signal (txmsync_n) are all inputs. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 1-0 transmit timing source select r/w these two read/write bit-fields permit the user to select the timing source of trans- mit section of the framer. when the transmit back-plane interface is operating at a clock rate of 1.544mhz for t1, these two read/write bit-fields also determine the direction of single frame syn- chronization pulse (txsync), multi-frame synchronization pulse (txmsync) and trans- mit serial clock input (txserclk). when the framer is operating at other back-plane mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all inputs. 00 - the recovered receive line clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 1.544mhz back-plane interface mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all outputs. upon losing of the recovered receiver line clock, the oscclk driven divided clock is automati- cally chosen to be the timing source of the transmit section of the framer. 01 - the transmit serial clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 1.544mhz back-plane interface mode, the sin- gle frame synchronization pulse (txsync), multi-frame synchronization pulse (txm- sync) and transmit serial clock input (txserclk) are all inputs. 10 - the oscclk driven divided clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 1.544mhz back-plane interface mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all outputs. upon losing of the recovered receiver line clock, the oscclk driven divided clock is automati- cally chosen to be the timing source of the transmit section of the framer. 11 - the recovered receive line clock is the timing source of transmit section of the framer. when operating at the non-multiplexed 1.544mhz back-plane interface mode, the single frame synchronization pulse (txsync), multi-frame synchronization pulse (txmsync) and transmit serial clock input (txserclk) are all outputs. upon losing of the recovered receiver line clock, the oscclk driven divided clock is automati- cally chosen to be the timing source of the transmit section of the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 255 the following table illustrates the input and output nature of these signals for different transmit timing sources. the transmit time-slot indication bits (txtsb[4:0]_n) are multiplexed i/o pins. the functionality of these pins is governed by the value of transmit fractional t1 input enable bit of the transmit interface control register (ticr). the following table illustrates the configurations of the transmit fractional ds1 input enable bit. when configured to operate in normal condition (that is, when the transmit fractional t1 input enable bit is equal to zero), these bits reflect the five-bit binary value of the time slot number (0 - 23) being accepted and processed by the transmit payload data input interface block of the framer. txtsb[4] represents the msb of the binary val- ue and txtsb[0] represents the lsb. when the transmit fractional t1 input enable bit is equal to one, the txtsb[0]_n bit becomes the transmit frac- tional t1 input signal (txfrtd_n). this input pin carries fractional t1 input data to be inserted into the outbound ds1 data stream. the fraction t1 input interface allows certain time-slots of outbound ds1 data stream to have a different source other than the local terminal equipment. function of the fractional t1 input signal will be dis- cussed in details in later sections. when the transmit fractional t1 input enable bit is equal to one, the txtsb[1]_n bit becomes the transmit sig- naling data input signal (txsig_n). these input pins can be used to insert robbed-bit signaling data into the out- bound ds1 frame. function of the transmit signaling data input signal will be discussed in details in later sec- tions. t able 168: s ignals for different t ransmit timing sources t ransmit t iming s ource t x s er c lk _ n t x s ync _ n t x ms ync _ n terminal equipment driven txserclk input input input oscclk driven divided clock output output output recovered receive line clock output output output transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 4 transmit fractional ds1 input enable r/w 0 - the transmit time-slot indication bits (txtsb[4:0] are outputting five-bit binary values of time-slot number (0-23) being accepted and processed by the transmit pay- load data input interface block of the framer. the transmit time-slot indicator clock signal (txtsclk_n) is a 192khz clock that pulses high for one ds1 bit period whenever the transmit payload data input interface block is accepting the lsb of each of the twenty-four time slots. 1 - the txtsb[0]_n bit becomes the transmit fractional t1 input signal (txfrtd_n) which carries fractional ds1 payload data into the framer. the txtsb[1]_n bit becomes the transmit signaling data input signal (txsig_n) which is used to insert robbed-bit signaling data into the outbound ds1 frame. the txtsb[2]_n bit serially outputs all five-bit binary values of the time slot number (0-23) being accepted and processed by the transmit payload data input interface block of the framer. the txtsb[3]_n bit becomes the transmit overhead synchronization pulse (txohsync_n) which is used to output an overhead synchronization pulse that indi- cates the first bit of each ds1multi-frame. the txtsclk_n will output gaped fractional ds1 clock that can be used by terminal equipment to clock out fractional ds1 payload data at rising edge of the clock. or,the txtsclk_n pin will be a clock enable signal to transmit fractional ds1 input signal (txfrtd_n) when the un-gaped transmit serail input clock (txserclk_n) is used to clock in fractional ds1 payload data into the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 256 when the transmit fractional t1 input enable bit is equal to one, the txtsb[2]_n bit serially outputs all five-bit bi- nary values of the time slot number (0-23) being accepted and processed by the transmit payload data input interface block of the framer. msb of the binary value is presented first and the lsb is presented last. when the transmit fractional t1 input enable bit is equal to one, the txtsb[3]_n bit becomes the transmit over- head synchronization pulse (txohsync_n). these pins can be used to output an overhead synchronization pulse that indicates the first bit of each ds1multi-frame. function of the transmit overhead synchronization out- put signal will be discussed in details in later sections. the txtsb[4]_n bit is not multiplexed. the table below shows functionality of the txtsb[3:0] bits when the transmit fractional t1 input bit is set to dif- ferent values. the transmit time-slot indicator clock signal (txtsclk_n) is a multi-function output pin. when configured to op- erate in normal condition (that is, when the transmit fractional t1 input enable bit is equal to zero), the txtsclk_n is a 192khz clock that pulses high for one ds1 bit period whenever the transmit payload data in- put interface block is accepting the lsb of each of the twenty-four time slots. the local terminal equipment should use this clock signal to sample the txtsb[0] through txtsb[4] bits and identify the time-slot being pro- cessed via the transmit section of the framer. when the transmit fractional t1 input enable bit is equal to one, the txtsclk_n will output gaped fractional ds1 clock at time-slots where fractional t1 input data is present. this clock can be used by terminal equipment to clock out fractional ds1 payload data at rising edge of the clock. the framer will then input fractional ds1 pay- load data using falling edge of the clock. otherwise, this pin can be configured as a clock enable signal to trans- mit fractional ds1 input signal (txfrtd_n) if the framer is set accordingly. in this way, fractional ds1 payload data is clocked into the framer using un-gaped transmit serail input clock (txserclk_n). a detailed discussion of the fractional ds1 payload data input interface can be found in later sections. both the transmit time-slot indicator clock (txtsclk_n) and the transmit time-slot indication bits (txts- bb[4:0]_n) are output signals in normal 1.544mbit/s back-plane mode regardless of the timing source of the transmit section of framer. 5.1.2.1 connect the transmit payload data input interface block to the local terminal equipment if transmit timing source = txserclk_n by setting the transmit timing source [1:0] bits of the clock select register to 01, the txserclk_n input signal is configured to be the timing source for the transmit section of the framer. the terminal equipment should supply an external free-running clock with frequency of 1.544mhz to the txserclk_n input pin. the transmit single- frame synchronization signal and the transmit multi-frame synchronization signal are inputs to the framer. the transmit single-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the framing bit position of each ds1 frame. by sampling the high pulse on the transmit single-frame synchroniza- tion signal, the framer can position the beginning of a ds1 frame. the transmit multi-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the fram- ing bit position of the first frame of a ds1 multi-frame. by sampling the high pulse on the transmit multi-frame synchronization signal, the framer can position the beginning of a ds1 super-frame. it is the responsibility of the terminal equipment to provide serial input data through the txser_n pin aligned with the transmit single-frame synchronization signal and the transmit multi-frame synchronization signal. see t able 169: t he t x ts b [3:0] bits when the t ransmit f ractional t1 i nput bit is set to different values t ransmit f ractional t1 i nput b it = 0 t ransmit f ractional t1 i nput b it = 1 txtsb[0] output txfrtd input txtsb[1] output txsig input txtsb[2] output txts output txtsb[3] output txohsync output
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 257 figure 47 below for how to connect the transmit payload data input interface block to the local terminal equip- ment with the transmit serial clock being the timing source of transmit section. f igure 47. i nterfacing XRT86L34 to local t erminal e quipment with t x s er c lk _ n as t ransmit t iming s ource txserclk_0 txser_0 txmsync_0 txsync_0 txtsclk_0 txtsb[4:0]_0 txserclk_3 txser_3 txmsync_3 txsync_3 txtsclk_3 txtsb[4:0]_3 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 258 figure 48 shows waveforms of the signals (txserclk_n, txser_n, txsync_n, txtsclk_n and txtsb[4:0]_n) that connect the transmit payload data input interface block to the local terminal equipment with the transmit serial clock being the timing source of transmit section. 5.1.2.2 connect the transmit payload data input interface block to the local terminal equipment if the transmit timing source = oscclk by setting the transmit timing source [1:0] bits of the clock select register (csr) to 10, the oscclk driven di- vided clock is configured to be the timing source for the transmit section of the framer. a free-running clock should apply to the oscclk input pin with frequencies of 12.352mhz, 24.704mhz and 49.408mhz depending on the setting of oscclk frequency select [1:0] bits of the clock select register (csr). the free-running oscclk is divided inside the XRT86L34 and routed to all four framers. this oscclk driven divided clock has to be 12.352mhz in frequency. when these bits are set to 00, the framer will internally divide the incoming oscclk by one. therefore, the external oscillator clock applied to the oscclk pin should be 12.352mhz. when these bits are set to 01, the framer will internally divide the incoming oscclk by two. there- fore, the external oscillator clock applied to the oscclk pin should be 24.704mhz. when these bits are set to 10, the framer will internally divide the incoming oscclk by four. therefore, the external oscillator clock applied to the oscclk pin should be 49.408mhz. the following table shows configurations of the oscclk frequency select [1:0] bits of the clock select register. f igure 48. w aveforms of the signals that connect the t ransmit p ayload d ata i nput i nterface block to the local t erminal e quipment with the t ransmit s erial clock being the t iming s ource of the t ransmit s ection c txserclk txserclk (inv) txser txsync(input) txchclk txchn[4:0] txchn[0]/txsig txtsb[4:0] txtsclk txchn[1]/txfrtd f f c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data input data input data input data timeslot #0 timeslot #5 timeslot #6 timeslot #23 timeslot 23 timeslot 0 timeslot 5 timeslot 6 a b d c a b d c a b d c a b d
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 259 the transmit serial clock signal pin (txserclk_n) is output from the framer. the framer outputs a 1.544mhz clock through this pin to the local terminal equipment. the transmit single-frame synchronization signal and the transmit multi-frame synchronization signal are also automatically configured to be output signals. the transmit single-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the last bit position of each ds1 frame. by triggering on the high pulse on the transmit single-frame synchronization signal, the local terminal equipment can identify the end of a ds1 frame and should start inserting payload data of the next ds1 frame to the framer. the transmit multi-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the last bit position of the last frame of a ds1 multi-frame. by triggering on the high pulse on the transmit multi-frame syn- chronization signal, the local terminal equipment can identify the end of a ds1 super-frame and should start in- serting payload data of the next ds1 multi-frame into the framer. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 3-2 oscclk frequency select r/w oscclk frequency select: these two read/write bit-fields permit the user to select internal clock dividing logic of the framer depending on the frequency of incoming oscillator clock (oscclk). the frequency of internal clock used by the framer should be 12.352mhz. 00 - the framer will internally divide the incoming oscclk by one. therefore, the external oscillator clock applied to the oscclk pin should be 12.352mhz. 01 - the framer will internally divide the incoming oscclk by two. therefore, the external oscillator clock applied to the oscclk pin should be 24.704mhz. 10 - the framer will internally divide the incoming oscclk by four. therefore, the external oscillator clock applied to the oscclk pin should be 49.408mhz.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 260 see figure 49 for how to connect the transmit payload data input interface block to the local terminal equip- ment with the oscclk driven divided clock as the timing source of transmit section. f igure 49. i nterfacing XRT86L34 to the local t erminal e quipment with the oscclk d riven d ivided c lock as t ransmit t iming s ource txserclk_0 txser_0 txmsync_0 txsync_0 txtsclk_0 txtsb[4:0]_0 txserclk_3 txser_3 txmsync_3 txsync_3 txtsclk_3 txtsb[4:0]_3 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 oscclk oscclk driven divided clock
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 261 figure 50 shows waveforms of the signals (txserclk_n, txser_n, txsync_n, txtsclk_n and txtsb[4:0]_n) that connect the transmit payload data input interface block to the local terminal equipment with the oscclk driv- en divided clock as the timing source of transmit section. 5.1.2.3 connect the transmit payload data input interface block to the local terminal equipment for loop-timing applications if the transmit timing source [1:0] bits of the clock select register are set to 00 or 11, the recovered receive line clock is configured to be the timing source for the transmit section of the framer. this is also known as the loop-timing mode. if the clock loss detection enable bit of the clock select register is set to one, and if the recovered receive line clock from the liu is lost, the framer will automatically begin to use the oscclk driven divided clock as transmit timing source until the liu is able to regain clock recovery. f igure 50. w aveforms of the signals connecting the t ransmit p ayload d ata i nput i nterface block to the local t erminal e quipment with the oscclk d riven d ivided clock as the timing source of the t ransmit s ection c txserclk txserclk (inv) txser txsync(output) txchclk txchn[4:0] txchn[0]/txsig txchclk txchn[1]/txfrtd f f c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data input data input data input data timeslot #0 timeslot #5 timeslot #6 timeslot #23 timeslot 23 timeslot 0 timeslot 5 timeslot 6 a b d c a b d c a b d c a b d txchn[0]/txsig
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 262 the following table shows configuration of the clock loss detection enable bit of the clock select register (csr). the transmit serial clock signal pin (txserclk_n) is output from the framer. the XRT86L34 routes the recov- ered receive line clock internally across the framer and output through the transmit serial clock signal pin to the local terminal equipment. the transmit single-frame synchronization signal and the transmit multi-frame synchronization signal are automatically configured to be output signals. the transmit single-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the last bit position of each ds1 frame. by triggering on the high pulse on the transmit single-frame synchronization signal, the local terminal equipment can identify the end of a ds1 frame and should start inserting payload data of the next ds1 frame to the framer. the transmit multi-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the last bit position of the last frame of a ds1 multi-frame. by triggering on the high pulse on the transmit multi-frame syn- chronization signal, the local terminal equipment can identify the end of a ds1 super-frame and should start in- serting payload data of the next ds1 multi-frame into the framer. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 4 clock loss detection enable r/w clock loss detection enable: this read/write bit-field permits the user to enable the clock loss detection logic for the framer when the recovered receive line clock is used as transmit timing source of the framer. 0 - the framer disables the clock loss detection logic. 1 - the framer enables the clock loss detection logic. if the recovered receive line clock is used as transmit timing source of the framer, and if clock recovered from the liu is lost, the framer can detect loss of the recovered receive line clock. upon detecting of this occurrence, the framer will automatically begin to use the oscclk driven divided clock as transmit timing source until the liu is able to regain clock recovery. n ote : this bit-field is ignored if the txserclk or the oscclk driven divided clock is chosen to be the timing source of transmit section of the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 263 see figure 51 for how to connect the transmit payload data input interface block to the local terminal equip- ment with the recovered receive line clock being the timing source of transmit section. f igure 51. i nterfacing XRT86L34 to local t erminal e quipment with r ecovered r eceive l ine c lock as t ransmit t iming s ource txserclk_0 txser_0 txmsync_0 txsync_0 txtsclk_0 txtsb[4:0]_0 txserclk_3 txser_3 txmsync_3 txsync_3 txtsclk_3 txtsb[4:0]_3 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 rxlineclk_0 rxlineclk_7
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 264 the following figure 52 shows waveforms of the signals (txserclk_n, txser_n, txsync_n, txtsclk_n and txtsb[4:0]_n) that connecting the transmit payload data input interface block to the local terminal equipment with the recovered receive line clock being the timing source of transmit section. 5.2 t ransmit h igh -s peed b ack -p lane i nterface the high-speed back-plane interface supports payload data to be taken from or presented to the terminal equip- ment at a rate higher than 1.544mbit/s. in ds1 mode, supported high-speed data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 12.352mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the transmit multiplex enable bit and the transmit interface mode select [1:0] bits of the transmit interface control register (ticr) determine the transmit back-plane interface data rate. the following table shows configurations of the transmit multiplex enable bit and the transmit interface mode select [1:0] bits of the transmit interface control register (ticr). f igure 52. w aveforms of the signals connecting the t ransmit p ayload d ata i nput i nterface block to the local t erminal e quipment with the r ecovered r eceive l ine c lock being the timing source of the t ransmit s ection transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 2 transmit multiplex enable r/w 0 - the transmit back-plane interface block is configured to non-channel-multiplexed mode. 1 - the transmit back-plane interface block is configured to channel-multiplexed mode 1-0 transmit interface mode select r/w when combined with the transmit multiplex enable bit, these bits determine the trans- mit back-plane interface data rate. c txserclk txserclk (inv) txser txsync(output) txchclk txchn[4:0] txchn[0]/txsig txchclk txchn[1]/txfrtd f f c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data input data input data input data timeslot #0 timeslot #5 timeslot #6 timeslot #23 timeslot 23 timeslot 0 timeslot 5 timeslot 6 a b d c a b d c a b d c a b d txchn[0]/txsig
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 265 the table below shows the combinations of transmit multiplex enable bit and transmit interface mode select [1:0] bits and the resulting transmit back-plane interface data rates. when the transmit multiplex enable bit is set to zero, the framer is configured in non-channel-multiplexed mode. the possible data rates are 1.544mbit/s, mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s. in non-channel-multi- plexed mode, payload data of each channel are taken from the terminal equipment separately. each channel us- es its own transmit serial clock, transmit serial data, transmit single-frame synchronization signal and trans- mit multi-frame synchronization signal as interface between the framer and the terminal equipment. section 1.1.2.1, 1.1.2.2 and 1.1.2.3 provide details on how to connect the transmit payload data interface block with the terminal equipment when the back-plane interface data rate is 1.544mbit/s. when the back-plane interface data rate is mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s, the transmit serial clock, transmit serial data, transmit single-frame synchronization signal and transmit multi-frame synchroni- zation signal are all configured as inputs. the transmit serial clock is always an input clock with frequency of 1.544 mhz for all data rates. the txmsync_n signal is configured as the transmit input clock with frequencies of 2.048 mhz, 4.096 mhz and 8.192 mhz respectively. it serves as the primary clock source for the high-speed back-plane interface. the table below summaries the clock frequencies of txserclk_n and txinclk_n inputs when the framer is oper- ating in non-multiplexed high-speed back-plane mode. when the transmit multiplex enable bit is set to one, the framer is configured in channel-multiplexed mode. the possible data rates are multiplexed 12.352mbit/s, bit-multiplexed 16.384mbit/s, hmvip 16.384mbit/s and h.100 16.384mbit/s. in channel-multiplexed mode, every four channels share the transmit serial data and transmit single-frame synchronization signal of one channel as interface between the framer and the local terminal equipment. the txmsync_n signal of one channel is configured as the transmit input clock with frequencies of 12.352 mhz or 16.384. it serves as the primary clock source for the high-speed back-plane interface. t able 170: t ransmit m ultiplex e nable bit and t ransmit i nterface m ode s elect [1:0] bits with the resulting t ransmit b ack - plane i nterface data rates t ransmit m ultiplex e nable b it t ransmit i nterface m ode s elect b it 1 t ransmit i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate 0 0 0 1.544mbit/s 0 0 1 mvip 2.048mbit/s 0 1 0 4.096mbit/s 0 1 1 8.192mbit/s 1 0 0 multiplexed 12.352mbit/s 1 0 1 bit multiplexed 16.384mbit/s 1 1 0 hmvip 16.384mbit/s 1 1 1 h.100 16.384mbit/s transmit multiplex enable bit = 0 t ransmit i nterface m ode s elect b it 1 t ransmit i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate t x s er c lk t x ms ync /t x i n c lk 0 0 1.544mbit/s 1.544 mhz - 0 1 mvip 2.048mbit/s 1.544 mhz 2.048 mhz 1 0 4.096mbit/s 1.544 mhz 4.096 mhz 1 1 8.192mbit/s 1.544 mhz 8.192 mhz
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 266 payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. pay- load and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. the transmit single-frame synchronization signal of channel 0 pulses high at the beginning of the frame with data from channel 0-3 multiplexed together. the transmit single-frame synchronization signal of channel 4 pulses high at the beginning of the frame with data from channel 4-7 multiplexed together. it is responsibility of the ter- minal equipment to align the multiplexed transmit serial data with the transmit single-frame synchronization pulse. additionally, each channel requires the local terminal equipment to provide a free-running 1.544 mhz clock into the transmit serial clock input. the table below summaries the clock frequencies of txserclk_n and txinclk_n inputs when the framer is oper- ating in multiplexed high-speed back-plane mode. the transmit serial clock is always running at 1.544mhz for all the high-speed back-plane interface modes. it is automatically the timing source of the transmit section of the framer in high-speed back-plane interface mode. the transmit single-frame synchronization signal should pulse high or low for one bit period at the framing bit position of each ds1 frame. length of the bit period depends on data rate of the high-speed back-plane inter- face. the transmit synchronization pulse low bit of the transmit interface control register (ticr) determines whether the transmit single-frame synchronization signal is high active or low active. the table below shows configurations of the transmit synchronization pulse low bit of the transmit interface control register (ticr). throughout the discussion of this datasheet, we assume that the transmit single-frame synchronization signal pulses high unless stated otherwise. the txmsync_n signal, which is a multiplexed i/o pin, no longer functions as the transmit multi-frame synchro- nization signal. indeed, it becomes the transmit input clock signal (txinclk) of the high-speed back-plane inter- face of the framer. the local terminal equipment should provide a free-running clock with the same frequency as the high-speed back-plane interface to this input pin. the following sections discuss details of how to operate the framer in different back-plane interface speed mode and how to connect the transmit payload data input interface block to the local terminal equipment. 5.2.0.1 t1 transmit input interface - mvip 2.048 mhz transmit multiplex enable bit = 1 t ransmit i nterface m ode s elect b it 1 t ransmit i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate t x s er c lk t x ms ync /t x c lk 0 0 multiplexed 12.352mbit/s 1.544 mhz 12.352 mhz 0 1 bit-multiplexed 16.384mbit/s 1.544 mhz 16.384 mhz 1 0 hmvip 16.384mbit/s 1.544 mhz 16.384 mhz 1 1 h.100 16.384mbit/s 1.544 mhz 16.384 mhz transmit interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 3transmit synchronization pulse low r/w 0 - the transmit single-frame synchronization signal will pulse high indicating the beginning of a ds1 frame when the high-speed back-plane interface is running at a mode other than the 1.544mbit/s. 1 - the transmit single-frame synchronization signal will pulse low indicating the beginning of a ds1 frame when the high-speed back-plane interface is running at a mode other than the 1.544mbit/s.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 267 when the transmit multiplex enable bit is set to zero and the transmit interface mode select [1:0] bits are set to 01, the transmit back-plane interface of framer is running at a data rate of 2.048mbit/s. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_n at an e1 equivalent data rate of 2.048mbit/ s. the local terminal equipment supplies a free-running 2.048mhz clock to he transmit input clock pin of the framer. the local terminal equipment also provides synchronized payload data at rising edge of the clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the transmit input clock. the local terminal equipment should pump in data grouped in 256-bit frame 8000 times ev- ery second. each frame consists of thirty-two octets as in e1. the local terminal equipment maps a 193-bit t1 frame into this 256-bit format as described below: 1. the framing (f-bit) is mapped into msb of the first e1 time-slot. the local terminal equipment will stuff the rest seven bits of the first octet with "don't care" bits that would be ignored by the framer. 2. payload data of t1 time-slot 0, 1 and 2 are mapped into e1 time-slot 1, 2 and 3. 3. the local terminal equipment will stuff e1 time-slot 4 with eight "don't care" bits that would be ignored by the framer. 4. following the same rules of step 2 and 3, the local terminal equipment maps every three time-slots of t1 payload data into four e1 time-slots. the mapping of t1 frame into e1 framing format is shown in the table below. the transmit single-frame synchronization input signal (txsync_n) should pulse high at the beginning (f-bit position) of the 256-bit frame indicating start of the frame. by sampling the high pulse on the transmit single- frame synchronization signal, the framer can position the beginning of a ds1 frame. it is responsibility of the local terminal equipment to align the transmit single-frame synchronization signal with serial data stream going into the framer. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are then processed by the framer and send to liu interface. the local terminal equipment provides a free-running 1.544mhz clock to the transmit serial input clock. the framer will use this clock to carry the processed payload and signaling data to the transmit section of the device. t able 171: t he mapping of t1 frame into e1 framing format t1 f-bit ts0 ts1 ts2 don't care bits ts3 ts4 ts5 e1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 t1 don't care bits ts6 ts7 ts8 don't care bits ts9 ts10 ts11 e1 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 t1 don't care bits ts12 ts13 ts14 don't care bits ts15 ts16 ts17 e1 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 t1 don't care bits ts18 ts19 ts20 don't care bits ts21 ts22 ts23 e1 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 268 see figure 53 below for how to interface the local terminal equipment with the transmit payload data input in- terface block of the framer in mvip 2.048mbit/s mode. the timing diagram of input signals to the framer when running at mvip 2.048mbit/s mode is shown in figure 54. 5.2.0.2 t1 transmit input interface - 4.096 mhz this interface mode is the same as running at 2.048 mhz. the only difference is that the transmit input clock runs two times faster at 4.096 mhz. f igure 53. i nterfacing XRT86L34 to the local t erminal e quipment using mvip 2.048m bit / s d ata b us f igure 54. t iming d iagram of the i nput s ignals to the f ramer when running at mvip 2.048m bit / s m ode txserclk_0 txser_0 txinclk_0 (2.048mhz) txsync_0 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 txserclk_3 txser_3 txinclk_3 (2.048mhz) txsync_3 txserclk txserclk (inv) txser txsync(input) txsync(input) mvip mode txchclk txchn[0]/txsig txsyncfrd=0 txchn[1]/txfrtd f 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care don't care c a b d don't care don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txchn[1]/txfrtd txchclk txsyncfrd=1
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 269 when the transmit multiplex enable bit is set to zero and the transmit interface mode select [1:0] bits are set to 10, the transmit back-plane interface of framer is running at a clock rate of 4.096mhz. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is still accepting data through txser_n at an e1 equivalent data rate of 2.048mbit/s. however, the local terminal equipment supplies a free-running 4.096mhz clock to the transmit in- put clock pin of the framer. the local terminal equipment provides synchronized payload data at every other ris- ing edge of the transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at every other falling edge of the clock. the local terminal equipment should pump in data grouped in 256-bit frame 8000 times every second. each frame consists of thirty-two octets as in e1. the local terminal equipment maps a 193-bit t1 frame into this 256-bit format as described below: 1. the framing (f-bit) is mapped into msb of the first e1 time-slot. the local terminal equipment will stuff the rest seven bits of the first octet with "don't care" bits that would be ignored by the framer. 2. payload data of t1 time-slot 0, 1 and 2 are mapped into e1 time-slot 1, 2 and 3. 3. the local terminal equipment will stuff e1 time-slot 4 with eight "don't care" bits that would be ignored by the framer. 4. following the same rules of step 2 and 3, the local terminal equipment maps every three time-slots of t1 payload data into four e1 time-slots. the mapping of t1 frame into e1 framing format is shown in the table below. the transmit single-frame synchronization input signal (txsync_n) should pulse high at the beginning (f-bit position) of the 256-bit frame indicating start of the frame. by sampling the high pulse on the transmit single- frame synchronization signal, the framer can position the beginning of a ds1 frame. it is responsibility of the local terminal equipment to align the transmit single-frame synchronization signal with serial data stream going into the framer. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are then processed by the framer and send to liu interface. the local terminal equipment provides a free-running 1.544mhz clock to the transmit serial input clock. the framer will use this clock to carry the processed payload and signaling data to the transmit section of the device. t able 172: t he mapping of t1 frame into e1 framing format t1 f-b it ts0 ts1 ts2 d on ' t c are b its ts3 ts4 ts5 e1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 t1 don't care bits ts6 ts7 ts8 don't care bits ts9 ts10 ts11 e1 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 t1 don't care bits ts12 ts13 ts14 don't care bits ts15 ts16 ts17 e1 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 t1 don't care bits ts18 ts19 ts20 don't care bits ts21 ts22 ts23 e1 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 270 see figure 55 below for how to interface the local terminal equipment with the transmit payload data input in- terface block of the framer in mvip 2.048mbit/s mode. the timing diagram of input signals to the framer when running at 4.096mbit/s mode is shown in figure 56 5.2.0.3 t1 transmit input interface - 8.192 mhz this interface mode is the same as running at 2.048 mhz. the only difference is that the transmit input clock runs four times faster at 8.192mhz. when the transmit multiplex enable bit is set to zero and the transmit interface mode select [1:0] bits are set to 11, the transmit back-plane interface of framer is running at a clock rate of 8.192mhz. the interface consists of the following pins: f igure 55. i nterfacing XRT86L34 to the local t erminal e quipment using 4.096m bit / s d ata b us f igure 56. t iming d iagram of the i nput s ignals to the f ramer when running at 4.096m bit / s m ode txserclk_0 txser_0 txinclk_0 (4.096mhz) txsync_0 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 txserclk_3 txser_3 txinclk_3 (4.096mhz) txsync_3 txserclk (2mhz) txserclk (inv) txser txsync(input) txchclk(inv) txchn[0]/txsig txchn[1]/txfrtd f 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txserclk (4mhz) don't care don't care
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 271 ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is still accepting data through txser_n at an e1 equivalent data rate of 2.048mbit/s. however, the local terminal equipment supplies a free-running 8.192mhz clock to the transmit in- put clock pin of the framer. the local terminal equipment provides synchronized payload data at every other four rising edge of the transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at every other four falling edge of the clock. the local terminal equipment should pump in data grouped in 256-bit frame 8000 times every second. each frame consists of thirty-two octets as in e1. the lo- cal terminal equipment maps a 193-bit t1 frame into this 256-bit format as described below: 1. the framing (f-bit) is mapped into msb of the first e1 time-slot. the local terminal equipment will stuff the rest seven bits of the first octet with "don't care" bits that would be ignored by the framer. 2. payload data of t1 time-slot 0, 1 and 2 are mapped into e1 time-slot 1, 2 and 3. 3. the local terminal equipment will stuff e1 time-slot 4 with eight "don't care" bits that would be ignored by the framer. 4. following the same rules of step 2 and 3, the local terminal equipment maps every three time-slots of t1 payload data into four e1 time-slots. the mapping of t1 frame into e1 framing format is shown in the table below. the transmit single-frame synchronization input signal (txsync_n) should pulse high at the beginning (f-bit position) of the 256-bit frame indicating start of the frame. by sampling the high pulse on the transmit single- frame synchronization signal, the framer can position the beginning of a ds1 frame. it is responsibility of the local terminal equipment to align the transmit single-frame synchronization signal with serial data stream going into the framer. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are then processed by the framer and send to liu interface. the local terminal equipment provides a free-running 1.544mhz clock to the transmit serial input clock. the framer will use this clock to carry the processed payload and signaling data to the transmit section of the device. t able 173: t he mapping of t1 frame into e1 framing format t1 f-bit ts0 ts1 ts2 don't care bits ts3 ts4 ts5 e1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 t1 don't care bits ts6 ts7 ts8 don't care bits ts9 ts10 ts11 e1 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 t1 don't care bits ts12 ts13 ts14 don't care bits ts15 ts16 ts17 e1 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 t1 don't care bits ts18 ts19 ts20 don't care bits ts21 ts22 ts23 e1 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 272 see figure 57 below for how to interface the local terminal equipment with the transmit payload data input in- terface block of the framer in mvip 2.048mbit/s mode. the timing diagram of input signals to the framer when running at 8.192mbit/s mode is shown in figure 58. 5.2.0.4 t1 transmit input interface - multiplexed 12.352mbit/s when the transmit multiplex enable bit is set to one and the transmit interface mode select [1:0] bits are set to 00, the transmit back-plane interface of framer is running at a clock rate of 12.352mhz. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) f igure 57. i nterfacing XRT86L34 to the l ocal t erminal e quipment using 8.192m bit / s d ata b us f igure 58. t iming d iagram of the i nput s ignals to the f ramer when running at 8.192m bit / s m ode txserclk_0 txser_0 txinclk_0 (8.192mhz) txsync_0 transmit payload data input interface chn 0 transmit payload data input interface chn 3 terminal equipment XRT86L34 txserclk_3 txser_3 txinclk_3 (8.192mhz) txsync_3 txserclk (2mhz) txserclk (inv) txser txsync(input) txchclk(inv) txchn[0]/txsig txchn[1]/txfrtd f 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txserclk (8mhz) don't care don't care
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 273 ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_0 or txser_4 pins at 12.352mbit/s. the local terminal equipment multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. free-running clocks of 12.352mhz is supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at rising edge of this transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the clock. the local terminal equipment maps four 1.544mbit/s ds1 data streams into this 12.352mbit/s data stream as de- scribed below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. f x : f-bit of channel x 2. payload data of four channels are repeated and grouped together in a bit-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of channel 3 is sent last. after the first bits of timeslot 0 of all four channels are sent, it comes the second bit of timeslot 0 of channel 0 and so on. the table below demon- strates how payload bits of four channels are mapped into the 12.352mbit/s data stream. x y : the xth payload bit of channel y 3. the local terminal equipment also multiplexed signaling bits with payload bits and sent them together through the 12.352mbit/s data stream. when the terminal equipment is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. simi- first octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 second octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 2 1 3 third octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 274 larly, the sixth payload bit of a particular channels is followed by the signaling bit b of that channel; the sev- enth payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 12.352mbit/ s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 4. following the same rules of step 2 and 3, the local terminal equipment maps the payload data and signal- ing data of four channels into a 12.352mbit/s data stream. the transmit single-frame synchronization signal of channel 0 pulses high for one clock cycle at the first bit po- sition (f-bit of channel 0) of the data stream with data from channel 0-3 multiplexed together. the transmit sin- gle-frame synchronization signal of channel 4 pulses high for one clock cycle at the first bit position (f-bit of channel 4) of the data stream with data from channel 4-7 multiplexed together. by sampling the high pulse on the transmit single-frame synchronization signal, the framer can position the beginning of the multiplexed ds1 frame. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchronization pulse. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are de-multiplexed inside the XRT86L34 and send to each individual channel. these data will be processed by each individual framer and send to liu interface. the local terminal equipment provides a free-running 1.544mhz clock to the transmit serial input clock of each channel. the framer will use this clock to carry the processed pay- load and signaling data to the transmit section of the device. sixth octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 seventh octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 eighth octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3 nineth octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 275 see figure 59 below for how to interface the local terminal equipment with the transmit payload data input in- terface block of the framer in 12.352mbit/s mode. the input signal timing is shown in figure 60 below when the framer is running at 12.352mbit/s mode. 5.2.0.5 t1 transmit input interface - bit-multiplexed 16.384mbit/s when the transmit multiplex enable bit is set to one and the transmit interface mode select [1:0] bits are set to 01, the transmit back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) f igure 59. i nterfacing XRT86L34 to the l ocal t erminal e quipment using b it -m ultiplexed 12.352m bit / s d ata b us f igure 60. t iming d iagram of the i nput s ignals to the f ramer when running at 12.352m bit / s m ode txser_0 txinclk_0 (12.352mhz) txsync_0 txserclk_0 (1.544mhz) transmit payload data input interface chn 0 terminal equipment XRT86L34 chn 1 chn 2 chn 3 txserclk_1 (1.544mhz) txserclk_2 (1.544mhz) txserclk_3 (1.544mhz) txserclk (12.352mhz) txserclk (inv) txser txsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 276 ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_0 or txser_4 pins at 16.384mbit/s. the local terminal equipment multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. free-running clocks of 16.384mhz is supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at rising edge of this transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the clock. the local terminal equipment maps four 1.544mbit/s ds1 data streams into this 16.384mbit/s data stream as de- scribed below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. f x : f-bit of channel x 2. after the first octet of data is sent, the local terminal equipment should insert seven octets (fifty-six bits) of "don't care" data into the outgoing data stream. 3. payload data of four channels are repeated and grouped together in a bit-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of channel 3 is sent last. after the first bits of timeslot 0 of all four channels are sent, it comes the second bit of timeslot 0 of channel 0 and so on. the table below demon- strates how payload bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 nineth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 2 1 3 tenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 277 4. the local terminal equipment also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the terminal equipment is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. simi- larly, the sixth payload bit of a particular channels is followed by the signaling bit b of that channel; the sev- enth payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/ s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 5. after payload bits of timeslot 0, 1 and 2 of all four channels are sent, the terminal equipment should stuff another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream. 6. following the same rules of step 2 to 5, the local terminal equipment stuffs eight octets of "don't care" data after sending twenty-four octets of multiplexed payload and signaling data. a 16.384mbit/s data stream is thus created. the transmit single-frame synchronization signal of channel 0 pulses high for one clock cycle at the first bit po- sition (f-bit of channel 0) of the data stream with data from channel 0-3 multiplexed together. the transmit sin- gle-frame synchronization signal of channel 4 pulses high for one clock cycle at the first bit position (f-bit of channel 4) of the data stream with data from channel 4-7 multiplexed together. by sampling the high pulse on the transmit single-frame synchronization signal, the framer can position the beginning of the multiplexed ds1 frame. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchronization pulse. thirteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 fourteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 fifteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3 sixteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 278 inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are de-multiplexed inside the XRT86L34 and send to each individual channel. these data will be processed by each individual framer and send to liu interface. the local terminal equipment provides a free-running 1.544mhz clock to the transmit serial input clock of each channel. the framer will use this clock to carry the processed pay- load and signaling data to the transmit section of the device. see figure 61 below for how to interface the local terminal equipment with the transmit payload data input in- terface block of the framer in bit-multiplexed 16.384mbit/s mode. the input signal timing is shown in figure 62 below when the framer is running at bit-multiplexed 16.384mbit/s mode. 5.2.0.6 t1 transmit input interface - hmvip 16.384mbit/s f igure 61. i nterfacing XRT86L34 to the l ocal t erminal e quipment using 16.384m bit / s d ata b us f igure 62. t iming d iagram of the i nput s ignals to the f ramer when running at b it -m ultiplexed 16.384m bit / s m ode txser_0 txinclk_0 (16.384mhz) txsync_0 txserclk_0 (1.544mhz) transmit payload data input interface chn 0 terminal equipment XRT86L34 chn 1 chn 2 chn 3 txserclk_1 (1.544mhz) txserclk_2 (1.544mhz) txserclk_3 (1.544mhz) txserclk (16.384mhz) txserclk (inv) txser txsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 56 cycles
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 279 when the transmit multiplex enable bit is set to one and the transmit interface mode select [1:0] bits are set to 10, the transmit back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_0 or txser_4 pins at 16.384mbit/s. the local terminal equipment multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. free-running clocks of 16.384mhz is supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at rising edge of this transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the clock. the local terminal equipment maps four 1.544mbit/s ds1 data streams into this 16.384mbit/s data stream as de- scribed below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. f x : f-bit of channel x 2. after the first octet of data is sent, the local terminal equipment should insert seven octets (fifty-six bits) of "don't care" data into the outgoing data stream. 3. 3.payload data of four channels are repeated and grouped together in a byte-interleaved way. the first payload bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the terminal equip- ment will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 ninth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 280 x y : the xth payload bit of channel y 4. the local terminal equipment also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the terminal equipment is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. simi- larly, the sixth payload bit of a particular channels is followed by the signaling bit b of that channel; the sev- enth payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. eleventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 thirteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 fifteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3 tenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0 twelfth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 fourteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 281 x y : the xth payload bit of channel y a y : the signaling bit a of channel y 5. after payload bits of timeslot 0, 1 and 2 of all four channels are sent, the terminal equipment should stuff another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream. 6. following the same rules of step 2 to 5, the local terminal equipment stuffs eight octets of "don't care" data after sending twenty-four octets of multiplexed payload and signaling data. a 16.384mbit/s data stream is thus created. the transmit single-frame synchronization signal should pulse high for four clock cycles (the last two bit posi- tions of the previous multiplexed frame and the first two bits of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the transmit single-frame synchronization signal of channel 0 pulses high to identify the start of multiplexed data stream of channel 0-3. the transmit single-frame synchronization signal of channel 4 pulses high to identify the start of multiplexed data stream of channel 4-7. by sampling the high pulse on the transmit single-frame synchronization signal, the framer can position the beginning of the multiplexed ds1 frame. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchronization pulse. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are de-multiplexed inside the XRT86L34 and send to each individual channel. these data will be processed by each individual framer and send to liu interface. the local terminal equipment provides a free-running 1.544mhz clock to the transmit serial input clock of each channel. the framer will use this clock to carry the processed pay- load and signaling data to the transmit section of the device. sixteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 282 see figure 63 below for how to interface the local terminal equipment with the transmit payload data input in- terface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 64 below when the framer is running at hmvip 16.384mbit/s mode. 5.2.0.7 t1 transmit input interface - h.100 16.384mbit/s when the transmit multiplex enable bit is set to one and the transmit interface mode select [1:0] bits are set to 11, the transmit back-plane interface of framer is running at h.100 16.384mbit/s mode. (the hmvip mode and the h.100 mode are essential the same except for the high pulse position of the trans- mit single-frame synchronization signal) f igure 63. i nterfacing XRT86L34 to the l ocal t erminal e quipment using 16.384m bit / s d ata b us f igure 64. t iming d iagram of the i nput s ignals to the f ramer when running at hmvip 16.384m bit / s m ode txser_0 txinclk_0 (16.384mhz) txsync_0 txserclk_0 (1.544mhz) transmit payload data input interface chn 0 terminal equipment XRT86L34 chn 1 chn 2 chn 3 txserclk_1 (1.544mhz) txserclk_2 (1.544mhz) txserclk_3 (1.544mhz) txserclk (16.384mhz) txserclk (inv) txser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 txsig txsync(input) hmvip, negative sync txsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 283 the interface consists of the following pins: ? data input (txser_n) ? transmit serial clock input signal (txserclk_n) ? transmit single-frame synchronization input signal (txsync_n) ? transmit input clock (txinclk_n) ? transmit time-slot indication clock (txtsclk_n) ? transmit time slot indicator bits (txtsb[4:0]_n) the transmit back-plane interface is accepting data through txser_0 or txser_4 pins at 16.384mbit/s. the local terminal equipment multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the transmit serial data pin of channel 4. free-running clocks of 16.384mhz is supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at rising edge of this transmit input clock. the transmit high-speed back-plane interface of the framer then latches incoming serial data at falling edge of the clock. the local terminal equipment maps four 1.544mbit/s ds1 data streams into this 16.384mbit/s data stream as de- scribed below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. fx: f-bit of channel x 2. after the first octet of data is sent, the local terminal equipment should insert seven octets (fifty-six bits) of "don't care" data into the outgoing data stream. 3. 3.payload data of four channels are repeated and grouped together in a byte-interleaved way. the first payload bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the terminal equip- ment will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 ninth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 284 x y : the xth payload bit of channel y 4. the local terminal equipment also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the terminal equipment is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. simi- larly, the sixth payload bit of a particular channels is followed by the signaling bit b of that channel; the sev- enth payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. eleventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 thirteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 fifteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3 tenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0 twelfth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 fourteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 285 x y : the xth payload bit of channel y a y : the signaling bit a of channel y 5. after payload bits of timeslot 0, 1 and 2 of all four channels are sent, the terminal equipment should stuff another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream. 6. following the same rules of step 2 to 5, the local terminal equipment stuffs eight octets of "don't care" data after sending twenty-four octets of multiplexed payload and signaling data. a 16.384mbit/s data stream is thus created. the transmit single-frame synchronization signal should pulse high for two clock cycles (the last bit position of the previous multiplexed frame and the first bit position of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the transmit single-frame synchronization signal of channel 0 pulses high to identify the start of multiplexed data stream of channel 0-3. the transmit single-frame synchronization signal of channel 4 pulses high to identify the start of multiplexed data stream of channel 4-7. by sampling the high pulse on the transmit single-frame synchronization signal, the framer can position the beginning of the multi- plexed ds1 frame. it is responsibility of the terminal equipment to align the multiplexed transmit serial data with the transmit single-frame synchronization pulse. inside the framer, all the "don't care" bits will be stripped away. the framing bits, signaling and payload data are de-multiplexed inside the XRT86L34 and send to each individual channel. these data will be processed by each individual framer and send to liu interface. the local terminal equipment provides a free-running 1.544mhz clock to the transmit serial input clock of each channel. the framer will use this clock to carry the processed pay- load and signaling data to the transmit section of the device. sixteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 286 see figure 65 below for how to interface the local terminal equipment with the transmit payload data input in- terface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 66 below when the framer is running at h.100 16.384mbit/s mode. 5.3 ds1 t ransmit f ramer b lock 5.3.1 how to configure XRT86L34 to operate in ds1 mode f igure 65. i nterfacing XRT86L34 to the l ocal t erminal e quipment using 16.384m bit / s d ata b us f igure 66. t iming d iagram of the i nput s ignals to the f ramer when running at h.100 16.384m bit / s m ode txser_0 txinclk_0 (16.384mhz) txsync_0 txserclk_0 (1.544mhz) transmit payload data input interface chn 0 terminal equipment XRT86L34 chn 1 chn 2 chn 3 txserclk_1 (1.544mhz) txserclk_2 (1.544mhz) txserclk_3 (1.544mhz) txserclk (16.384mhz) txserclk (inv) txser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 txsig start of frame x y : x is the bit number and y is the channel number txsync(input) h.100, negative sync txsync(input) h.100, positive sync delayer h.100 txsync(input) h.100, negative sync txsync(input) h.100, positive sync
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 287 the XRT86L34 octal t1/e1/j1 framer supports ds1, j1 or e1 framing modes. since j1 standard is very sim- ilar to ds1 standard with a few minor changes, the j1 framing mode is included as a sub-set of the ds1 fram- ing mode. all four framers within the XRT86L34 silicon can be individually configured to support ds1, j1 or e1 framing modes. n ote : if transmitting section of one framer is configured to support either one of the framing modes, the receiving section is automatically configured to support the same framing modes. the t1/e1 select bit of the clock select register (csr) controls which framing mode, that is, t1/j1 or e1, supported by the framer. the table below illustrates configurations of the t1/e1 select bit of the clock select register (csr). since j1 and ds1 are two very similar standards, to configure the framer to run in j1 mode, the user has to se- lect ds1 mode by setting the t1/e1 select bit of the clock select register to 1 first. the next step is to set the j1 crc calculation bit of the framing select register (fsr). if this bit is set to 1, the XRT86L34 will do crc-6 calculation in j1 mode. that is, the crc-6 calculation is based on the actual val- ues of all 4,632 bits in ds1 multi-frame including framing bits. if this bit is set to 0, the XRT86L34 will perform crc-6 calculation in ds1 mode. that is, the crc-6 calculation is done based on the actual values of 4,608 payload bits of a ds1 multi-frame and assumes that all the framing bits are one. the table below shows configurations of the j1 crc calculation bit of the framing select register (fsr). the table below provides summary of how to select different operating modes for the XRT86L34 framer. the purpose of the ds1 transmit framer block is to embed and encode user payload data into frames and to route this ds1 frame data to the transmit ds1 liu interface block. please note that the XRT86L34 has four (4) individual ds1 transmit framer blocks. hence, the following description applies to all four of these individual transmit ds1 framer blocks. the purpose of the ds1 transmit framer block is: ? to encode user data, inputted from the terminal equipment into a standard framing format. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 6 t1/e1 select r/w 0 - the XRT86L34 framer is running in e1 mode. 1 - the XRT86L34 framer is running in t1 mode. framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 5 j1 crc calculation r/w in j1 format, crc-6 calculation is done based on the actual values of all payload bits as well as the framing bits. in ds1 format, crc-6 calculation is done based on the payload bits only while assuming all the framing bits are one. 0 - the framer performs crc-6 calculation in ds1 format. 1 - the framer performs crc-6 calculation in j1 format. this feature permits the driver to comply with j1 standard. t1/e1 s elect bit of csr j1 crc c alculation bit of fsr t1 set to 1 set to 0 j1 set to 1 set to 1 e1 set to 0 -
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 288 ? to provide individual data control and signaling conditioning of each ds0 channel. ? to support the transmission of hdlc messages, from the local transmitting terminal, to the remote receiving terminal. ? to transmit indications that the local receive framer has received error frames from the remote terminal. ? to transmit alarm condition indicators to the remote terminal. the following sections discuss functionalities of the ds1 transmit framer block in details. we will also de- scribe how to configure the XRT86L34 to transmit ds1 frames according to system requirement of users. 5.3.2 how to configure the framer to transmit data in various ds1 framing formats the XRT86L34 octal t1/e1/j1 framer supports the following ds1 framing formats: ? super-frame format (sf), also referred to as d4 framing ? extended super-frame format (esf) ? non-signaling format (n) ? t1dm framing format ? slca96 data link framing format, which use the super-frame (sf) framing structure n ote : if the framer is configured to transmit ds1 frames according to one particular framing format, the receiving side of the framer is also configured to receive ds1 frames according to the same framing format. the user can set the framing format select [2:0] bits of the framing select register (fsr) to determine which ds1 framing format should XRT86L34 be configured to operate. the table below shows configurations of the framing format select [2:0] bits of the framing select register (fsr). 5.3.3 how to configure the framer to input framing alignment bits from different sources in ds1 mode, different framing formats are distinguished by different patterns and functions of the framing alignment bit (first bit of a ds1 frame). the XRT86L34 can generate the framing alignment bits internally ac- cording to a particular framing format. at the same time, the users can generate the framing alignment bits externally and insert them into the framer through the transmit serial data input interface block via the txser_n pin. it is the user's responsibility to maintain the accuracy and integrity of the framing alignment bits. the user also has to make sure that the fram- framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 2-0 t1 framing select r/w t1 framing select: these read/write bit-fields allow the user to select one of the five t1 framing formats supported by the framer. these framing formats include esf, slca96, sf, n and t1dm mode. n ote : changing of framing format automatically forces the framer to perform re-synchronization. 0 x x bit 2 bit 1 bit 0 1 0 0 1 0 1 1 1 0 1 1 1 framing format esf slc?96 sf n t1dm
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 289 ing alignment bits are inserted into the framer at right position and right timing. however, this option is only available when the XRT86L34 is configured to run at a normal back-plane rate of 1.544mbit/s. the framing bit source select bit of the synchronization mux register (smr) controls source of the framing alignment bit. the table below shows configurations of the framing bit source select bit of the synchroniza- tion mux register (smr). 5.3.4 how to configure the framer to input crc-6 bits from different sources if the framer is configured to operate in extended super-frame format, the framing bits of frame number 2, 6, 10, 14, 18 and 22 of an esf multi-frame are used as cyclic redundancy check (crc-6) code of the last esf multi-frame. the crc-6 bits are an indicator of the link quality and could be monitored by the user to establish error performance report. the XRT86L34 can generate the crc-6 bits internally by calculating the crc check-sum of all the 4,632 bits in ds1 multi-frame while assuming the framing bits to be one. at the same time, the users can generate the crc-6 bits externally and insert them into the framer through the transmit serial data input interface block via the txser_n pin. it is the user's responsibility to correctly com- pute the crc-6 bits according to ds1 algorithm. also, the user has to make sure that the crc-6 bits are in- serted into the framer at right position and right timing. however, this option is only available when the XRT86L34 is configured to run at a normal back-plane rate of 1.544mbit/s. the crc-6 source select bit of the synchronization mux register (smr) controls from where to input crc-6 bits into the framer. the table below shows configurations of the crc-6 source select bit of the synchroniza- tion mux register (smr). 5.3.5 how to configure the framer to apply data and signaling conditioning to ds1 payload data on a per-channel basis the XRT86L34 t1/j1/e1 octal framer provides individual control of each of the twenty-four ds0 channels. the user can apply data and signaling conditioning to raw ds1 payload data coming from the terminal equip- ment on a per-channel basis. synchronization mux register (smr) (address = 0xn109h) b it n umber b it n ame b it t ype b it d escription 0 framing bit source r/w framing bit source: this read/write bit-field permits the user to determine where the framing alignment bits should be inserted. 0 - the framing alignment bits are generated and inserted by the framer internally. 1 - if the framer is operating in normal 1.544mbit/s mode, the framing alignment bits are passed through from the transmit serial data input interface block via the txser_n pin. synchronization mux register (smr) (address = 0xn109h) b it n umber b it n ame b it t ype b it d escription 1 crc-6 source select r/w crc-6 source select: this read/write bit-field permits the user to determine where the crc-6 bits should be inserted. 0 - the crc-6 bits are generated and inserted by the framer internally. 1 - if the framer is operating in normal 1.544mbit/s mode, the crc-6 bits are gen- erated by external equipment and passed through from the transmit serial data input interface block via the txser_n pin.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 290 the XRT86L34 framer can apply the following changes to raw ds1 pcm data coming from the terminal equip- ment on a per-channel basis: ? all 8 bits of the input pcm data are inverted ? the even bits of the input pcm data are inverted ? the odd bits of the input pcm data are inverted ? the msb of the input pcm data is inverted ? all input pcm data except the msb are inverted configuration of the XRT86L34 framer to apply the above-mentioned changes to raw ds1 pcm data are con- trolled by the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of each ds0 channel. the XRT86L34 framer can also replace the incoming raw ds1 pcm data from the terminal equipment with pre-defined or user-defined codes. the XRT86L34 supports the following conditioning substitutions: ? busy code - an octet with hexadecimal value of 0x7f ? busy_ts code - an octet of pattern "111xxxxx" where "xxxxx" represents the timeslot number ? vacant code - an octet with hexadecimal value of 0xff ? a-law digital milliwatt code ? u-law digital milliwatt code ? idle code - an octet defined by the value stored in the user idle code register (ucr) ? moof code - mux-out-of-frame code with hexadecimal value of 0x1a ? prbs code - an octet generated by the pseudo-random bit sequence (prbs) generator block of the framer once again, configuration of the XRT86L34 framer to replace raw ds1 pcm data with the above-mentioned coding schemes are controlled by the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of each ds0 channel. finally, the XRT86L34 framer can configure any one or ones of the twenty-four ds0 channels to be d or e channels. d channel is used primarily for data link applications. e channel is used primarily for signaling for cir- cuit switching with multiple access configurations. the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of each channel determine whether that particular channel is configured as d or e channel.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 291 the table below illustrates configurations of the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr). 5.3.6 how to apply user idle code to the ds1 payload data when the transmit data conditioning select [3:0] bits of the transmit channel control register (tccr) of a particular ds0 channel are set to 0100, input ds1 pcm data of this ds0 channel are replaced by the octet stored in user idle code register (ucr). the table below shows contents of the user idle code register. let us study the following example of applying the user idle code. in t1dm mode, the time slot 24 of a ds1 frame is used for synchronization and alarm. to generate the t1dm framing mode externally, the user can do the following: ? write the t1dm synchronization word (0xbc) to the user idle code register of the time slot 24. ? set the transmit data conditioning select [3:0] bits of the tccr of channel 24 to "0100". upon doing the above, the payload data of channel 24 will be replaced by the t1dm synchronization code 0xbc. transmit channel control register (tccr) (address = 0xn300h - 0xn31fh) b it n umber b it n ame b it t ype b it d escription 3-0 transmit conditioning select r/w 0000 - the input ds1 pcm data of this ds0 channel is unchanged. 0001 - all 8 bits of the input ds1 pcm data of this ds0 channel are inverted. 0010 - the even bits of the input ds1 pcm data of this ds0 channel are inverted. 0011 - the odd bits of the input ds1 pcm data of this ds0 channel are inverted. 0100 - the input ds1 pcm data of this ds0 channel are replaced by the octet stored in user idle code register (ucr). 0101 - the input ds1 pcm data of this ds0 channel are replaced by busy code (0x7f). 0110 - the input ds1 pcm data of this ds0 channel are replaced by vacant code (0xff). 0111 - the input ds1 pcm data of this ds0 channel are replaced by busy_ts code (111xxxxx). 1000 - the input ds1 pcm data of this ds0 channel are replaced by mux-out- of-frame (moof) code with value 0x1a. 1001 - the input ds1 pcm data of this ds0 channel are replaced by the a-law digital milliwatt pattern. 1010 - the input ds1 pcm data of this ds0 channel are replaced by the u-law digital milliwatt pattern. 1011 - the msb bit of the input ds1 pcm data of this ds0 channel is inverted. 1100 - all bits of the input ds1 pcm data of this ds0 channel except msb bit are inverted. 1101 - the input ds1 pcm data of this ds0 channel are replaced by prbs pat- tern created by the internal prbs generator of XRT86L34 framer. 1110 - the input ds1 pcm data of this ds0 channel is unchanged. 1111 - this channel is configured as d or e timeslot. user idle code register (ucr) (address = 0xn320h - 0x337h) b it n umber b it n ame b it t ype b it d escription 7-0 user idle code r/w these read/write bit-fields permits the user store any value of idle code into the framer. when the transmit data conditioning select [3:0] bits of tccr register of a particular ds0 channel are set to 0100, the input ds1 pcm data are replaced by contents of this register and sent to the transmit liu interface.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 292 5.3.7 how to configure the XRT86L34 framer to apply zero code suppression to ds1 payload data on a per-channel basis in order to guarantee adequate clock recovery from the received pcm data, a minimum "ones density" must be maintained. in the case of an all zero channel, that is, if all the incoming pcm data of a particular ds0 channel from the terminal equipment is zero, the raw pcm data is replaced by a certain pattern that no more than fif- teen consecutive zeros will occur. it is known as zero code suppression. the XRT86L34 framer supports three types of zero code suppression schemes: ? at&t bit 7 stuffing - an old coding method that forces bit 7 (the second lsb of a ds0 channel) to a 1 in an all zero channel. ? gte zero code suppression - bit 8 (the lsb of a ds0 channel) is stuffed by 1 in non-signaling frame in an all zero channel. otherwise, bit 7 is stuffed by 1 in signaling frame if the signaling bit is zero. ? dds zero code suppression - an octet with hexadecimal value of 0x98 is used to replace the input data if it is all zero. the transmit zero code suppression select [1:0] bits of the transmit channel control register (tccr) of a particular ds0 channel is used to select which type of zero code suppression scheme is used by the framer. the table below shows configurations of the transmit zero code suppression select [1:0] bits of the transmit channel control register (tccr). 5.3.8 how to configure the XRT86L34 framer to transmit robbed-bit signaling information the XRT86L34 t1/j1/e1 octal framer supports insertion of robbed-bit signaling information into the outgoing ds1 frame. it also supports extraction and substitution of robbed-bit signaling information from the incoming ds1 frame. the following section provides a brief overview of robbed-bit signaling in ds1 mode. 5.3.9 brief discussion of robbed-bit signaling in ds1 framing format signaling is required when dealing with voice and dial-up data services in ds1 applications. traditionally, sig- naling is provided on a dial-up telephone line, across the talk-path. bit robbing, or stealing the least significant bit (8th bit) in each of the twenty-four voice channels in the signaling frames allows enough bits to signal be- tween the transmitting and receiving end. that is how the name robbed-bit signaling comes from. these ends can be cpe to central office (co) for switched services, or cpe to cpe for pbx-to-pbx connections. signaling is used to tell the receiver where the call or route is destined. the signal is sent through switches along the route to a distant end. common types of signals are: ? on hook ? off hook ? dial tone ? dialed digits ? ringing cycle ? busy tone robbed-bit signaling is supported in three ds1 framing formats: ? super-frame (sf) ? slc?96 transmit channel control register (tccr) (address = 0xn300h - 0x31fh) b it n umber b it n ame b it t ype b it d escription 5-4 transmit zero code suppression select r/w 00 - the input ds1 pcm data of this ds0 channel is unchanged. no zero code suppression is used. 01 - at&t bit 7 stuffing is used. 10 - gte zero code suppression is used. 11 - dds zero code suppression is used.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 293 ? extended super-frame (esf) in super-frame or slc?96 framing mode, frame number 6 and frame number 12 are signaling frames. in channelized ds1 applications, these frames are used to contain the signaling information. in frame number 6 and 12, the least significant bit of all twenty-four timeslots is 'robbed' to carry call state information. the bit in frame 6 is called the a bit and the bit in frame 12 is called the b bit. the combination of a and b defines the state of the call for the particular timeslot that these two bits are located. in extended super-frame framing mode, frame number 6, 12, 18 and 24 are signaling frames. in these frames, the least significant bit of all twenty-four timeslots is 'robbed' to carry call state information. the bit in frame 6 is called the a bit, the bit in frame 12 is called the b bit, the bit in frame 18 is called the c bit and the bit in frame 24 is called the d bit. the combination of a, b, c and d defines the state of the call for the particular timeslot that these signaling bits are located. 5.3.10 configure the framer to transmit robbed-bit signaling the XRT86L34 framer supports transmission of robbed-bit signaling in esf, sf and slc?96 framing for- mats. signaling bits can be inserted into the outgoing ds1 frame through the following: ? signaling data is inserted from transmit signaling control registers (tscr) of each timeslot ? signaling data is inserted from txsig_n pin ? signaling data is embedded into the input pcm data coming from the terminal equipment 5.3.10.1 insert signaling bits from tscr register the four most significant bits of the transmit signaling control register (tscr) of each timeslot can be used to store outgoing signaling data. the user can program these bits through microprocessor access. if the XRT86L34 framer is configure to insert signaling bits from tscr registers, the ds1 transmit framer block will strip off the least significant bits of signaling frames and replace it with the signaling bit stored inside the tscr registers. the insertion of signaling bit into pcm data is done on a per-channel basis. the most significant bit (bit 7) of tscr register is used to store signaling bit a. bit 6 is used to hold signaling bit b. bit 5 is used to hold signaling bit c. bit 4 is used to hold signaling bit d. in sf or slca96 mode, the user can control the XRT86L34 framer to transmit no signaling (transparent), two- code signaling, or four-code signaling. two-code signaling is done by substituting the least significant bit (lsb) of the specific channel in frame 6 and 12 with the content of the signaling bit a of the specific tscr register. n ote : the user should make sure that signaling bit a and signaling bit b of the specific tscr register have the same value. four-code signaling is done by substituting the lsb of channel data in frame 6 with the signaling bit a and the lsb of channel data in frame 12 with the signaling bit b of the specific channel's tscr register. if sixteen- code signaling is selected in sf format, only the signaling bit a and signaling bit b information are used. in esf mode, the user can control the XRT86L34 framer to transmit no signaling (transparent) by disable sig- naling insertion, two-code signaling, four-code signaling or sixteen code signaling. two-code signaling is done by substituting the least significant bit (lsb) of the specific channel in frame 6, 12, 18 and 24 with the content of the signaling bit a of the specific tscr register. f rame n umber s ignaling b it 6a 12 b f rame n umber s ignaling b it 6a 12 b 18 c 24 d
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 294 n ote : the user should duplicate the contents of signaling bit a of the specific tscr register to signaling bit b, c and d. four-code signaling is done by substituting the lsb of channel data in frame 6 and frame 18 with the signaling bit a and the lsb of channel data in frame 12 and frame 24 with the signaling bit b of the specific channel's tscr register. n ote : the user should duplicate the contents of signaling bit a of the specific tscr register to signaling bit c and dupli- cate the contents of signaling bit b of the specific tscr register to signaling bit d. sixteen-code signaling is implemented by substituting the lsb of channel data in frames 6, 12, 18, and 24 with the content of signaling bit a, b, c, and d of tscr register respectively. in n mode, no robbed-bit signaling is allowed and the transmit data stream remains intact. the table below shows the four most significant bits of the transmit signaling control register. 5.3.10.2 insert signaling bits from txsig_n pin the XRT86L34 framer can be configure to insert signaling bits provided by external equipment through the txsig_n pins. this pin is a multiplexed i/o pin with two functions: ? txtsb[0]_n - transmit timeslot number bit [0] output pin ? txsig_n - transmit signaling input pin when the transmit fractional ds1 bit of the transmit interface control register (ticr) is set to 0, this pin is configured as txtsb[0]_n pin, it outputs bit 0 of the timeslot number of the ds1 pcm data that is transmitting. when the transmit fractional ds1 bit of the transmit interface control register (ticr) is set to 1, this pin is configured as txsig_n pin, it acts as an input source for the signaling bits to be transmitted in the outbound ds1 frames. figure 67 below is a timing diagram of the txsig_n input pin. please note that the signaling bit a of a certain timeslot coincides with bit 5 of the pcm data; signaling bit b coincides with bit 6 of the pcm data; signaling bit c coincides with bit 7 of the pcm data and signaling bit d coincides with bit 8 (lsb) of the pcm data. transmit signaling control register (tscr) (address = 0xn340h - 0xn357h) b it n umber b it n ame b it t ype b it d escription 7 signaling bit a r/w this bit is used to store signaling bit a that is sent as the least significant bit of timeslot of frame number 6. 6 signaling bit b r/w this bit is used to store signaling bit b that is sent as the least significant bit of timeslot of frame number 12. 5 signaling bit c r/w this bit is used to store signaling bit c that is sent as the least significant bit of timeslot of frame number 18. 4 signaling bit d r/w this bit is used to store signaling bit d that is sent as the least significant bit of timeslot of frame number 24. f igure 67. t iming d iagram of the t x s ig _ n i nput
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 295 the table below shows configurations of the transmit fractional ds1 bit of the transmit interface control reg- ister (ticr). 5.3.10.3 insert signaling data from txser_n pin depends on applications, the terminal equipment can embed signaling information into the ds1 pcm data and then send the data to the XRT86L34 framer device. in this case, the user should configure the framer not to insert any signaling data. the input ds1 pcm data will then be directed to the transmit liu interface without any modifications. 5.3.10.4 enable robbed-bit signaling and signaling data source control the transmit signaling control register (tscr) of each channel selects source of signaling data to be insert- ed into the outgoing ds1 frame and enables robbed-bit signaling. as we mentioned before, the signaling data can be inserted from transmit signaling control registers (tscr) of each timeslot, from the txsig_n input pin or from the txser_n input pin. the transmit signaling data source select [1:0] bits of the transmit signaling control register (tscr) deter- mines from which sources the signaling data is inserted from. the table below shows configurations of the transmit signaling data source select [1:0] bits of the transmit signaling control register (tscr). transmit interface control register (ticr)(address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 4transmit fractional ds1 r/w this read/write bit-field permits the user to determine which one of the two functions the multiplexed i/o pin of txtsb[0]_n/txsig_n is spotting. 0 - this pin is configured as txtsb[0]_n pin, it outputs bit 0 of the timeslot num- ber of the ds1 pcm data that is transmitting. 1 - this pin is configured as txsig_n pin, it acts as an input source for the signal- ing bits to be transmitted in the outbound ds1 frames transmit signaling control register (tscr) (address = 0xn340h - 0xn357h) b it n umber b it n ame b it t ype b it d escription 1-0 transmit signaling source select r/w 00 - no signaling data is inserted into the input ds1 pcm data by the framer. however, the user can embed signaling data into ds1 pcm data before routing the pcm data into the framer. 01 - signaling data is inserted into the input ds1 pcm data from tscr register of each timeslot. 10 - signaling data is inserted into the input ds1 pcm data from the txsig_n input pin. 11 - no signaling data is inserted into the input ds1 pcm data by the framer. however, the user can embed signaling data into ds1 pcm data before routing the pcm data into the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 296 the robbed-bit signaling enable bit of the transmit signaling control register (tscr) determines whether robbed-bit signaling is available. the table below shows configurations of the robbed-bit signaling enable bit of the transmit signaling control register (tscr). 5.3.11 how to configure the XRT86L34 framer to generate and transmit alarms and error indica- tions to remote terminal the XRT86L34 t1/j1/e1 octal framer can be configured to monitor quality of received ds1 frames. it can generate error indications if the local receive framer has received error frames from the remote terminal. if cor- responding interrupt is enabled, the local microprocessor operation is interrupted by these error conditions. upon microprocessor interruption, the user can intervene by looking into the error conditions. at the same time, the user can configure the XRT86L34 framer to transmit alarms and error indications to re- mote terminal. different alarms and error indications will be transmitted depending on the error condition. the section below gives a brief discussion of the error conditions and appropriate alarms that should be generated and transmitted by the XRT86L34 framer. 5.3.12 brief discussion of alarms and error conditions as defined in ansi t1.231 specification, alarm conditions are created from defects. defects are momentary impairments present on the ds1 trunk. if a defect is present for a sufficient amount of time (called the integra- tion time), then the defect becomes an alarm. once an alarm is declared, the alarm is present until after the de- fect clears for a sufficient period of time. the time it takes to clear an alarm is called the de-integration time. alarms are used to detect and warn maintenance personnel of problems on the ds1 trunk. there are three types of alarms: ? red alarm or service alarm indication (sai) signal ? blue alarm or alarm indication signal (ais) ? yellow alarm or remote alarm indication (rai) signal to explain the error conditions and generation of different alarms, let us create a simple ds1 system model. in this model, a ds1 signal is sourced from the central office (co) through a repeater to the customer premises transmit signaling control register (tscr) (address = 0xn340h - 0xn357h) b it n umber b it n ame b it t ype b it d escription 1-0 robbed-bit signaling enable r/w 0 - robbed-bit signaling is disabled. no signaling data will be inserted into the input pcm data no matter what the setting of the transmit signaling source select [1:0] bits is. 1 - signaling data is enabled and inserted into the input ds1 pcm data according to setting of the transmit signaling source select [1:0] bits.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 297 equipment (cpe). at the same time, a ds1 signal is routed from the cpe to the repeater and back to the cen- tral office. figure 68 below shows the simple ds1 system model. when the e1 system runs normally, that is, when there is no loss of signal (los) or loss of frame (lof) de- tected in the line, no alarm will be generated. sometimes, intermittent outburst of electrical noises on the line might result in bipolar violation or bit errors in the incoming signals, but these errors in general will not trigger the equipment to generate alarms. they will at most trigger the framer to generate interrupts which would cause the local microprocessor to create performance reports of the line. now, consider a case in which the e1 line from the repeater to cpe is broken or interrupted, resulting in com- pletely loss of incoming data or severely impaired signal quality. upon detection of loss of signal (los) or loss of frame (lof) condition, the cpe will generate an internal red alarm, also known as the service alarm indication. this alarm will normally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. when the cpe is in the red alarm state, it will transmit the yellow alarm to the repeater indicating the loss of an incoming signal or loss of frame synchronization. this yellow alarm informs the repeater that there is a f igure 68. s imple d iagram of ds1 s ystem m odel ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe simple ds1 system model
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 298 problem further down the line and its transmission is not being received at the cpe. the figure below illus- trates the scenario in which the e1 connection from the repeater to cpe is broken. the repeater, upon detection of yellow alarm originated from the cpe, will transmit a blue alarm, also known as alarm indication signal (ais) to the co. blue alarm is an all ones pattern indicating that the equipment is functioning but unable to offer service due to failures originated from remote side. it is sent such that the equip- ment downstream will not lose clock synchronization even though no meaningful data is received. the figure f igure 69. g eneration of y ellow a larm by the cpe upon detection of line failure ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe the ds1 line is broken cpe declares red alarm internally yellow alarm
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 299 below illustrates this scenario in which the repeater is sending an ais to co upon detection of yellow alarm originated from the cpe. now let us consider another scenario in which the ds1 line between co and the repeater is broken. again, upon detection of loss of signal (los) or loss of frame (lof) condition, the repeater will generate an inter- nal red alarm. this alarm will normally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. the repeater will also send an all ones ais pattern downstream to the cpe. the cpe uses the ais signal to recover received clock and remain in synchronization with the system. upon detecting the incoming ais signal, the cpe will generate a yellow alarm to the repeater to indicate the loss of incoming signal. the figure below f igure 70. g eneration of ais by the r epeater upon detection of y ellow a larm originated by the cpe ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe the ds1 line is broken cpe declares red alarm internally yellow alarm repeater detects yellow alarm and generate ais to co ais
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 300 illustrates this scenario in which the repeater is sending an ais to the cpe and the cpe is sending a yellow alarm back to the repeater. 5.3.13 how to configure the framer to transmit ais as we discussed in the previous section, alarm indication signal (ais) or blue alarm is transmitted by the in- termediate node to indicate that the equipment is still functioning but unable to offer services. it is an all ones (except for framing bits) pattern which can be used by the equipment further down the line to maintain clock re- covery and timing synchronization. the XRT86L34 framer can generate two types of ais: ? framed ais ? unframed ais unframed ais is an all ones pattern. if unframed ais is sent, the equipment further down the line will be able to maintain timing synchronization and be able to recover clock from the received ais signal. however, due to the lack of framing bits, the equipment farther down the line will not be able to maintain frame synchronization and will declare loss of frame (lof). on the other hand, the payload portion of a framed ais pattern is all ones. however, a framed ais pattern still has correct framing bits. therefore, the equipment further down the line can still maintain frame synchroniza- tion as well as timing synchronization. in this case, no lof or red alarm will be declared. f igure 71. g eneration of y ellow a larm by the cpe upon detection of ais originated by the r epeater ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe the ds1 line is broken repeater declares red alarm internally yellow alarm repeater detects yellow alarm and generate ais to co ais
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 301 the transmit alarm indication signal select [1:0] bits of the alarm generation register (agr) enable the two types of ais transmission that are supported by the XRT86L34 framer. the table below shows configurations of the transmit alarm indication signal select [1:0] bits of the alarm generation register (agr). 5.3.14 how to configure the framer to generate red alarm upon detection of loss of signal (los) or loss of frame (lof) condition, the repeater will generate an inter- nal red alarm when enabled. this alarm will normally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. the loss of frame declaration enable bit of the alarm generation register (agr) enable the generation of red alarm. the table below shows configurations of the of frame declaration enable bit of the alarm genera- tion register (agr). 5.3.15 how to configure the framer to transmit yellow alarm upon detection of loss of signal (los) or loss of frame (lof) condition, the receiver will transmit the yellow alarm back to the source indicating the loss of an incoming signal. this yellow alarm informs the source that there is a problem further down the line and its transmission is not being received at the destination. the XRT86L34 framer supports transmission of yellow alarm when running at the following framing formats: ? sf mode ? esf mode ? n mode ? t1dm mode yellow alarm is transmitted in different forms for various framing formats. the yellow alarm generation select [1:0] bits of the alarm generation register (agr) enable transmission of different types of yellow alarm that are supported by the XRT86L34 framer. 5.3.15.1 transmit yellow alarm in sf mode alarm generation register (agr)(address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 3-2 transmit ais select r/w these read/write bit-fields allows the user to choose which one of the two ais pattern supported by the XRT86L34 framer will be transmitted. 00 - no ais alarm is generated. 01 - enable unframed ais alarm of all ones pattern. 10 - enable framed ais alarm of all ones pattern except for framing bits. 11 - no ais alarm is generated. alarm generation register (agr)(address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 6 loss of frame dec- laration enable r/w this read/write bit-field permits the framer to declare red alarm in case of loss of frame alignment (lof). when receiver module of the framer detects loss of frame alignment in the incoming data stream, it will generate a red alarm. the framer will also generate an rxlofs interrupt to notify the microprocessor that an lof condition is occurred. a yellow alarm is then returned to the remote transmitter to report that the local receiver detects lof. 0 - red alarm declaration is disabled. 1 - red alarm declaration is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 302 in sf mode, the XRT86L34 supports transmission of yellow alarm in two ways. when the yellow alarm gener- ation select [1:0] bits of the alarm generation register are set to 01 or 11, the second msb of all ds0 chan- nels is transmitted as zero. this is yellow alarm for ds1 standard. when the yellow alarm generation select [1:0] bits of the alarm generation register are set to 10, the fram- ing bit of frame 12 is transmitted as one. this is yellow alarm for j1 standard. 5.3.15.2 transmit yellow alarm in esf mode in esf mode, the XRT86L34 transmits yellow alarm on the 4kbit/s data link channel. the facility data link bits are sent in the pattern of eight ones followed by eight zeros. the number of repetitions of this pattern de- pends on the duration of yellow alarm generation select [1:0] bits of the alarm generation register. when these select bits are set to 01 or 11, the following scenario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required to trans- mit 255 patterns on the 4kbit/s data link, the alarm is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transmit 255 patterns on the 4kbit/s data link, the alarm continues until bit 0 goes low. 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the pattern counter. the framer will send another 255 patterns of the yellow alarm. when these select bits are set to 10, bit 1 of the yellow alarm generation select forms a pulse that controls the duration of yellow alarm transmission. the alarm continues until bit 1 goes low. when these select bits are set to 01, the following scenario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required to trans- mit 255 patterns on the 4kbit/s data link, the alarm is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transmit 255 patterns on the 4kbit/s data link, the alarm continues until bit 0 goes low. 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the pattern counter. the framer will send another 255 patterns of the yellow alarm. 5.3.15.3 transmit yellow alarm in n mode in n mode, when the yellow alarm generation select [1:0] bits of the alarm generation register are set to 01, 10 or 11, the second msb of all ds0 channels is transmitted as zero. 5.3.15.4 transmit yellow alarm in t1dm mode in t1dm mode, when the yellow alarm generation select [1:0] bits of the alarm generation register are set to 01, 10 or 11, the yellow alarm bit (the third lsb of timeslot 23) is set to zero.the table below shows configura- tions of the yellow alarm generation select [1:0] bits of the alarm generation register (agr).
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 303 ) alarm generation register (agr)(address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 5-4 yellow alarm generation select r/w 00 - transmission of yellow alarm is disabled. 01 - the framer transmits yellow alarm by converting the second msb of all out- going twenty-four ds0 channel into zero. 10 - the framer transmits yellow alarm by sending the super-frame alignment bit (fs) of frame 12 as one. 11 - the framer transmits yellow alarm by converting the second msb of all out- going twenty-four ds0 channel into zero. n mode: 00 - transmission of yellow alarm is disabled. 01, 10 or 11 - the framer transmits yellow alarm by converting the second msb of all outgoing twenty-four ds0 channel into zero. esf mode: when the framer is in esf mode, it transmits yellow alarm pattern of eight ones followed by eight zeros (1111_1111_0000_0000) through the 4kbit/s data link bits. 00 - transmission of yellow alarm is disabled. 01 - the following scenario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required to transmit 255 patterns on the 4kbit/s data link, the alarm is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transmit 255 patterns on the 4kbit/s data link, the alarm continues until bit 0 goes low. 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the pattern counter. the framer will send another 255 patterns of the yellow alarm. 10 - bit 1 of the yellow alarm generation select forms a pulse that controls the duration of yellow alarm transmission. the alarm continues until bit 1 goes low. 11 - the following scenario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required to transmit 255 patterns on the 4kbit/s data link, the alarm is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transmit 255 patterns on the 4kbit/s data link, the alarm continues until bit 0 goes low. 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the pattern counter. the framer will send another 255 patterns of the yellow alarm. t1dm mode: 00 - transmission of yellow alarm is disabled. 01, 10 or 11 - the framer transmits yellow alarm by setting the yellow alarm bit (y-bit) to zero.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 304 6.0 liu transmit path 6.1 t ransmit d iagnostic f eatures in addition to taos, the XRT86L34 offers multiple diagnostic features for analyzing network integrity such as ataos, network loop code generation, and qrss on a per channel basis by programming the appropriate registers. these diagnostic features take priority over the digital data provided by the framer block. the transmitters will send the diagnostic code to the line and will be maintained in the digital loopback if selected. 6.1.1 taos (transmit all ones) the XRT86L34 has the ability to transmit all ones on a per channel basis by programming the appropriate channel register. this function takes priority over the digital data provided by the framer block. for example: if a fixed "0011" pattern is provided by the framer block and taos is enabled, the transmitter will output all ones. figure 72 is a diagram showing the all ones signal at ttip and tring. f igure 72. taos (t ransmit a ll o nes ) taos 111
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 305 6.1.2 ataos (automatic transmit all ones) if ataos is selected by programming the appropriate global register, an ami all ones signal will be transmitted for each channel that experiences an rlos condition. if rlos does not occur, the ataos will remain inactive until an rlos on a given channel occurs. a simplified block diagram of the ataos function is shown in figure 73. f igure 73. s implified b lock d iagram of the ataos f unction 6.1.3 network loop up code by setting the liu to generate a nluc, the transmitters will send out a repeating "00001" pattern. the output waveform is shown in figure 74. f igure 74. n etwork l oop u p c ode g eneration 6.1.4 network loop down code by setting the liu to generate a nldc, the transmitters will send out a repeating "001" pattern. the output waveform is shown in figure 75. f igure 75. n etwork l oop d own c ode g eneration rlos ataos taos ttip tring tx network loop-up code 1 1 0 0 0 0 0 0001 network loop-down code 1111 0 000000
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 306 6.1.5 qrss generation the XRT86L34 can transmit a qrss random sequence to a remote location from ttip/tring. the polynomi- al is shown in table 174. 6.2 t1 l ong h aul l ine b uild o ut (lbo) the long haul transmitter output pulses are generated using a 7-bit internal dac (6-bits plus the msb sign bit). the line build out can be set to -7.5db, -15db, or -22db cable attenuation by programming the appropriate channel register. the long haul lbo consist of 32 discrete time segments extending over four consecutive pe- riods of tclk. as the lbo attenuation is increased, the pulse amplitude is reduced so that the waveform com- plies with ansi t1.403 specifications. a long haul pulse with -7.5db attenuation is shown in figure 76, a pulse with -15db attenuation is shown in figure 77, and a pulse with -22.5db attenuation is shown in figure 78. f igure 76. l ong h aul l ine b uild o ut with -7.5 d b a ttenuation f igure 77. l ong h aul l ine b uild o ut with -15 d b a ttenuation t able 174: r andom b it s equence p olynomials r andom p attern t1 e1 qrss/prbs 2 20 - 1 2 15 - 1
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 307 f igure 78. l ong h aul l ine b uild o ut with -22.5 d b a ttenuation 6.3 t1 s hort h aul l ine b uild o ut (lbo) the short haul transmitter output pulses are generated using a 7-bit internal dac (6-bit plus the msb sign bit). the line build out can be set to interface to five different ranges of cable attenuation by programming the ap- propriate channel register. the pulse shape is divided into eight discrete time segments which are set to fixed values to comply with the pulse template. to program the eight segments individually to optimize a special line build out, see the arbitrary pulse section of this datasheet. the short haul lbo settings are shown in table 175 6.3.1 arbitrary pulse generator in t1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. each segment is set by a 7-bit binary word by programming the appropriate channel register. this allows the system design- er to set the overshoot, amplitude, and undershoot for a unique line build out. the msb (bit 7) is a sign-bit. if the sign-bit is set to "0", the segment will move in a positive direction relative to a flat line (zero) condition. if this sign-bit is set to "1", the segment will move in a negative direction relative to a flat line condition. the res- olution of the dac is typically 60mv per lsb. thus, writing 7-bit = 1111111 will clamp the output at either volt- age rail corresponding to a maximum amplitude. a pulse with numbered segments is shown in figure 79. t able 175: s hort h aul l ine b uild o ut lbo setting eqc[4:0] r ange of c able a ttenuation 08h (01000) 0 - 133 feet 09h (01001) 133 - 266 feet 0ah (01010) 266 - 399 feet 0bh (01011) 399 - 533 feet 0ch (01100) 533 - 655 feet
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 308 f igure 79. a rbitrary p ulse s egment a ssignment n ote : by default, the arbitrary segments are programmed to 0x00h. the transmitter outputs will result in an all zero pat- tern to the line interface. 6.3.2 dmo (digital monitor output) the driver monitor circuit is used to detect transmit driver failures by monitoring the activities at ttip/tring outputs. driver failure may be caused by a short circuit in the primary transformer or system problems at the transmit inputs. if the transmitter of a channel has no output for more than 128 clock cycles, dmo goes "high" until a valid transmit pulse is detected. if the dmo interrupt is enabled, the change in status of dmo will cause the interrupt pin to go "low". once the status register is read, the interrupt pin will return "high" and the status register will be reset (rur). 6.3.3 transmit jitter attenuator the transmit path has a dedicated jitter attenuator to reduce phase and frequency jitter in the transmit clock. the jitter attenuator uses a data fifo (first in first out) with a programmable depth of 32-bit or 64-bit. when the read and write pointers of the fifo are within 2-bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. when this con- dition occurs, the jitter attenuator will not attenuate input jitter until the read/write pointers position is outside the 2-bit window. in t1 mode, the bandwidth of the ja is always set to 3hz. in e1 mode, the bandwidth is pro- grammable to either 10hz or 1.5hz (1.5hz automatically selects the 64-bit fifo depth). the ja has a clock delay equal to ? of the fifo bit depth. n ote : the receive path has a dedicated jtter attenuator. see the receive path line interface section. 1 2 3 4 5 6 7 8 segment register 1 0x0fn8 2 0x0fn9 3 0x0fna 4 0x0fnb 5 0x0fnc 6 0x0fnd 7 0x0fne 8 0x0fnf
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 309 6.4 l ine t ermination (ttip/tring) the output stage of the transmit path generates standard return-to-zero (rz) signals to the line interface for t1/e1/j1 twisted pair or e1 coaxial cable. the physical interface is optimized by placing the terminating im- pedance inside the liu. this allows one bill of materials for all modes of operation reducing the number of ex- ternal components necessary in system design. the transmitter outputs only require one dc blocking capaci- tor of 0.68 m f. for redundancy applications (or simply to tri-state the transmitters), set txtsel to a "1" in the appropriate channel register. a typical transmit interface is shown in figure 80. f igure 80. t ypical c onnection d iagram u sing i nternal t ermination t tip t ring XRT86L34 liu 1:2 internal impedance line interface t1/e1/j1 c=0.68uf one bill of materials transmitter output
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 310
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 311 7.0 the e1 receive section 7.1 t he r eceive p ayload d ata o utput i nterface b lock 7.1.1 description of the receive payload data output interface block each of the four framers within the XRT86L34 device includes a receive payload data output interface block. the function of the block is to provide an interface to the terminal equipment (for example, a central office or switching equipment) that has data to receive from a "far end" terminal over an ds1 or e1 transport medium. the payload data output interface module (also known as the back-plane interface module) supports payload data to be taken from or presented to the system. in e1 mode, supported data rates are 1.544mbit/s, mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 12.352mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. in e1 mode, supported data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the receive payload data output interface block supplies or accepts the following signals to the terminal equipment circuitry: ? receive serial data input (rxser_n) ? receive serial clock (rxserclk_n) ? receive single-frame synchronization signal (rxsync_n) ? receive multi-frame synchronization signal (rxmsync_n) ? receive time-slot indicator clock (rxtsclk_n) ? receive time-slot indication bits (rxtsb[4:0]_n) the receive serial data is an output pin carrying payload, signaling and sometimes data link data supplied by XRT86L34 device to the local terminal equipment. the receive serial clock is an input or output signal used by the receive payload data input interface block to send out serial data to the local terminal equipment. the receive clock inversion bit of the receive inter- face control register (ticr) determines at which edge of the receive serial clock would data transition on the receive serial data pin occur. the table below shows configurations of the receive clock inversion bit of the receive interface control reg- ister (ricr). throughout the discussion of this datasheet, we assume that serial data transition happens on rising edge of the receive serial clock unless stated otherwise. the receive single-frame synchronization signal is either input or output. when configure as input, it indicates beginning of an e1 frame. when configure as output, it indicates end of an e1 frame. the receive multi-frame synchronization signal is an output pin from XRT86L34 indicating end of an e1 multi- frame. by connecting these signals with the local terminal equipment, the receive payload data output interface routes received payload data from the receive framer module to the local terminal equipment. 7.1.2 brief discussion of the receive payload data output interface block operating at xrt84v24 compatible 2.048mbit/s mode the incoming receive payload data is taken into the framer from the liu interface using the recovered re- ceive line clock. the payload data is then routed through the receive farmer module and presented to the receive payload data output interface through the receive serial data output pin (rxser_n). this data is then clocked out using the receive serial clock (rxserclk_n). receive interface control register (ricr) (address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 3 receive clock inversion r/w 0 - serial data transition happens on rising edge of the receive serial clock. 1 - serial data transition happens on falling edge of the receive serial clock.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 312 there is a two-frame (512 bits) elastic buffer between the receive framer module and the receive payload data output interface. this buffer can be enabled or disabled via programming the slip buffer enable [1:0] bits in slip buffer control register (sbcr). the following table shows configurations of the slip buffer enable [1:0] bits in slip buffer control register. if the slip buffer is not in bypass mode, then the user has the option of either providing the receive single- frame synchronization pulse or getting the receive single-frame synchronization pulse on frame boundary at the rxsync_n pin. the slip buffer receive synchronization direction bit of the slip buffer control register (sbcr) determines whether the receive single-frame synchronization signal is input or output. the table be- low demonstrates settings of the slip buffer receive synchronization direction bit of the slip buffer control register. if the slip buffer is in bypass mode, the receive payload data is routed to the receive payload data output interface from the receive framer module directly. the recovered line clock is used to carry the receive payload data all the way from the liu interface, to the receive framer module and eventually output through the receive serial data output pin. the receive serial clock signal is therefore an output using the recovered receive line clock as timing source. the receive single-frame synchronization signal is also output in slip buffer bypass mode. if the slip buffer is enabled, the receive payload data is latched into the elastic store using the recovered receive line clock. the local terminal equipment supplies a free-running 2.048mhz clock to the receive se- rial clock pin to latch the receive payload data out from the elastic store. since the recovered receive line clock and the receive serial clock are coming from different timing sources, the slip buffer will gradually fill or empty. if the elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties and a read oc- curs, then a full frame of data will be repeated and a status bit will be updated. if the buffer fills and a write comes, then a full frame of data will be deleted and another status bit will be set. a detailed description of the elastic buffer can be found in later sections. in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. slip buffer control register (sbcr)(address = 0xn116h) b it n umber b it n ame b it t ype b it d escription 1-0 slip buffer enable r/w 00 - slip buffer is bypassed. the receive payload data is passing from the receive framer module to the receive payload data output interface directly without routing through the slip buffer. the receive serial clock signal (rxserclk_n) is an output. 01 - the elastic store (slip buffer) is enabled. the receive payload data is passing from the receive framer module through the slip buffer to the receive payload data output interface. the receive serial clock signal (rxserclk_n) is an input. 10 - the slip buffer acts as a fifo. the fifo latency register (flr) determines the data latency. the receive payload data is passing from the receive framer module through the fifo to the receive payload data output interface. the receive serial clock signal (rxserclk_n) is an input. 11 - slip buffer is bypassed. the receive payload data is passing from the receive framer module to the receive payload data output interface directly without routing through the slip buffer. the receive serial clock signal (rxserclk_n) is an output. slip buffer control register (sbcr)(address = 0xn116h) b it n umber b it n ame b it t ype b it d escription 2 slip buffer receive synchronization direction r/w 0 - the receive single-frame synchronization signal (rxsync_n) is an output if the slip buffer is not in bypass mode. 1 - the receive single-frame synchronization signal (rxsync_n) is an input if the slip buffer is not in bypass mode.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 313 if the slip buffer is put into a fifo mode, it is acting like a standard first-in-first-out storage. a fixed read and write latency is maintained in a programmable fashion controlled by the fifo latency register (fifolr). the local terminal equipment supplies a 2.048mhz clock to the receive serial clock pin to latch the receive payload data out from the fifo. however, it is the responsibility of the user to phase lock the in- put receive serial clock to the recovered receive line clock to avoid either over-run or under-run of the fifo. in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. the following table summaries the input or output nature of the receive serial clock and receive single- frame synchronization signals for different slip buffer settings. the receive time-slot indication bits (rxtsb[4:0]_n) are multiplexed i/o pins. the functionality of these pins is governed by the value of receive fractional e1 output enable bit of the receive interface control register (ricr). the following table illustrates the configurations of the receive fractional e1 input enable bit. when configured to operate in normal condition (that is, when the receive fractional e1 input enable bit is equal to zero), these bits reflect the five-bit binary value of the time slot number (0-31) being outputted and processed by the receive payload data output interface block of the framer. rxtsb[4] represents the msb of the binary value and rxtsb[0] represents the lsb. when the receive fractional e1 output enable bit is equal to one, the rxtsb[0]_n bit becomes the receive fractional e1 output signal (rxfrtd_n). this output pin carries fractional e1 output data extracted by the framer from the incoming e1 data stream. the fractional e1 output interface allows certain time-slots of e1 data to be routed to destinations other than the local terminal equipment. function of the fractional e1 output signal will be discussed in details in later sections. r eceive t iming s ource r x s er c lk _ n r x s ync _ n slip buffer synchronization direction bit = 0 slip buffer synchronization direction bit = 1 slip buffer bypassed output output output slip buffer enabled input output input slip buffer acts as fifo input output input receive interface control register (ricr) (address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 4 receive fractional e1 output enable r/w 0 - the receive time-slot indication bits (rxtsb[4:0] are outputting five-bit binary val- ues of time-slot number (0-31) being accepted and processed by the receive payload data output interface block of the framer. the receive time-slot indicator clock signal (rxtsclk_n) is a 256khz clock that pulses high for one e1 bit period whenever the receive payload data output interface block is accepting the lsb of each of the twenty-four time slots. 1 - the rxtsb[0]_n bit becomes the receive fractional e1 output signal (rxfrtd_n) which carries fractional e1 payload data from the framer. the rxtsb[1]_n bit becomes the receive signaling data output signal (rxsig_n) which is used to carry robbed-bit signaling data extracted from the inbound e1 frame. the rxtsb[2]_n bit serially outputs all five-bit binary values of the time slot number (0-31) being accepted and processed by the receive payload data output interface block of the framer. the rxtsclk_n will output gaped fractional e1 clock that can be used by terminal equipment to latch in fractional e1 payload data at rising edge of the clock. or, the rxtsclk_n pin will be a clock enable signal to receive fractional e1 output signal (rxfrtd_n) when the un-gaped receive serail output clock (rxserclk_n) is used to latch in fractional e1 payload data into the terminal equipment.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 314 when the receive fractional e1 output enable bit is equal to one, the rxtsb[1]_n bit becomes the receive signaling data output signal (rxsig_n). these output pins can be used to carry robbed-bit signaling data ex- tracted from the inbound e1 frame. function of the receive signaling data output signal will be discussed in details in later sections. when the receive fractional e1 output enable bit is equal to one, the rxtsb[2]_n bit serially outputs all five- bit binary values of the time slot number (0-31) being outputted and processed by the receive payload data output interface block of the framer. msb of the binary value is presented first and the lsb is presented last. the rxtsb[3]_n and rxtsb[4}_n pins are not multiplexed. the table below shows functionality of the rxtsb[2:0] bits when the receive fractional e1 output bit is set to different values. the receive time-slot indicator clock signal (rxtsclk_n) is a multi-function output pin. when configured to operate in normal condition (that is, when the receive fractional e1 input enable bit is equal to zero), the rxtsclk_n is a 256khz clock that pulses high for one e1 bit period whenever the receive payload data output interface block is outputting the lsb of each of the twenty-four time slots. the local terminal equipment should use this clock signal to sample the rxtsb[0] through rxtsb[4] bits and identify the time-slot being pro- cessed via the receive section of the framer. when the receive fractional e1 output enable bit is equal to one, the rxtsclk_n will output gaped fractional e1 clock whenever fractional e1 payload data is present at the rxfrtd_n pin. the local terminal equipment can latch in fractional e1 payload data at falling edge of the clock. otherwise, this pin will be a clock enable signal to receive fractional e1 output signal (rxfrtd_n) if the framer is configured accordingly. in this way, fractional e1 payload data is clocked into the terminal equipment using un-gaped receive serial output clock (rxserclk_n). a detailed discussion of the fractional e1 payload data output interface can be found in later sections. a detailed discussion of how to connect the receive payload data output interface block to the local terminal equipment with slip buffer enabled or disabled can be found in the later sections. 7.1.2.1 connect the receive payload data output interface block to the local terminal equipment if the slip buffer is bypassed by setting the slip buffer enable [1:0] bits of the slip buffer control register to 00 or 11, the receive framer module routes the receive payload data directly to the receive payload data output interface without pass- ing through the elastic buffer. the XRT86L34 device uses the recovered receive line clock internally to car- ry the receive payload data directly across the whole chip. the recovered receive line clock is essentially become timing source of the receive serial clock output. if the slip buffer is bypassed, the receive single-frame synchronization signal is automatically configured to be output signals. it should pulse high for one e1 bit period (488ns) at the last bit position of each e1 frame. by triggering on the high pulse on the receive single-frame synchronization signal, the terminal equipment can identify the end of an e1 frame and should prepare to accept payload data of the next e1 frame from the framer. the receive multi-frame synchronization signal should pulse high for one e1 bit period (488ns) at the last bit position of an e1 multi-frame. by triggering on the high pulse on the receive multi-frame synchronization sig- nal, the framer can identify the end of an e1 super-frame and should prepare to accept payload data of the next e1 super-frame from the framer. r eceive f ractional e1 o utput b it = 0 r eceive f ractional e1 o utput b it = 1 rxtsb[0] output rxfrtd output rxtsb[1] output rxsig output rxtsb[2] output rxts output
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 315 see figure 81 for how to connect the receive payload data output interface block to the local terminal equip- ment when the slip buffer is bypassed and the recovered receive line clock is timing source of the receive section. the following figure 82 shows waveforms of the signals (rxserclk_n, rxser_n, rxsync_n, rxtsclk_n and rxtsb[4:0]_n) which connecting the receive payload data output interface block to the local terminal equip- f igure 81. i nterfacing XRT86L34 to local terminal equipment with slip buffer bypassed and recov - ered receive line clock as receive timing source rxserclk_0 rxser_0 rxmsync_0 rxsync_0 rxtsclk_0 rxtsb[4:0]_0 rxserclk_3 rxser_3 rxmsync_3 rxsync_3 rxtsclk_3 rxtsb[4:0]_3 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxlineclk_0 rxlineclk_7
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 316 ment when the slip buffer is bypassed and the recovered receive line clock is timing source of the receive section. 7.1.2.2 connect the receive payload data output interface block to the local terminal equipment if the slip buffer is enabled by setting the slip buffer enable [1:0] bits of the slip buffer control register to 01, the framer includes the two- frame elastic buffer into its data path. the receive framer module routes the receive payload data to the elastic buffer first. the receive payload data is then presented to the receive payload data output interface. the XRT86L34 device uses the recovered receive line clock internally to clock in the receive payload data into the elastic buffer. the terminal equipment should provide a 2.048mhz clock to the receive serial clock input pin to latch data out from the elastic buffer. the recovered receive line clock and the receive serial clock are generated from two different timing sources. that is, the recovered receive line clock is originating from a remote site while receive serial clock generating by a local oscillator. any mismatch in frequencies of these two clocks will result in the slip buffer to gradually fill or deplete. overtime, the elastic buffer either fills or empties completely. once that happened, a controlled slip by the XRT86L34 device will occur. the receive slip buffer slip bit of the slip buffer status register (sbsr) is set to 1. if the buffer empties and a read occurs, then a full frame of data will be repeated and the receive slip buffer empty bit of the slip buffer status register (sbsr) will be forced high. if the buffer fills and a write comes, then a full frame of data will be deleted and the receive slip buffer full bit of the slip buffer status register (sbsr) will be forced high. f igure 82. w aveforms of the s ignals c onnecting the r eceive p ayload d ata o utput i nterface block to the local t erminal e quipment when the s lip b uffer is b ypassed and the r ecovered l ine c lock is the t iming s ource of the r eceive s ection c rxserclk rxser rxsync(input) rxsync(output) rxchclk rxchn[4:0] rxchn[0]/rxsig rxchclk rxchn[2]/rxchn rxchn[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 16 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #16
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 317 the following table demonstrates settings of the receive slip buffer slip bit, receive slip buffer empty bit and receive slip buffer full bit of the slip buffer status register. in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. when the slip buffer receive synchronization direction bit is set to 0, the receive single-frame synchronization signal (rxsync_n) is an. when the slip buffer receive synchronization direction bit is set to 1,the receive single- frame synchronization signal (rxsync_n) is an input. if the receive single-frame synchronization signal is an output, it should pulse high for one e1 bit period (488ns) at the last bit position of each e1 frame. by triggering on the high pulse on the receive single-frame synchronization signal, the terminal equipment can identify the end of an e1 frame and should prepare to ac- cept payload data of the next e1 frame from the framer. if the receive single-frame synchronization signal is an input, it should pulse high for one e1 bit period (488ns) at the first bit position (f-bit) of each e1 frame. by sampling the high pulse of the receive single- frame synchronization signal, the framer should identity the beginning of an e1 frame and can send out data in a synchronized way. it is the responsibility of the local terminal equipment to align the start of an e1 frame with the receive single-frame synchronization pulse. the receive multi-frame synchronization signal should pulse high for one e1 bit period (488ns) at the last bit position of frame number one of an e1 multi-frame. by triggering on the high pulse on the receive multi- frame synchronization signal, the framer can identify the end of an e1 super-frame and should prepare to ac- cept payload data of the next e1 super-frame from the framer. slip buffer status register (sbsr)(address = 0xnb08h) b it n umber b it n ame b it t ype b it d escription 2 receive slip buffer full r/w 0 - the receive slip buffer is not full. 1 - the receive slip buffer is full and one frame of data is discarded. 1 receive slip buffer empty r/w 0 - the receive slip buffer is not empty. 1 - the receive slip buffer is empty and one frame of data is repeated. 1 receive slip buffer slip r/w 0 - the receive slip buffer does not slip. 1 - the receive slip buffer slips since either full or emptied.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 318 see figure 83 for how to connect the receive payload data output interface block to the local terminal equip- ment when the slip buffer is enabled. f igure 83. i nterfacing XRT86L34 to local terminal equipment with slip buffer enabled or acts as fifo rxserclk_0 rxser_0 rxmsync_0 rxsync_0 rxtsclk_0 rxtsb[4:0]_0 rxserclk_3 rxser_3 rxmsync_3 rxsync_3 rxtsclk_3 rxtsb[4:0]_3 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 319 the following figure 84 shows waveforms of the signals (rxserclk_n, rxser_n, rxsync_n, rxtsclk_n and rxtsb[4:0]_n) which connecting the receive payload data output interface block to the local terminal equip- ment when the slip buffer is enabled. 7.1.2.3 connect the receive payload data output interface block to the local terminal equipment if the slip buffer is configured as fifo by setting the slip buffer enable [1:0] bits of the slip buffer control register to 10, the framer puts the elastic buffer into fifo mode. receive framer module routes the receive payload data through the first-in-first-out storage to the receive payload data output interface. the XRT86L34 device uses the recovered receive line clock internally to clock in the receive payload data into the fifo. the terminal equipment should pro- vide an external 2.048mhz clock to the receive serial clock input pin to latch data out from the fifo. it is the responsibility of the user to phase lock the input receive serial clock to the recovered receive line clock to avoid either over-run or under-run of the fifo. the latency between writing a bit into the fifo and reading the same bit from it (read and write latency) is actually depth of the fifo, which is maintained in a programmable fashion controlled by the fifo latency register (fifolr). the largest possible depth of the fifo is thirty-two bytes or one e1 frame. the default depth of the fifo when XRT86L34 first powered up is four bytes. the table below shows the fifo latency register. in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. when the slip buffer receive synchronization direction bit is set to 0, the receive single-frame synchronization signal (rxsync_n) is an. when the slip buffer receive synchronization direction bit is set to 1,the receive single- frame synchronization signal (rxsync_n) is an input. f igure 84. w aveforms of the s ignals that c onnect the r eceive p ayload d ata o utput i nterface block to the local t erminal e quipment when the s lip b uffer is e nabled fifo latency register (fifol) (address = 0xn117h) b it n umber b it n ame b it t ype b it d escription 4-0 fifo latency r/w these bits determine depth of the fifo in terms of bytes. the largest possible value is thirty-two bytes or one e1 frame. c rxserclk rxser rxsync(input) rxsync(output) rxchclk rxchn[4:0] rxchn[0]/rxsig rxchclk rxchn[2]/rxchn rxchn[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 16 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #16
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 320 if the receive single-frame synchronization signal is an output, it should pulse high for one e1 bit period (488ns) at the last bit position of each e1 frame. by triggering on the high pulse on the receive single-frame synchronization signal, the terminal equipment can identify the end of an e1 frame and should prepare to ac- cept payload data of the next e1 frame from the framer. if the receive single-frame synchronization signal is an input, it should pulse high for one e1 bit period (488ns) at the first bit position (f-bit) of each e1 frame. by sampling the high pulse of the receive single- frame synchronization signal, the framer should identity the beginning of an e1 frame and can send out data in a synchronized way. it is the responsibility of the local terminal equipment to align the start of an e1 frame with the receive single-frame synchronization pulse. the receive multi-frame synchronization signal should pulse high for one e1 bit period (488ns) at the last bit position of frame number one of an e1 multi-frame. by triggering on the high pulse on the receive multi- frame synchronization signal, the framer can identify the end of an e1 super-frame and should prepare to ac- cept payload data of the next e1 super-frame from the framer. see figure 85 for how to connect the receive payload data output interface block to the local terminal equip- ment when the slip buffer is acted as fifo. f igure 85. i nterfacing XRT86L34 to local terminal equipment with slip buffer enabled or acts as fifo rxserclk_0 rxser_0 rxmsync_0 rxsync_0 rxtsclk_0 rxtsb[4:0]_0 rxserclk_3 rxser_3 rxmsync_3 rxsync_3 rxtsclk_3 rxtsb[4:0]_3 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 321 the following figure 86 shows waveforms of the signals (rxserclk_n, rxser_n, rxsync_n, rxtsclk_n and rxtsb[4:0]_n) which connecting the receive payload data output interface block to the local terminal equip- ment when the slip buffer is acted as fifo. 7.1.3 high speed receive back-plane interface the high-speed back-plane interface supports payload data to be taken from or presented to the local termi- nal equipment at different data rates. in e1 mode, supported high-speed data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the receive multiplex enable bit and the receive interface mode select [1:0] bits of the receive interface control register (ricr) determine the receive back-plane interface data rate. the following table shows configurations of the receive multiplex enable bit and the receive interface mode select [1:0] bits of the receive interface control register (ricr). f igure 86. w aveforms of the s ignals that c onnect the r eceive p ayload d ata o utput i nterface block to the local t erminal e quipment when the s lip b uffer is acted as fifo receive interface control register (ricr) (address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 2 receive multi- plex enable r/w 0 - the receive back-plane interface block is configured to non-channel-multiplexed mode 1 - the receive back-plane interface block is configured to channel-multiplexed mode 1-0 receive interface mode select r/w when combined with the receive multiplex enable bit, these bits determine the receive back-plane interface data rate. c rxserclk rxser rxsync(input) rxsync(output) rxchclk rxchn[4:0] rxchn[0]/rxsig rxchclk rxchn[2]/rxchn rxchn[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 16 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #16
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 322 the table below shows the combinations of receive multiplex enable bit and receive interface mode select [1:0] bits and the resulting receive back-plane interface data rates. when the receive multiplex enable bit is set to zero, the framer is configured in non-channel-multiplexed mode. the possible data rates are xrt84v24 compatible 2.048mbit/s, mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s. in non-channel-multiplexed mode, payload data of each channel are sending out from the re- ceive high-speed back-plane interface separately. each channel uses its own receive serial clock, receive serial data, receive single-frame synchronization signal and receive multi-frame synchronization signal as interface between the framer and the terminal equipment. section 2.1.1.1, 2.1.1.2 and 2.1.1.3 provide details on how to connect the receive payload data interface block with the local terminal equipment when the back- plane interface data rate is 2.048mbit/s. when the back-plane interface data rate is mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s, the receive serial clock, receive serial data and receive single-frame synchronization are all configured as inputs. the re- ceive multi-frame synchronization signal is still output. the receive serial clock is configured as an input tim- ing source for the high-speed back-plane interface with frequencies of 2.048 mhz, 4.096 mhz and 8.192 mhz respectively. the table below summaries the clock frequencies of rxserclk_n input when the framer is operating in non- multiplexed high-speed back-plane mode. when the receive multiplex enable bit is set to one, the framer is configured in channel-multiplexed mode. the possible data rates are bit-multiplexed 16.384mbit/s, hmvip 16.384mbit/s and h.100 16.384mbit/s. in channel-multiplexed mode, four channels share the receive serial data, receive single-frame synchroniza- tion signal and receive serial clock of one channel as interface between the framer and the terminal equip- ment. the receive serial clock runs at frequencies of 12.352 mhz or 16.384 mhz. it serves as the primary clock source for the high-speed back-plane interface. payload and signaling data of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. pay- load and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. the re- r eceive m ultiplex e nable b it r eceive i nterface m ode s elect b it 1 r eceive i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate 0 0 0 xrt84v24 compatible 2.048mbit/s 0 0 1 mvip 2.048mbit/s 0 1 0 4.096mbit/s 0 1 1 8.192mbit/s 100 - 1 0 1 bit multiplexed 16.384mbit/s 1 1 0 hmvip 16.384mbit/s 1 1 1 h.100 16.384mbit/s receive multiplex enable bit = 0 r eceive i nterface m ode s elect b it 1 r eceive i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate r x s er c lk 0 0 xrt84v24 compatible 2.048mbit/s 2.048mhz 0 1 mvip 2.048mbit/s 2.048 mhz 1 0 4.096mbit/s 4.096 mhz 1 1 8.192mbit/s 8.192 mhz
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 323 ceive single-frame synchronization signal of channel 0 pulses high at the beginning of the frame with data from channel 0-3 multiplexed together. the receive single-frame synchronization signal of channel 4 pulses high at the beginning of the frame with data from channel 4-7 multiplexed together. the table below summaries the clock frequencies of rxserclk_n input when the framer is operating in multi- plexed high-speed back-plane mode. when the frame is running at high-speed back-plane interface mode other than the 2.048mbit/s data rate, the receive single-frame synchronization signal could pulse high or low indicating boundaries of e1 frames. the receive synchronization pulse low bit of the receive interface control register (ticr) determines whether the receive single-frame synchronization signal is high active or low active. the table below shows configurations of the receive synchronization pulse low bit of the receive interface control register (ricr). throughout the discussion of this datasheet, we assume that the receive single-frame synchronization signal pulses high unless stated otherwise. the following sections discuss details of how to operate the framer in different back-plane interface speed mode and how to connect the receive payload data output interface block to the local terminal equipment. 7.1.3.1 e1 receive input interface - mvip 2.048 mhz when the receive multiplex enable bit is set to zero and the receive interface mode select [1:0] bits are set to 01, the receive back-plane interface of framer is running at a data rate of 2.048mbit/s. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_n at an e1 equivalent data rate of 2.048mbit/s. the local terminal equipment supplies a free-running 2.048mhz clock to the receive serial clock input. the receive high-speed back-plane interface of the framer then sends out serial data at rising receive multiplex enable bit = 1 r eceive i nterface m ode s elect b it 1 r eceive i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate r x s er c lk 00 - - 0 1 bit-multiplexed 16.384mbit/s 16.384 mhz 1 0 hmvip 16.384mbit/s 16.384 mhz 1 1 h.100 16.384mbit/s 16.384 mhz receive interface control register (ricr)(address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 3 receive synchro- nization pulse low r/w 0 - the receive single-frame synchronization signal will pulse high indicating the beginning of an e1 frame when the high-speed back-plane interface is running at a mode other than the 2.048mbit/s. 1 - the receive single-frame synchronization signal will pulse low indicating the beginning of an e1 frame when the high-speed back-plane interface is running at a mode other than the 2.048mbit/s.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 324 edge of the receive serial clock. the local terminal equipment samples the serial data at falling edge of the clock. the receive single-frame synchronization input signal (rxsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse of the receive single-frame synchro- nization signal, the framer can identity the beginning of an e1 frame and start pumping payload data out. see figure 87 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in mvip 2.048mbit/s mode. the timing diagram of input signals to the framer when running at mvip 2.048mbit/s mode is shown in figure 88. 7.1.3.2 e1 receive input interface - 4.096 mhz f igure 87. i nterfacing XRT86L34 to local terminal equipment using mvip 2.048m bit / s data bus f igure 88. t iming d iagram of i nput signals to the f ramer when running at mvip 2.048m bit / s rxserclk_0 (2.048mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxserclk_3 (2.048mhz) rxser_3 rxmsync_3 rxsync_3 rxserclk rxserclk(inv) rxser rxsync(input) rxsync(input) (mvip) rxchn[0]/rxsig rxchn[1]/frrxd rxchclk (rxsyncfrtd=1) rxchclk(inv) rxchclk (rxsyncfrtd=1) timeslot 2 timeslot 3 timeslot 4 timeslot 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d c a b d c a b d c a b d c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 rxchn[2]/rxchn
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 325 (this interface mode is the same as running at 2.048 mhz. the only difference is that the receive serial clock runs two times faster at 4.096 mhz) when the receive multiplex enable bit is set to zero and the receive interface mode select [1:0] bits are set to 10, the receive back-plane interface of framer is running at a clock rate of 4.096mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_n at an e1 equivalent data rate of 2.048mbit/s. the local terminal equipment supplies a free-running 4.096mhz clock to the receive serial clock input. the receive high-speed back-plane interface of the framer then sends out serial data at every other rising edge of the receive serial clock. the local terminal equipment samples the serial data at every other falling edge of the clock. the receive single-frame synchronization input signal (rxsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse of the receive single-frame synchro- nization signal, the framer can identity the beginning of an e1 frame and start pumping payload data out. see figure 89 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in 4.096mbit/s mode. f igure 89. i nterfacing XRT86L34 to local terminal equipment using 4.096m bit / s data bus rxserclk_0 (4.096mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxserclk_3 (4.096mhz) rxser_3 rxmsync_3 rxsync_3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 326 the timing diagram of input signals to the framer when running at 4.096mbit/s mode is shown in figure 90. 7.1.3.3 e1 receive input interface - 8.192 mhz (this interface mode is the same as running at 2.048 mhz. the only difference is that the receive serial clock runs four times faster at 8.192mhz) when the receive multiplex enable bit is set to zero and the receive interface mode select [1:0] bits are set to 11, the receive back-plane interface of framer is running at a clock rate of 8.192mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_n at an e1 equivalent data rate of 2.048mbit/s. the local terminal equipment supplies a free-running 8.192mhz clock to the receive serial clock input. the receive high-speed back-plane interface of the framer then sends out serial data at every other four rising edge of the receive serial clock. the local terminal equipment samples the serial data at ev- ery other four falling edge of the clock. the receive single-frame synchronization input signal (rxsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse of the receive single-frame synchro- nization signal, the framer can identity the beginning of an e1 frame and start pumping payload data out. f igure 90. t iming d iagram of input signals to the framer when running at 4.096m bit / s mode txserclk (2mhz) txserclk (inv) txser txsync(input) txchclk(inv) txchn[0]/txsig txchn[1]/txfrtd 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txserclk (4mhz) don't care don't care
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 327 see figure 91 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in 8.192mbit/s mode. the timing diagram of input signals to the framer when running at 8.192mbit/s mode is shown in figure 92. 7.1.3.4 e1 receive input interface - bit-multiplexed 16.384mbit/s when the receive multiplex enable bit is set to one and the receive interface mode select [1:0] bits are set to 01, the receive back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) f igure 91. i nterfacing XRT86L34 to local terminal equipment using 8.192m bit / s data bus f igure 92. t iming diagram of input signals to the framer when running at 8.192m bit / s mode rxserclk_0 (8.192mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxserclk_3 (8.192mhz) rxser_3 rxmsync_3 rxsync_3 txserclk (2mhz) txserclk (inv) txser txsync(input) txchclk(inv) txchn[0]/txsig txchn[1]/txfrtd 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the txchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txserclk (8mhz) don't care don't care
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 328 ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_0 or rxser_4 pins at 16.384mbit/s. it multiplexes payload and signaling data of every four channels into one data stream. payload and signaling da- ta of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. free-running clocks of 16.384mhz are supplied to the receive serial clock pin of channel 0 and channel 4 of the framer. the receive high-speed back-plane interface of the farmer provides data at rising edge of this re- ceive serial clock. the local terminal equipment then latches incoming serial data at falling edge of the clock. the receive high-speed back-plane interface maps four 2.048mbit/s e1 data streams into this 16.384mbit/s data stream as described below: 1. payload data of four channels are repeated and grouped together in a bit-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of channel 3 is sent last. after the first bits of timeslot 0 of all four channels are sent, it comes the second bit of timeslot 0 of chan- nel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y 2. the receive high-speed back-plane interface also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the receive high-speed back-plane interface is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth pay- load bit of a particular channels is followed by the signaling bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 second octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3 fifth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 329 x y : the xth payload bit of channel y a y : the signaling bit a of channel y 3. after the first octets of all four channels are sent, the receive high-speed back-plane interface will start sending the second octets following the same rules of step 1 and 2. the receive single-frame synchronization signal of channel 0 pulses high for one clock cycle at the first bit position of the data stream with data from channel 0-3 multiplexed together. the receive single-frame syn- chronization signal of channel 4 pulses high for one clock cycle at the first bit position of the data stream with data from channel 4-7 multiplexed together. by sampling the high pulse of the receive single-frame syn- chronization signal, the receive high-speed back-plane interface of the framer can identify the beginning of a multiplexed frame and can start sending payload data of that frame. sixth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 seventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3 eighth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 330 see figure 93 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in bit-multiplexed 16.384mbit/s mode. the input signal timing is shown in figure 94 below when the framer is running at bit-multiplexed 16.384mbit/s mode. 7.1.3.5 e1 receive input interface - hmvip 16.384mbit/s when the receive multiplex enable bit is set to one and the receive interface mode select [1:0] bits are set to 10, the receive back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_0 or rxser_4 pins at 16.384mbit/s. the receive high-speed back-plane interface multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the receive serial data pin f igure 93. i nterfacing XRT86L34 to local terminal equipment using 16.384 m bit / s data bus f igure 94. iming signal when the framer is running at b it -m ultiplexed 16.384m bit / s mode rxserclk_0 (16.384mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0-3 terminal equipment XRT86L34 txserclk (16.384mhz) txserclk (inv) txser txsync(input) 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 56 cycles
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 331 of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. free-running clocks of 16.384mhz are supplied to the receive serial clock pin of channel 0 and channel 4 of the framer. the receive high-speed back-plane interface of the farmer provides data at rising edge of this re- ceive serial clock. the local terminal equipment then latches incoming serial data at falling edge of the clock. the receive high-speed back-plane interface maps four 2.048mbit/s e1 data streams into this 16.384mbit/s data stream as described below: 1. payload data of four channels are repeated and grouped together in a byte-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the terminal equipment will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y 2. the receive high-speed back-plane interface also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the receive high-speed back-plane interface is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth pay- load bit of a particular channels is followed by the signaling bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 third octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 fifth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 seventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 332 the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 3. after the first octets of all four channels are sent, the receive high-speed back-plane interface will start sending the second octets following the same rules of step 1 and 2. the receive single-frame synchronization signal should pulse high for four clock cycles (the last two bit po- sitions of the previous multiplexed frame and the first two bits of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the receive single-frame synchronization signal of channel 0 puls- es high to identify the start of multiplexed data stream of channel 0-3. the receive single-frame synchroni- zation signal of channel 0 pulses high to identify the start of multiplexed data stream of channel 0-3. by sam- pling the high pulse of the receive single-frame synchronization signal, the receive high-speed back-plane interface of the framer can identify the beginning of a multiplexed frame and can start sending payload data of that frame. second octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0 fourth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 sixth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2 eighth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 333 see figure 95 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 96 below when the framer is running at hmvip 16.384mbit/s mode. 7.1.3.6 e1 receive input interface - h.100 16.384mbit/s when the receive multiplex enable bit is set to one and the receive interface mode select [1:0] bits are set to 11, the receive back-plane interface of framer is running at h.100 16.384mbit/s mode. (the hmvip mode and the h.100 mode are essential the same except for the high pulse position of the re- ceive single-frame synchronization signal) the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) f igure 95. i nterfacing XRT86L34 to local terminal equipment using 16.384m bit / s data bus f igure 96. t iming s ignal when the framer is running at hmvip 16.384m bit / s mode rxserclk_0 (16.384mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0-3 terminal equipment XRT86L34 rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig rxsync(input) hmvip, negative sync rxsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 334 the receive back-plane interface is pumping out data through rxser_0 or rxser_4 pins at 16.384mbit/s. the receive high-speed back-plane interface multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. free-running clocks of 16.384mhz are supplied to the receive serial clock pin of channel 0 and channel 4 of the framer. the receive high-speed back-plane interface of the farmer provides data at rising edge of this re- ceive serial clock. the local terminal equipment then latches incoming serial data at falling edge of the clock. the receive high-speed back-plane interface maps four 2.048mbit/s e1 data streams into this 16.384mbit/s data stream as described below: 1. payload data of four channels are repeated and grouped together in a byte-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the receive high-speed back- plane interface will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y 2. the receive high-speed back-plane interface also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 third octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 fifth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 seventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 335 when the receive high-speed back-plane interface is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth pay- load bit of a particular channels is followed by the signaling bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 3. after the first octets of all four channels are sent, the receive high-speed back-plane interface will start sending the second octets following the same rules of step 1 and 2. the receive single-frame synchronization signal should pulse high for two clock cycles (the last bit position of the previous multiplexed frame and the first bit position of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the receive single-frame synchronization signal of channel 0 puls- es high to identify the start of multiplexed data stream of channel 0-3. the receive single-frame synchroni- zation signal of channel 0 pulses high to identify the start of multiplexed data stream of channel 0-3. by sam- pling the high pulse of the receive single-frame synchronization signal, the receive high-speed back-plane interface of the framer can identify the beginning of a multiplexed frame and can start sending payload data of that frame. second octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0 fourth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 sixth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2 eighth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 336 see figure 97 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 98 below when the framer is running at h.100 16.384mbit/s mode. 7.2 e1 r eceive f ramer b lock 7.2.1 how to configure XRT86L34 to operate in e1 mode the XRT86L34 octal t1/e1/j1 framer supports ds1, j1 or e1 framing modes. since j1 standard is very sim- ilar to ds1 standard with a few minor changes, the j1 framing mode is included as a sub-set of the ds1 fram- ing mode. all four framers within the XRT86L34 silicon can be individually configured to support ds1, j1 or e1 framing modes. n ote : if transmitting section of one framer is configured to support either one of the framing modes, the receiving section is automatically configured to support the same framing modes. f igure 97. i nterfacing XRT86L34 to local terminal equipment using 16.384m bit / s data bus f igure 98. t iming s ignal when the framer is running at h.100 16.384m bit / s mode rxserclk_0 (16.384mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0-3 terminal equipment XRT86L34 rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig start of frame x y : x is the bit number and y is the channel number rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync delayer h.100 rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 337 the t1/e1 select bit of the clock select register (csr) controls which framing mode, that is, t1/j1 or e1, supported by the framer. the table below illustrates configurations of the t1/e1 select bit of the clock select register (csr). the purpose of the e1 transmit framer block is to embed and encode user payload data into frames and to route this e1 frame data to the transmit e1 liu interface block. please note that the XRT86L34 has four (4) in- dividual e1 transmit framer blocks. hence, the following description applies to all four of these individual transmit e1 framer blocks. the purpose of the e1 transmit framer block is: ? to encode user data, inputted from the terminal equipment into a standard framing format. ? to provide individual data control and signaling conditioning of each ds0 channel. ? to support the transmission of hdlc messages, from the local transmitting terminal, to the remote receiving terminal. ? to transmit indications that the local receive framer has received error frames from the remote terminal. ? to transmit alarm condition indicators to the remote terminal. the following sections discuss the functionalities of e1 transmit framer block in details. we will also describe how to configure the XRT86L34 to transmit e1 frames according to system requirement of users. 7.2.2 how to configure the framer to receive data in various e1 framing formats the XRT86L34 octal t1/e1/j1 framer is designed to meet the requirement of itu-t recommendation g.704. the e1 framer supports the following: ? frame alignment signal (fas) ? crc-4 multi-frame the itu-t recommendation g.704 also specifies two forms of signaling that can be supported by the e1 transport medium: ? channel associated signaling (cas) ? common channel signaling (ccs) the XRT86L34 framer supports both cas, ccs signaling format together with clear channel without signal- ing. 7.2.3 how to configure the framer to choose fas searching algorithm the XRT86L34 framer can use two algorithms to search for fas pattern and thus declare fas alignment syn- chronization. the fas selection bit of the framing select register (fsr) allows the user to choose which one of the two algorithms for searching fas frame alignment. clock select register (csr)(address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 6 t1/e1 select r/w 0 - the XRT86L34 framer is running in e1 mode. 1 - the XRT86L34 framer is running in t1 mode.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 338 the table below shows configurations of the fas selection bit of the framing select register (fsr). 7.2.4 how to configure the framer to enable crc-4 multi-frame alignment and select the locking cri- teria the crc-4 selection [1:0] bits of the framing select register (fsr) enable the framer to search for crc-4 multi-frame alignment and select the criteria for locking the crc-4 multi-frame alignment. the table below shows configurations of the crc-4 selection [1:0] bit of the framing select register (fsr). 7.2.5 how to configure the framer to enable cas multi-frame alignment the XRT86L34 framer can use two algorithms to search for cas multi-frame alignment pattern. upon detect- ing of cas multi-frame alignment pattern, the framer will declare cas multi-frame alignment synchronization and generate the receive cas multi-frame synchronization pulse (rxcasmsync_n). the cas selection [1:0] bits of the framing select register (fsr) enable the framer to search for cas multi-frame alignment. the table below shows configurations of the cas selection [1:0] bit of the framing select register (fsr). framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 0 fas selection bit r/w this read/write bit field allows the user to determine which algorithm is used for searching fas frame alignment pattern. when an fas alignment pattern is found and locked, the XRT86L34 will generate receive synchronization (rxsync_n) pulse. 0 - algorithm 1 is selected for searching fas frame alignment pattern. 1 - algorithm 2 is selected for searching fas frame alignment pattern. framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 3-2 crc-4 selection bit r/w theses read/write bit fields allow the user to enable searching of crc-4 multi- frame alignment and determine what criteria are used for locking the crc-4 multi-frame alignment pattern. 00 - searching of crc-4 multi-frame alignment is disabled. the XRT86L34 framer will not search for crc-4 multi-frame alignment and thus will not declare crc-4 multi-frame synchronization. no receive crc-4 multi-frame synchroni- zation (rxcrcmsync_n) pulse will be generated by the framer. 01 - searching of crc-4 multi-frame alignment is enabled. the XRT86L34 will search for and declare crc-4 multi-frame synchronization if: at least one valid crc-4 multi-frame alignment signal is observed within 8 ms. 10 - searching of crc-4 multi-frame alignment is enabled. the XRT86L34 will search for and declare crc-4 multi-frame synchronization if: at least two valid crc-4 multi-frame alignment signals are observed within 8 ms. the time separating two crc-4 multi-frame alignment signals is multiple of 2 ms. 11 - searching of crc-4 multi-frame alignment is enabled. the XRT86L34 will search for and declare crc-4 multi-frame synchronization if: at least three valid crc-4 multi-frame alignment signals are observed within 8 ms. the time separating two crc-4 multi-frame alignment signals is multiple of 2 ms.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 339 7.2.6 how to configure the framer to apply data and signaling conditioning to received e1 pay- load data on a per-channel basis the XRT86L34 t1/j1/e1 octal framer provides individual control of each of the thirty two ds0 channels. the user can apply data and signaling conditioning to the received e1 payload data coming from the e1 liu re- ceive block on a per-channel basis. the XRT86L34 framer can apply the following changes to the received e1 payload data coming from the ter- minal equipment on a per-channel basis: ? all 8 bits of the received payload data are inverted ? the even bits of the received payload data are inverted ? the odd bits of the received payload data are inverted ? the msb of the received payload data is inverted ? all received payload data except the msb are inverted configurations of the XRT86L34 framer to apply the above-mentioned changes to the received e1 payload data are controlled by the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of each ds0 channel. the XRT86L34 framer can also replace the incoming e1 payload data from the e1 liu receive block with pre- defined or user-defined codes. the XRT86L34 supports the following conditioning substitutions: ? busy code - an octet with hexadecimal value of 0x7f ? busy_ts code - an octet of pattern "111xxxxx" where "xxxxx" represents the timeslot number ? vacant code - an octet with hexadecimal value of 0xff ? a-law digital milliwatt code ? u-law digital milliwatt code ? idle code - an octet defined by the value stored in the user idle code register (ucr) ? moof code - mux-out-of-frame code with hexadecimal value of 0x1a ? prbs code - an octet generated by the pseudo-random bit sequence (prbs) generator block of the framer framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 5-4 cas selection bit r/w these read/write bit fields allow the user to enable searching of cas multi- frame alignment and determine which algorithm of the two are used for locking the cas multi-frame alignment pattern. 00 - searching of cas multi-frame alignment is disabled. the XRT86L34 framer will not search for cas multi-frame alignment and thus will not declare cas multi-frame synchronization. no receive cas multi-frame synchronization (rxcrcmsync_n) pulse will be generated by the framer. 01 - searching of cas multi-frame alignment is enabled. the XRT86L34 will search for and declare cas multi-frame synchronization using algorithm 1. 10 - searching of cas multi-frame alignment is enabled. the XRT86L34 will search for and declare cas multi-frame synchronization using algorithm 2 (g.732). 11 - searching of cas multi-frame alignment is disabled. the XRT86L34 framer will not search for cas multi-frame alignment and thus will not declare cas multi-frame synchronization. no receive cas multi-frame synchronization (rxcrcmsync_n) pulse will be generated by the framer.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 340 once again, configuration of the XRT86L34 framer to replace the received e1 payload data with the above- mentioned coding schemes are controlled by the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of each ds0 channel. finally, the XRT86L34 framer can configure any one or ones of the thirty two ds0 channels to be d or e chan- nels. d channel is used primarily for data link applications. e channel is used primarily for signaling for circuit switching with multiple access configurations. the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of each channel determine whether that particular channel is configured as d or e channel. the table below illustrates configurations of the receive data conditioning select [3:0] bits of the receive channel control register (rccr). when the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of a particular ds0 channel are set to 0100, the received e1 payload data of this ds0 channel are replaced by the octet stored in the receive user idle code register (rucr). the table below shows contents of the receive user idle code register. receive channel control register (rccr) (address = 0xn360h - 0xn37fh) b it n umber b it n ame b it t ype b it d escription 3-0 receive condition- ing select r/w 0000 - the received e1 payload data of this ds0 channel is unchanged. 0001 - all 8 bits of the input e1 payload data of this ds0 channel are inverted. 0010 - the even bits of the input e1 payload data of this ds0 channel are inverted. 0011 - the odd bits of the input e1 payload data of this ds0 channel are inverted. 0100 - the input e1 payload data of this ds0 channel are replaced by the octet stored in user idle code register (ucr). 0101 - the input e1 payload data of this ds0 channel are replaced by busy code (0x7f). 0110 - the input e1 payload data of this ds0 channel are replaced by vacant code (0xff). 0111 - the input e1 payload data of this ds0 channel are replaced by busy_ts code (111xxxxx). 1000 - the input e1 payload data of this ds0 channel are replaced by mux-out- of-frame (moof) code with value 0x1a. 1001 - the input e1 payload data of this ds0 channel are replaced by the a-law digital milliwatt pattern. 1010 - the input e1 payload data of this ds0 channel are replaced by the u-law digital milliwatt pattern. 1011 - the msb bit of the input e1 payload data of this ds0 channel is inverted. 1100 - all bits of the input e1 payload data of this ds0 channel except msb bit are inverted. 1101 - the input e1 payload data of this ds0 channel are replaced by prbs pat- tern created by the internal prbs generator of XRT86L34 framer. 1110 - the input e1 payload data of this ds0 channel is unchanged. 1111 - this channel is configured as d or e timeslot. receive user idle code register (ucr) (address = 0xn380h - 0xn397h) b it n umber b it n ame b it t ype b it d escription 7-0 user idle code r/w these read/write bit-fields permits the user store any value of idle code into the framer. when the receive data conditioning select [3:0] bits of rccr register of a particular ds0 channel are set to 0100, the received e1 payload data are replaced by contents of this register and sent to the terminal equipment.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 341 7.2.7 how to configure the XRT86L34 framer to extract robbed-bit signaling information the XRT86L34 t1/j1/e1 octal framer supports insertion of robbed-bit signaling information into the outgoing e1 frame. it also supports extraction and substitution of robbed-bit signaling information from the incoming e1 frame. the following section describes how does the XRT86L34 framer extract and substitute robbed-bit sig- naling in e1 mode. 7.2.8 configure the framer to receive and extract robbed-bit signaling the XRT86L34 framer supports receiving and extraction of cas signaling. the receive signaling extraction control [1:0] bits of the receive signaling control register (rscr) of each channel select either: ? no signaling extraction ? two-code signaling ? four-code signaling or ? sixteen-code signaling the table below shows configurations of the receive signaling extraction control [1:0] bits of the receive sig- naling control register. upon receiving and extraction of signaling bits from the incoming e1 frames, the XRT86L34 framer compares the signaling bits with the previously received ones. if there is a change of signaling data, a signaling update (sig) interrupt request may be generated at the end of an e1 multi-frame. the user can thus be notified of a change of signaling data event. to enable the signaling update interrupt, the signaling change interrupt enable bit of the framer interrupt en- able register (fier) has to be set. in addition, the t1/e1 framer interrupt enable bit of the block interrupt en- able register (bier) needs to be one. the table below shows configurations of the signaling change interrupt enable bit of the framer interrupt en- able register. receive signaling control register (rscr) (address = 0xn3a0h - 0xn3b7h) b it n umber b it n ame b it t ype b it d escription 1-0 signaling extraction control r/w 00 - the XRT86L34 framer does not extract signaling information from incoming e1 payload data. 01 - the XRT86L34 framer extracts sixteen-code signaling information from incoming e1 payload data. 10 - the XRT86L34 framer extracts four-code signaling information from incom- ing e1 payload data. 11 - the XRT86L34 framer extracts two-code signaling information from incom- ing e1 payload data. framer interrupt enable register (fier) (address = 0xnb05h) b it n umber b it n ame b it t ype b it d escription 5 signaling change interrupt enable r/w 0 - the signaling update interrupt is disabled. 1 - the signaling update interrupt is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 342 the table below shows configurations of the t1/e1 framer interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and the signaling information received is changed, the e1 receive framer block will set the signaling updated status bit of the framer interrupt status register (fisr) to one. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control register (icr). otherwise, a write-to- clear operation by the microprocessor is required to reset these status indicators. the table below shows the signaling update status bits of the framer interrupt status register. now, there is only one problem remains. since there are thirty two ds0 channels in e1, how do we know sig- naling information of which channel is changed? to solve this problem, the XRT86L34 provides three 8-bit signaling change registers to indicate the chan- nel(s) which signaling data change had occurred over the last e1 multi-frame period. each bit of the signaling change registers represents one timeslot of the e1 frame. if any particular bit is zero, it means there is no change of signaling data occurred in that particular timeslot over the last e1 multi-frame period. if any particular bit is one, it means there is change of signaling data occurred over the last e1 multi-frame period. the table below shows configurations of the signaling change registers. by reading contents of the signaling update status bits of the framer interrupt status register and the signal- ing change registers, the user can clearly identify which one(s) of the thirty-two ds0 channels has changed signaling information over the last multi-frame period. depending on configurations of the XRT86L34 framer, the signaling bits can be extracted from the incoming e1 frame and direct to all or any one of the following destinations: ? signaling data is stored to receive signaling register array (rsra) of each channel ? signaling data is sent to the terminal equipment through the receive signaling output pin (rxsig_n) block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 1 t1/e1 framer inter- rupt enable r/w 0 - every interrupt generated by the framer interrupt status register (fisr) is dis- abled. 1 - every interrupt generated by the framer interrupt status register (fisr) is enabled. framer interrupt status register (fisr) (address = 0xnb04h) b it n umber b it n ame b it t ype b it d escription 5 signaling updated rur / wc 0 - there is no change of signaling information in the incoming e1 payload data. 1 - there is change of signaling information in the incoming e1 payload data. signaling change registers (scr) (address = 0xn10dh - 0xn10fh) l ocation \ b it b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 0xn10dh ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 0xn10eh ch 8 ch 9 ch 10 ch 11 ch 12 ch 13 ch 14 ch 15 0xn10fh ch 16 ch 17 ch 18 ch 19 ch 20 ch 21 ch 22 ch 23 0xn10fh ch 24 ch 25 ch 26 ch 27 ch 28 ch 29 ch 30 ch 31
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 343 ? signaling data is sent to the terminal equipment through the receive overhead output pin (rxoh_n) ? signaling data is embedded into the output pcm data sending towards the terminal equipment through the receive serial output pin (rxser_n) the follow sections discuss how to configure the XRT86L34 framer to extract signaling information bits and send them to different destinations. 7.2.8.1 store signaling bits into rsra register array the four least significant bits of the receive signaling register array (rsra) of each timeslot can be used to store received signaling data. the user can read these bits through microprocessor access. if the XRT86L34 framer is configure to extract signaling bits from incoming e1 payload data, the e1 receive framer block will strip off the cas signaling bits from time slot 16 of the incoming e1 frames and store them into appropriate lo- cations of the rsra. the extraction of signaling bit from e1 pcm data is done on a per-channel basis. the bit 3 of rsra register is used to hole signaling bit a. bit 2 is used to hold signaling bit b. bit 1 is used to hold sig- naling bit c. bit 0 is used to hold signaling bit d. the table below shows the four least significant bits of the receive signaling register array. 7.2.8.2 outputting signaling bits through rxsig_n pin the XRT86L34 framer can be configure to output extracted signaling bits to external equipment through the rxsig_n pins. this pin is a multiplexed i/o pin with two functions: ? rxtsb[0]_n - receive timeslot number bit [0] output pin ? rxsig_n - receive signaling output pin when the receive fractional e1 bit of the receive interface control register (ricr) is set to 0, this pin is con- figured as rxtsb[0]_n pin, it outputs bit 0 of the timeslot number of the e1 pcm data that is receiving. when the receive fractional e1 bit of the receive interface control register (ricr) is set to 1, this pin is con- figured as rxsig_n pin, it acts as an output source for the signaling bits to be received in the inbound e1 frames. the table below shows configurations of the receive fractional e1 bit of the receive interface control regis- ter (ricr). receive signaling register array (rsra) (address = 0xn500h - 0xn51fh) b it n umber b it n ame b it t ype b it d escription 3 signaling bit a r/w this bit is used to store signaling bit a that is received and extracted. 2 signaling bit b r/w this bit is used to store signaling bit b that is received and extracted. 1 signaling bit c r/w this bit is used to store signaling bit c that is received and extracted. 0 signaling bit d r/w this bit is used to store signaling bit d that is received and extracted. receive interface control register (ricr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 4 receive fractional e1 r/w this read/write bit-field permits the user to determine which one of the two functions the multiplexed i/o pin of rxtsb[0]_n/rxsig_n is spotting. 0 - this pin is configured as rxtsb[0]_n pin, it outputs bit 0 of the timeslot num- ber of the e1 pcm data that is receiving. 1 - this pin is configured as rxsig_n pin, it acts as an output source for the signal- ing bits to be received in the inbound e1 frames
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 344 figure 99 below is a timing diagram of the rxsig_n output pin. please note that the signaling bit a of a certain timeslot coincides with bit 3 of the received serial output data; signaling bit b coincides with bit 2 of the re- ceived serial output data; signaling bit c coincides with bit 1 of the received serial output data and signaling bit d coincides with bit 0 of the received serial output data. 7.2.8.3 outputting signaling bits from rxoh_n pin the XRT86L34 framer can be configure to output extracted signaling bits to external equipment through the receive overhead rxoh_n output pins. the rxoh_n pin can acts as an output source for the signaling bits to be received in the inbound e1 frames. when this pin is chosen as the output source for the signaling bits, any data presents in time slot 16 of the in- coming e1 frames would be presented onto the pin directly. please note that the signaling bit a of channel 1-15 coincides with bit 1 of the pcm data; signaling bit b chan- nel 1-15 coincides with bit 2 of the pcm data; signaling bit c channel 1-15 coincides with bit 3 of the pcm; signaling bit d channel 1-15 coincides with bit 4 of the pcm data. similarly, the signaling bit a of channel 17-31 coincides with bit 5 of the pcm data; signaling bit b channel 17-31 coincides with bit 6 of the pcm data; signaling bit c channel 17-31 coincides with bit 7 of the pcm; sig- naling bit d channel 17-31 coincides with bit 8 of the pcm data. the receive signaling output enable bit of the receive signaling control register (rscr) determines wheth- er the extracted signaling bits will be sent through the receive overhead output pin (rxoh_n) to external equipments. the table below shows configurations of the receive overhead output enable bit of the receive signaling control register. 7.2.8.4 send signaling data through rxser_n pin as mentioned in the above sections, signaling information embedded in the incoming e1 pcm data can be sent to either the rsra register array and/or sent through the receive signaling output pin, at the same time, the signaling data will be directed to the receive serial data output pin together with other incoming e1 pay- load data. the external equipment can thus still extract signaling data from the received e1 payload data sep- arately. 7.2.8.5 signaling data substitution f igure 99. t iming diagram of r x s ig _ n o utput pin receive signaling control register (rscr) (address = 0xn3a0h - 0xn3bfh) b it n umber b it n ame b it t ype b it d escription 5 receive signaling output enable r/w 0 - the XRT86L34 framer will not send extracted signaling bits from the incom- ing e1 payload data to external equipment through the receive overhead output pin (rxoh_n). 1 - the XRT86L34 framer will send extracted signaling bits from the incoming e1 payload data to external equipment through the receive overhead output pin (rxoh_n).
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 345 after channel conditioning, the signaling conditioning can be optionally enabled by the rscr registers. the actual signaling bits in each channel can be replaced either with all ones or with signaling bits stored in the re- ceive substitution signaling register (rssr). to enable signaling substitution, the receive signaling substitu- tion enable bit of the receive signaling control register (rscr) has to be set to one. the table below shows configuration of the receive signaling substitution enable bit of the receive signaling control register. as mentioned before, the actual signaling bits in each channel can be replaced either with all ones or with sig- naling bits stored in the receive substitution signaling register (rssr). the table below shows configura- tions of the receive substitution signaling register. the receive signaling substitution control [1:0] bits can select all ones substitution, two-code signaling substi- tution, four-code signaling substitution, or sixteen-code signaling. the XRT86L34 framer can substitute received signaling bits with all ones. two-code signaling substitution is done by substituting all the four signaling bits with the content of the sig2-a bit of the register. four-code sig- naling substitution is done by substituting the first two signaling bits of the four with the sig4-a bit and the last two signaling bits of the four with the sig4-b bit of the rssr register. sixteen-code signaling substitution is implemented by substituting the four signaling bits with the content of sig16-a, sig16-b, sig16-c, and sig16-d bits of rssr register respectively. receive signaling control register (rscr) (address = 0xn3a0h - 0xn3bfh) b it n umber b it n ame b it t ype b it d escription 6 receive signaling substitution enable r/w 0 - signaling substitution is disabled. the XRT86L34 framer will not replace extracted signaling bits from the incoming e1 payload data with all ones or with signaling bits stored in rssr registers. 1 - signaling substitution is enabled. the XRT86L34 framer will replace extracted signaling bits from the incoming e1 payload data with all ones or with signaling bits stored in rssr registers. receive substitution signaling register (rssr) (address = 0xn380h - 0xn39fh) b it n umber b it n ame b it t ype b it d escription 7-4 reserved r/w 3 sig16-a sig4-a sig2-a sixteen-code signaling bit a four-code signaling bit a two-code signaling bit a 2 sig16-b sig4-b sig2-a sixteen-code signaling bit b four-code signaling bit b two-code signaling bit a 1 sig16-c sig4-a sig2-a sixteen-code signaling bit c four-code signaling bit a two-code signaling bit a 0 sig16-d sig4-b sig2-a sixteen-code signaling bit d four-code signaling bit b two-code signaling bit a
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 346 the table below shows configurations of the receive signaling substitution control [1:0] bits of the receive signaling control register. 7.2.9 how to configure the framer to detect alarms and error conditions the XRT86L34 t1/j1/e1 octal framer can be configured to monitor quality of received e1 frames. it can gen- erate error indicators if the local receive framer has received error frames from the remote terminal. if corre- sponding interrupt is enabled, the local microprocessor operation is interrupted by these error conditions. upon microprocessor interruption, the user can intervene by looking into the error conditions. at the same time, the user can configure the XRT86L34 framer to receive alarms and error indications to re- mote terminal. different alarms and error indications will be received depending on the error condition. the section below gives a brief discussion of the error conditions that can be detected by the XRT86L34 fram- er and error indications that will be generated. 7.2.10 how to configure the framer to detect ais alarm transmission of alarm indication signal (ais) or blue alarm by the intermediate node indicates that the equip- ment is still functioning but unable to offer services. it is an all ones (except for framing bits) pattern which can be used by the equipment further down the line to maintain clock recovery and timing synchronization. the XRT86L34 framer can detect three types of ais in e1 mode: ? framed ais ? unframed ais ? ais16 unframed ais is an all ones pattern. if unframed ais is sent, the equipment further down the line will be able to maintain timing synchronization and be able to recover clock from the received ais signal. however, due to the lack of framing bits, the equipment farther down the line will not be able to maintain frame synchronization and will declare loss of frame (lof). on the other hand, the payload portion of a framed ais pattern is all ones. however, a framed ais pattern still has correct framing bits. therefore, the equipment further down the line can still maintain frame synchroniza- tion as well as timing synchronization. in this case, no lof or red alarm will be declared. "ais16" is an ais alarm that only supported in e1 framing format. it is an all ones pattern in time slot 16 of each e1 frame. as we mentioned before, time slot 16 is usually used for signaling and data link in e1, therefore, an "ais16" alarm is transmitted by the intermediate node to indicate that the data link channel is having a prob- lem. since all the other thirty one time slots are still transmitting normal data (that is, framing information and pcm data), therefore, the equipment further down the line can still maintain frame synchronization, timing syn- chronization as well as receiving pcm data. in this case, no lof or red alarm will be declared by the equip- ments further down the line. however, a cas multi-frame yellow alarm will be sent by the equipment further down the line to indicate the loss of cas multi-frame alignment. the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming e1 frames for ais (both framed and unframed) and ais16 errors. ais alarm condition are detected and declared according to the following procedure: receive signaling control register (rscr) (address = 0xn340h - 0xn35fh) b it n umber b it n ame b it t ype b it d escription 3-2 receive signaling substitution control r/w 00 - the received signaling bits are replaced by all ones and send to the external equipment. 01 - two-code signaling substitution is applied to the received signaling bits. the replaced signaling information is sent to the external equipment. 10 - four-code signaling substitution is applied to the received signaling bits. the replaced signaling information is sent to the external equipment. 11 - sixteen-code signaling substitution is applied to the received signaling bits. the replaced signaling information is sent to the external equipment.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 347 1. the incoming e1 frames are monitored for ais detection. ais detection is defined as an unframed or framed pattern with less than three zeros in two consecutive frames. in the case of framed ais, time slot 0 is excluded. 2. an ais detection counter within the receive framer block of the XRT86L34 counts the occurrences of ais detection over a 4 ms interval. it will indicate a valid ais flag when thirteen or more of a possible sixteen ais are detected. 3. each 4 ms interval with a valid ais flag increments a flag counter which declares ais alarm when 25 valid flags have been collected. therefore, ais condition has to be persisted for 104 ms before ais alarm condition is declared by the XRT86L34 framer. if there is no valid ais flag over a 4ms interval, the alarm indication logic will decrement the flag counter. the ais alarm is removed when the counter reaches 0. that is, ais alarm will be removed if in over 104 ms, there is no valid ais flag. ais16 alarm condition are detected and declared according to the following procedure: 1. the incoming e1 frames are monitored for ais16 detection. ais16 detection is defined as two consecutive all ones time slot 16 bytes while cas multi-frame alignment pattern is missing or cas multi-frame is out of synchronization. 2. an ais16 detection counter within the receive framer block of the XRT86L34 counts the occurrences of ais16 detection. 3. each valid ais flag increments a flag counter which declares ais alarm when 22 valid flags have been col- lected. if there is no valid ais16 flag, the alarm indication logic will decrement the flag counter. the ais16 alarm is re- moved when the counter reaches 0. the alarm indication signal detection select [1:0] bits of the alarm generation register (agr) enable the three types of ais detection that are supported by the XRT86L34 framer. the table below shows configurations of the alarm indication signal detection select [1:0] bits of the alarm generation register (agr). if detection of unframed or framed ais alarm is enabled by the user and if ais is present in the incoming e1 frame, the XRT86L34 framer can generate a receive ais state change interrupt associated with the setting of receive ais state change bit of the alarm and error status register to one. to enable the receive ais state change interrupt, the receive ais state change interrupt enable bit of the alarm and error interrupt enable register (aeier) have to be set to one. in addition, the alarm and error inter- rupt enable bit of the block interrupt enable register (bier) needs to be one. alarm generation register (agr) (address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 1-0 ais detection select r/w 00 - ais alarm detection is disabled. 01 - detection of unframed ais alarm of all ones pattern is enabled. 10 - detection of ais16 alarm is enabled. 11 - detection of framed ais alarm of all ones pattern except for framing bits is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 348 the table below shows configurations of the receive ais state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and ais is present in the incoming e1 frame, the XRT86L34 framer will declare ais by doing the following: ? set the read-only receive ais state bit of the alarm and error status register (aesr) to one indicating there is ais alarm detected in the incoming e1 frame. ? set the receive ais state change bit of the alarm and error status register to one indicating there is a change in state of ais. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive ais state change status bits of the alarm and error status register. the receive ais state bit of the alarm and error status register (aesr), on the other hand, is a read-only bit indicating there is ais alarm detected in the incoming e1 frame. the table below shows the receive ais state status bits of the alarm and error status register. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 1 receive ais state change interrupt enable r/w 0 - the receive ais state change interrupt is disabled. 1 - the receive ais state change interrupt is enabled. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 1 receive ais state change rur / wc 0 - there is no change of ais state in the incoming e1 payload data. 1 - there is change of ais state in the incoming e1 payload data. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 6 receive ais state r 0 - there is no ais alarm condition detected in the incoming e1 payload data. 1 - there is ais alarm condition detected in the incoming e1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 349 7.2.11 how to configure the framer to detect red alarm the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming e1 frames for red alarm or loss of frame (lof) condition. red alarm condition are detected and declared accord- ing to the following procedure: 1. the red alarm is detected by monitoring the occurrence of loss of frame (lof) over a 4 ms interval. 2. an lof valid flag will be posted on the interval when one or more lof occurred during the interval. 3. each interval with a valid lof flag increments a flag counter which declares red alarm when 25 valid intervals have been accumulated. 4. an interval without valid lof flag decrements the flag counter. the red alarm is removed when the counter reaches zero. if lof condition is present in the incoming e1 frame, the XRT86L34 framer can generate a receive red alarm state change interrupt associated with the setting of receive red alarm state change bit of the alarm and er- ror status register to one. to enable the receive red alarm state change interrupt, the receive red alarm state change interrupt en- able bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive red alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and red alarm is present in the incoming e1 frame, the XRT86L34 framer will declare red alarm by doing the following: ? set the read-only receive red alarm state bit of the alarm and error status register (aesr) to one indicat- ing there is red alarm detected in the incoming e1 frame. ? set the receive red alarm state change bit of the alarm and error status register to one indicating there is a change in state of red alarm. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 2 receive red alarm state change inter- rupt enable r/w 0 - the receive red alarm state change interrupt is disabled. no receive loss of frame (rxlof) interrupt will be generated upon detection of lof condition. 1 - the receive red alarm state change interrupt is enabled. receive loss of frame (rxlof) interrupt will be generated upon detection of lof condition. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 350 the table below shows the receive red alarm state change status bits of the alarm and error status regis- ter. the receive red alarm state bit of the alarm and error status register (aesr), on the other hand, is a read- only bit indicating there is red alarm detected in the incoming e1 frame. the table below shows the receive red alarm state status bits of the alarm and error status register. 7.2.12 how to configure the framer to detect yellow alarm the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming e1 frames for yellow alarm condition. the yellow alarm is detected and declared according to the following proce- dure: 1. monitor the occurrence of yellow alarm pattern over a 4 ms interval. a yel valid flag will be posted on the interval when yellow alarm pattern occurred during the interval. 2. each interval with a valid yel flag increments a flag counter which declares yel alarm when 80 valid intervals have been accumulated. 3. an interval without valid yel flag decrements the flag counter. the yel alarm is removed when the counter reaches zero. if yellow alarm condition is present in the incoming e1 frame, the XRT86L34 framer can generate a receive yellow alarm state change interrupt associated with the setting of receive yellow alarm state change bit of the alarm and error status register to one. to enable the receive yellow alarm state change interrupt, the receive yellow alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive yellow alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier). alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 2 receive red alarm state change rur / wc 0 - there is no change of red alarm state in the incoming e1 payload data. 1 - there is change of red alarm state in the incoming e1 payload data. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 7 receive red alarm state r 0 - there is no red alarm condition detected in the incoming e1 payload data. 1 - there is red alarm condition detected in the incoming e1 payload data. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 0 receive yellow alarm state change interrupt enable r/w 0 - the receive yellow alarm state change interrupt is disabled. any state change of receive yellow alarm will not generate an interrupt. 1 - the receive yellow alarm state change interrupt is enabled. any state change of receive yellow alarm will generate an interrupt.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 351 the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and yellow alarm is present in the incoming e1 frame, the XRT86L34 framer will declare yellow alarm by doing the following: ? set the receive yellow alarm state change bit of the alarm and error status register to one indicating there is a change in state of yellow alarm. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive yellow alarm state change status bits of the alarm and error status reg- ister. 7.2.13 how to configure the framer to detect cas multi-frame yellow alarm the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming e1 frames for cas multi-frame yellow alarm condition. the cas multi-frame yellow alarm is detected and de- clared according to the following procedure: 1. monitor the occurrence of cas multi-frame yellow alarm pattern over a 4 ms interval. an myel valid flag will be posted on the interval when cas multi-frame yellow alarm pattern occurred during the interval. 2. each interval with a valid myel flag increments a flag counter which declares myel alarm when 80 valid intervals have been accumulated. 3. an interval without valid myel flag decrements the flag counter. the myel alarm is removed when the counter reaches zero. if cas multi-frame yellow alarm condition is present in the incoming e1 frame, the XRT86L34 framer can gen- erate a receive cas multi-frame yellow alarm state change interrupt associated with the setting of receive cas multi-frame yellow alarm state change bit of the alarm and error status register to one. to enable the receive cas multi-frame yellow alarm state change interrupt, the receive cas multi-frame yellow alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt enable bit of the block interrupt enable register (bier) needs to be one. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 0 receive yellow alarm state change rur / wc 0 - there is no change of yellow alarm state in the incoming e1 payload data. 1 - there is change of yellow alarm state in the incoming e1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 352 the table below shows configurations of the receive cas multi-frame yellow alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and cas multi-frame yellow alarm is present in the incoming e1 frame, the XRT86L34 framer will declare cas multi-frame yellow alarm by doing the following: ? set the receive cas multi-frame yellow alarm state change bit of the alarm and error status register to one indicating there is a change in state of cas multi-frame yellow alarm. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive cas multi-frame yellow alarm state change status bits of the alarm and error status register. 7.2.14 how to configure the framer to detect bipolar violation the line coding for the e1 signal should be bipolar. that is, a binary "0" is received as zero volts while a binary "1" is received as either a positive or negative pulse, opposite in polarity to the previous pulse. a bipolar viola- tion or bpv occurs when the alternate polarity rule is violated. the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming e1 frames for bipolar violations. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 5 receive cas multi- frame yellow alarm state change inter- rupt enable r/w 0 - the receive cas multi-frame yellow alarm state change interrupt is dis- abled. any state change of receive cas multi-frame yellow alarm will not gen- erate an interrupt. 1 - the receive cas multi-frame yellow alarm state change interrupt is enabled. any state change of receive cas multi-frame yellow alarm will gener- ate an interrupt. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 5 receive cas multi- frame yellow alarm state change rur / wc 0 - there is no change of cas multi-frame yellow alarm state in the incoming e1 payload data. 1 - there is change of cas multi-frame yellow alarm state in the incoming e1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 353 if a bipolar violation is present in the incoming e1 frame, the XRT86L34 framer can generate a receive bipo- lar violation interrupt associated with the setting of receive bipolar violation bit of the alarm and error status register to one. to enable the receive bipolar violation interrupt, the receive bipolar violation interrupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt en- able bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive bipolar violation interrupt enable bit of the alarm and er- ror interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and one or more bipolar violations are present in the incoming e1 frame, the XRT86L34 framer will declare receive bipolar violation by doing the following: ? set the receive bipolar violation bit of the alarm and error status register to one indicating there are one or more bipolar violations. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive bipolar violation status bits of the alarm and error status register. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 3 receive bipolar vio- lation interrupt enable r/w 0 - the receive bipolar violation interrupt is disabled. occurrence of one or more bipolar violations will not generate an interrupt. 1 - the receive bipolar violation interrupt is enabled. occurrence of one or more bipolar violations will generate an interrupt. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 3 receive bipolar vio- lation state change rur / wc 0 - there is no change of bipolar violation state in the incoming e1 payload data. 1 - there is change of bipolar violation state in the incoming e1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 354 the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and one or more loss of signals are present in the incoming e1 frame, the XRT86L34 framer will declare receive loss of signal by doing the following: ? set the receive loss of signal bit of the alarm and error status register to one indicating there is one or more loss of signals. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive loss of signal status bits of the alarm and error status register. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 4 receive loss of sig- nal interrupt enable r/w 0 - the receive loss of signal interrupt is disabled. occurrence of loss of sig- nals will not generate an interrupt. 1 - the receive loss of signal interrupt is enabled. occurrence of loss of signals will generate an interrupt. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 4 receive loss of sig- nal state rur / wc 0 - there is no change of loss of signal state in the incoming e1 payload data. 1 - there is change of loss of signal state in the incoming e1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 355 8.0 the ds1 receive section 8.1 t he ds1 r eceive p ayload d ata o utput i nterface b lock 8.1.1 description of the receive payload data output interface block each of the four framers within the XRT86L34 includes a receive payload data output interface block. the function of the block is to provide an interface to the terminal equipment (for example, a central office or switching equipment) that has data to receive from a "far end" terminal over a ds1 or e1 transport medium. the payload data output interface module (also known as the back-plane interface module) supports payload data to be taken from or presented to the system. in ds1 mode, supported data rates are 1.544mbit/s, mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 12.352mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. in e1 mode, supported data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the receive payload data output interface block supplies or accepts the following signals to the terminal equipment circuitry: ? receive serial data input (rxser_n) ? receive serial clock (rxserclk_n) ? receive single-frame synchronization signal (rxsync_n) ? receive multi-frame synchronization signal (rxmsync_n) ? receive time-slot indicator clock (rxtsclk_n) ? receive time-slot indication bits (rxtsb[4:0]_n) the receive serial data is an output pin carrying payload, signaling and sometimes data link data supplied by XRT86L34 to the local terminal equipment. the receive serial clock is an input or output signal used by the receive payload data input interface block to send out serial data to the local terminal equipment. the receive clock inversion bit of the receive inter- face control register (ticr) determines at which edge of the receive serial clock would data transition on the receive serial data pin occur. the table below shows configurations of the receive clock inversion bit of the receive interface control reg- ister (ricr). throughout the discussion of this datasheet, we assume that serial data transition happens on rising edge of the receive serial clock unless stated otherwise. the receive single-frame synchronization signal is either input or output. when configure as input, it indicates beginning of a ds1 frame. when configure as output, it indicates end of a ds1 frame. the receive multi-frame synchronization signal is an output pin from XRT86L34 indicating end of a ds1 multi- frame. by connecting these signals with the local terminal equipment, the receive payload data output interface routes received payload data from the receive framer module to the local terminal equipment. 8.1.2 brief discussion of the receive payload data output interface block operating at 1.544mbit/s mode the incoming receive payload data is taken into the framer from the liu interface using the recovered re- ceive line clock. the payload data is then routed through the receive farmer module and presented to the receive payload data output interface through the receive serial data output pin (rxser_n). this data is then clocked out using the receive serial clock (rxserclk_n). receive interface control register (ricr) (address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 3 receive clock inversion r/w 0 - serial data transition happens on rising edge of the receive serial clock. 1 - serial data transition happens on falling edge of the receive serial clock.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 356 there is a two-frame (512 bits) elastic buffer between the receive framer module and the receive payload data output interface. this buffer can be enabled or disabled via programming the slip buffer enable [1:0] bits in slip buffer control register (sbcr). the following table shows configurations of the slip buffer enable [1:0] bits in slip buffer control register. if the slip buffer is not in bypass mode, then the user has the option of either providing the receive single- frame synchronization pulse or getting the receive single-frame synchronization pulse on frame boundary at the rxsync_n pin. the slip buffer receive synchronization direction bit of the slip buffer control register (sbcr) determines whether the receive single-frame synchronization signal is input or output. the table below demonstrates settings of the slip buffer receive synchronization direction bit of the slip buff- er control register. if the slip buffer is in bypass mode, the receive payload data is routed to the receive payload data output interface from the receive framer module directly. the recovered line clock is used to carry the receive payload data all the way from the liu interface, to the receive framer module and eventually output through the receive serial data output pin. the receive serial clock signal is therefore an output using the recovered receive line clock as timing source. the receive single-frame synchronization signal is also output in slip buffer bypass mode. if the slip buffer is enabled, the receive payload data is latched into the elastic store using the recovered receive line clock. the local terminal equipment supplies a free-running 1.544mhz clock to the receive se- rial clock pin to latch the receive payload data out from the elastic store. since the recovered receive line clock and the receive serial clock are coming from different timing sources, the slip buffer will gradually fill or empty. if the elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties and a read oc- curs, then a full frame of data will be repeated and a status bit will be updated. if the buffer fills and a write comes, then a full frame of data will be deleted and another status bit will be set. a detailed description of the elastic buffer can be found in later sections. in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. slip buffer control register (sbcr) (address = 0xn116h) b it n umber b it n ame b it t ype b it d escription 1-0 slip buffer enable r/w 00 - slip buffer is bypassed. the receive payload data is passing from the receive framer module to the receive payload data output interface directly without routing through the slip buffer. the receive serial clock signal (rxserclk_n) is an output. 01 - the elastic store (slip buffer) is enabled. the receive payload data is passing from the receive framer module through the slip buffer to the receive payload data output interface. the receive serial clock signal (rxserclk_n) is an input. 10 - the slip buffer acts as a fifo. the fifo latency register (flr) determines the data latency. the receive payload data is passing from the receive framer module through the fifo to the receive payload data output interface. the receive serial clock signal (rxserclk_n) is an input. 11 - slip buffer is bypassed. the receive payload data is passing from the receive framer module to the receive payload data output interface directly without routing through the slip buffer. the receive serial clock signal (rxserclk_n) is an output. slip buffer control register (sbcr) (address = 0xn116h) b it n umber b it n ame b it t ype b it d escription 2 slip buffer receive synchronization direction r/w 0 - the receive single-frame synchronization signal (rxsync_n) is an output if the slip buffer is not in bypass mode. 1 - the receive single-frame synchronization signal (rxsync_n) is an input if the slip buffer is not in bypass mode.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 357 if the slip buffer is put into a fifo mode, it is acting like a standard first-in-first-out storage. a fixed read and write latency is maintained in a programmable fashion controlled by the fifo latency register (fifolr). the local terminal equipment supplies a 1.544mhz clock to the receive serial clock pin to latch the receive payload data out from the fifo. however, it is the responsibility of the user to phase lock the in- put receive serial clock to the recovered receive line clock to avoid either over-run or under-run of the fifo. in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. the following table summaries the input or output nature of the receive serial clock and receive single- frame synchronization signals for different slip buffer settings. the receive time-slot indication bits (rxtsb[4:0]_n) are multiplexed i/o pins. the functionality of these pins is governed by the value of receive fractional t1 output enable bit of the receive interface control register (ricr). the following table illustrates the configurations of the receive fractional ds1 input enable bit. when configured to operate in normal condition (that is, when the receive fractional t1 input enable bit is equal to zero), these bits reflect the five-bit binary value of the time slot number (0 - 23) being outputted and processed by the receive payload data output interface block of the framer. rxtsb[4] represents the msb of the binary value and rxtsb[0] represents the lsb. when the receive fractional t1 output enable bit is equal to one, the rxtsb[0]_n bit becomes the receive fractional t1 output signal (rxfrtd_n). this output pin carries fractional t1 output data extracted by the framer from the incoming ds1 data stream. the fractional t1 output interface allows certain time-slots of ds1 t able 176: t he r eceive s erial c lock and r eceive s ingle -f rame s ynchronization signals for different s lip b uffer settings r eceive t iming s ource r x s er c lk _ n r x s ync _ n s lip b uffer s ynchronization d irection b it = 0 s lip b uffer s ynchronization d irection b it = 1 slip buffer bypassed output output output slip buffer enabled input output input slip buffer acts as fifo input output input receive interface control register (ricr) (address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 4 receive fractional ds1 output enable r/w 0 - the receive time-slot indication bits (rxtsb[4:0] are outputting five-bit binary val- ues of time-slot number (0-23) being accepted and processed by the receive payload data output interface block of the framer. the receive time-slot indicator clock signal (rxtsclk_n) is a 192khz clock that pulses high for one ds1 bit period whenever the receive payload data output inter- face block is accepting the lsb of each of the twenty-four time slots. 1 - the rxtsb[0]_n bit becomes the receive fractional t1 output signal (rxfrtd_n) which carries fractional ds1 payload data from the framer. the rxtsb[1]_n bit becomes the receive signaling data output signal (rxsig_n) which is used to carry robbed-bit signaling data extracted from the inbound ds1 frame. the rxtsb[2]_n bit serially outputs all five-bit binary values of the time slot number (0-23) being accepted and processed by the receive payload data output interface block of the framer. the rxtsclk_n will output gaped fractional ds1 clock that can be used by terminal equipment to latch in fractional ds1 payload data at rising edge of the clock. or, the rxtsclk_n pin will be a clock enable signal to receive fractional ds1 output sig- nal (rxfrtd_n) when the un-gaped receive serial output clock (rxserclk_n) is used to latch in fractional ds1 payload data into the terminal equipment.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 358 data to be routed to destinations other than the local terminal equipment. function of the fractional t1 output signal will be discussed in details in later sections. when the receive fractional t1 output enable bit is equal to one, the rxtsb[1]_n bit becomes the receive signaling data output signal (rxsig_n). these output pins can be used to carry robbed-bit signaling data ex- tracted from the inbound ds1 frame. function of the receive signaling data output signal will be discussed in details in later sections. when the receive fractional t1 output enable bit is equal to one, the rxtsb[2]_n bit serially outputs all five- bit binary values of the time slot number (0-23) being outputted and processed by the receive payload data output interface block of the framer. msb of the binary value is presented first and the lsb is presented last. the rxtsb[3]_n and rxtsb[4}_n pins are not multiplexed. the table below shows functionality of the rxtsb[2:0] bits when the receive fractional t1 output bit is set to different values. the receive time-slot indicator clock signal (rxtsclk_n) is a multi-function output pin. when configured to operate in normal condition (that is, when the receive fractional t1 input enable bit is equal to zero), the rxtsclk_n is a 192khz clock that pulses high for one ds1 bit period whenever the receive payload data output interface block is outputting the lsb of each of the twenty-four time slots. the local terminal equipment should use this clock signal to sample the rxtsb[0] through rxtsb[4] bits and identify the time-slot being pro- cessed via the receive section of the framer. when the receive fractional t1 output enable bit is equal to one, the rxtsclk_n will output gaped fractional ds1 clock whenever fractional ds1 payload data is present at the rxfrtd_n pin. the local terminal equip- ment can latch in fractional ds1 payload data at falling edge of the clock. otherwise, this pin will be a clock enable signal to receive fractional ds1 output signal (rxfrtd_n) if the framer is configured accordingly. in this way, fractional ds1 payload data is clocked into the terminal equipment using un-gaped receive serial output clock (rxserclk_n). a detailed discussion of the fractional ds1 payload data output interface can be found in later sections. a detailed discussion of how to connect the receive payload data output interface block to the local terminal equipment with slip buffer enabled or disabled can be found in the later sections. 8.1.2.1 connect the receive payload data output interface block to the local terminal equipment if the slip buffer is bypassed by setting the slip buffer enable [1:0] bits of the slip buffer control register to 00 or 11, the receive framer module routes the receive payload data directly to the receive payload data output interface without pass- ing through the elastic buffer. the XRT86L34 uses the recovered receive line clock internally to carry the receive payload data directly across the whole chip. the recovered receive line clock is essentially be- come timing source of the receive serial clock output. if the slip buffer is bypassed, the receive single-frame synchronization signal is automatically configured to be output signals. it should pulse high for one ds1 bit period (648ns) at the last bit position of each ds1 frame. by triggering on the high pulse on the receive single-frame synchronization signal, the terminal equipment can identify the end of a ds1 frame and should prepare to accept payload data of the next ds1 frame from the framer. the receive multi-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the last bit position of a ds1 multi-frame. by triggering on the high pulse on the receive multi-frame synchronization t able 177: t he r x ts b [2:0] bits when the r eceive f ractional t1 o utput bit is set to different values r eceive f ractional t1 o utput b it = 0 r eceive f ractional t1 o utput b it = 1 rxtsb[0] output rxfrtd output rxtsb[1] output rxsig output rxtsb[2] output rxts output
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 359 signal, the framer can identify the end of a ds1 super-frame and should prepare to accept payload data of the next ds1 super-frame from the framer. see figure 100 for how to connect the receive payload data output interface block to the local terminal equipment when the slip buffer is bypassed and the recovered receive line clock is timing source of the re- ceive section. the following figure 101 shows waveforms of the signals (rxserclk_n, rxser_n, rxsync_n, rxtsclk_n and rxtsb[4:0]_n) which connecting the receive payload data output interface block to the local terminal equip- f igure 100. i nterfacing XRT86L34 local t erminal e quipment with s liff b uffer b ypassed and r ecov - ered r eceive l ine c lock as r eceive t iming s ource rxserclk_0 rxser_0 rxmsync_0 rxsync_0 rxtsclk_0 rxtsb[4:0]_0 rxserclk_3 rxser_3 rxmsync_3 rxsync_3 rxtsclk_3 rxtsb[4:0]_3 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxlineclk_0 rxlineclk_7
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 360 ment when the slip buffer is bypassed and the recovered receive line clock is timing source of the receive section. 8.1.2.2 connect the receive payload data output interface block to the local terminal equipment if the slip buffer is enabled by setting the slip buffer enable [1:0] bits of the slip buffer control register to 01, the framer includes the two- frame elastic buffer into its data path. the receive framer module routes the receive payload data to the elastic buffer first. the receive payload data is then presented to the receive payload data output interface. the XRT86L34 uses the recovered receive line clock internally to clock in the receive payload data into the elastic buffer. the terminal equipment should provide a 1.544mhz clock to the receive serial clock input pin to latch data out from the elastic buffer. the recovered receive line clock and the receive serial clock are generated from two different timing sources. that is, the recovered receive line clock is originating from a remote site while receive serial clock generating by a local oscillator. any mismatch in frequencies of these two clocks will result in the slip buffer to gradually fill or deplete. overtime, the elastic buffer either fills or empties completely. once that happened, a controlled slip by the XRT86L34 will occur. the receive slip buffer slip bit of the slip buffer status register (sbsr) is set to 1. if the buffer empties and a read occurs, then a full frame of data will be repeated and the receive slip buffer empty bit of the slip buffer status register (sbsr) will be forced high. if the buffer fills and a write comes, then a full frame of data will be deleted and the receive slip buffer full bit of the slip buffer status register (sbsr) will be forced high. the following table demonstrates settings of the receive slip buffer slip bit, receive slip buffer empty bit and receive slip buffer full bit of the slip buffer status register. f igure 101. w aveforms of the s ignals c onnecting the r eceive p ayload d ata o utput i nterface block to the local t erminal e quipment when the s lip b uffer is b ypassed and the r ecovered l ine c lock is the t iming s ource of the r eceive s ection c rxserclk rxser rxsync(input) rxsync(output) rxchclk rxchn[4:0] rxchn[0]/rxsig rxchclk rxchn[2]/rxchn rxchn[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 16 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #16
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 361 in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. when the slip buffer receive synchronization direction bit is set to 0, the receive single-frame synchronization signal (rxsync_n) is an. when the slip buffer receive synchronization direction bit is set to 1,the receive single- frame synchronization signal (rxsync_n) is an input. if the receive single-frame synchronization signal is an output, it should pulse high for one ds1 bit period (648ns) at the last bit position of each ds1 frame. by triggering on the high pulse on the receive single- frame synchronization signal, the terminal equipment can identify the end of a ds1 frame and should prepare to accept payload data of the next ds1 frame from the framer. if the receive single-frame synchronization signal is an input, it should pulse high for one ds1 bit period (648ns) at the first bit position (f-bit) of each ds1 frame. by sampling the high pulse of the receive single- frame synchronization signal, the framer should identity the beginning of a ds1 frame and can send out data in a synchronized way. it is the responsibility of the local terminal equipment to align the start of a ds1 frame with the receive single-frame synchronization pulse. the receive multi-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the last bit position of frame number one of a ds1 multi-frame. by triggering on the high pulse on the receive multi- frame synchronization signal, the framer can identify the end of a ds1 super-frame and should prepare to ac- cept payload data of the next ds1 super-frame from the framer. slip buffer status register (sbsr) (address = 0xnb08h) b it n umber b it n ame b it t ype b it d escription 2 receive slip buffer full r/w 0 - the receive slip buffer is not full. 1 - the receive slip buffer is full and one frame of data is discarded. 1 receive slip buffer empty r/w 0 - the receive slip buffer is not empty. 1 - the receive slip buffer is empty and one frame of data is repeated. 1 receive slip buffer slip r/w 0 - the receive slip buffer does not slip. 1 - the receive slip buffer slips since either full or emptied.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 362 see figure 102 for how to connect the receive payload data output interface block to the local terminal equipment when the slip buffer is enabled. f igure 102. i nterfacing XRT86L34 to local t erminal e quipment with s lip b uffer e nabled or a cts as fifo rxserclk_0 rxser_0 rxmsync_0 rxsync_0 rxtsclk_0 rxtsb[4:0]_0 rxserclk_3 rxser_3 rxmsync_3 rxsync_3 rxtsclk_3 rxtsb[4:0]_3 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 363 the following figure 103 shows waveforms of the signals (rxserclk_n, rxser_n, rxsync_n, rxtsclk_n and rxtsb[4:0]_n) which connecting the receive payload data output interface block to the local terminal equip- ment when the slip buffer is enabled. 8.1.2.3 connect the receive payload data output interface block to the local terminal equipment if the slip buffer is configured as fifo by setting the slip buffer enable [1:0] bits of the slip buffer control register to 10, the framer puts the elastic buffer into fifo mode. receive framer module routes the receive payload data through the first-in-first-out storage to the receive payload data output interface. the XRT86L34 uses the recovered receive line clock internally to clock in the receive payload data into the fifo. the terminal equipment should provide an external 1.544mhz clock to the receive serial clock input pin to latch data out from the fifo. it is the responsibility of the user to phase lock the input receive serial clock to the recovered receive line clock to avoid either over-run or under-run of the fifo. the latency between writing a bit into the fifo and reading the same bit from it (read and write latency) is actually depth of the fifo, which is maintained in a programmable fashion controlled by the fifo latency register (fifolr). the largest possible depth of the fifo is thirty-two bytes or one e1 frame. the default depth of the fifo when XRT86L34 first powered up is four bytes. the table below shows the fifo latency register. in this mode, the receive single-frame synchronization signal can be either input or output depending on the settings of the slip buffer receive synchronization direction bit of the slip buffer control register. when the slip buffer receive synchronization direction bit is set to 0, the receive single-frame synchronization signal f igure 103. w aveforms of the s ignals that c onnect the r eceive p ayload d ata o utput i nterface block to the local t erminal e quipment when the s lip b uffer is e nabled fifo latency register (fifolr) (address = 0x117h) b it n umber b it n ame b it t ype b it d escription 4-0 fifo latency r/w these bits determine depth of the fifo in terms of bytes. the largest possible value is thirty-two bytes or one e1 frame. c rxserclk rxser rxsync(input) rxsync(output) rxchclk rxchn[4:0] rxchn[0]/rxsig rxchclk rxchn[2]/rxchn rxchn[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 16 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #16
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 364 (rxsync_n) is an. when the slip buffer receive synchronization direction bit is set to 1,the receive single- frame synchronization signal (rxsync_n) is an input. if the receive single-frame synchronization signal is an output, it should pulse high for one ds1 bit period (648ns) at the last bit position of each ds1 frame. by triggering on the high pulse on the receive single- frame synchronization signal, the terminal equipment can identify the end of a ds1 frame and should prepare to accept payload data of the next ds1 frame from the framer. if the receive single-frame synchronization signal is an input, it should pulse high for one ds1 bit period (648ns) at the first bit position (f-bit) of each ds1 frame. by sampling the high pulse of the receive single- frame synchronization signal, the framer should identity the beginning of a ds1 frame and can send out data in a synchronized way. it is the responsibility of the local terminal equipment to align the start of a ds1 frame with the receive single-frame synchronization pulse. the receive multi-frame synchronization signal should pulse high for one ds1 bit period (648ns) at the last bit position of frame number one of a ds1 multi-frame. by triggering on the high pulse on the receive multi- frame synchronization signal, the framer can identify the end of a ds1 super-frame and should prepare to ac- cept payload data of the next ds1 super-frame from the framer. see figure 104 for how to connect the receive payload data output interface block to the local terminal equipment when the slip buffer is acted as fifo. the following figure 105 shows waveforms of the signals (rxserclk_n, rxser_n, rxsync_n, rxtsclk_n and rxtsb[4:0]_n) which connecting the receive payload data output interface block to the local terminal equip- ment when the slip buffer is acted as fifo. f igure 104. i nterfacing XRT86L34 to local t erminal e quipment with s lip b uffer e nabled or a cts as fifo rxserclk_0 rxser_0 rxmsync_0 rxsync_0 rxtsclk_0 rxtsb[4:0]_0 rxserclk_3 rxser_3 rxmsync_3 rxsync_3 rxtsclk_3 rxtsb[4:0]_3 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 365 8.1.3 high speed receive back-plane interface the high-speed back-plane interface supports payload data to be taken from or presented to the local termi- nal equipment at a rate higher than 1.544mbit/s. in ds1 mode, supported high-speed data rates are mvip 2.048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 12.352mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s or h.100 16.384mbit/s. the receive multiplex enable bit and the receive interface mode select [1:0] bits of the receive interface control register (ricr) determine the receive back-plane interface data rate. the following table shows configurations of the receive multiplex enable bit and the receive interface mode select [1:0] bits of the receive interface control register (ricr). f igure 105. w aveforms of the s ignals that c onnect the r eceive p ayload d ata o utput i nterface block to the local t erminal e quipment when the s lip b uffer is acted as fifo receive interface control register (ricr) (address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 2 receive multiplex enable r/w 0 - the receive back-plane interface block is configured to non-channel-multiplexed mode. 1 - the receive back-plane interface block is configured to channel-multiplexed mode 1-0 receive interface mode select r/w when combined with the receive multiplex enable bit, these bits determine the receive back-plane interface data rate. c rxserclk rxser rxsync(input) rxsync(output) rxchclk rxchn[4:0] rxchn[0]/rxsig rxchclk rxchn[2]/rxchn rxchn[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 16 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #16
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 366 the table below shows the combinations of receive multiplex enable bit and receive interface mode select [1:0] bits and the resulting receive back-plane interface data rates. when the receive multiplex enable bit is set to zero, the framer is configured in non-channel-multiplexed mode. the possible data rates are 1.544mbit/s, mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s. in non-chan- nel-multiplexed mode, payload data of each channel are sending out from the receive high-speed back-plane interface separately. each channel uses its own receive serial clock, receive serial data, receive single- frame synchronization signal and receive multi-frame synchronization signal as interface between the framer and the terminal equipment. section 2.1.1.1, 2.1.1.2 and 2.1.1.3 provide details on how to connect the re- ceive payload data interface block with the local terminal equipment when the back-plane interface data rate is 1.544mbit/s. when the back-plane interface data rate is mvip 2.048mbit/s, 4.096mbit/s and 8.192mbit/s, the receive serial clock, receive serial data and receive single-frame synchronization are all configured as inputs. the re- ceive multi-frame synchronization signal is still output. the receive serial clock is configured as an input tim- ing source for the high-speed back-plane interface with frequencies of 2.048 mhz, 4.096 mhz and 8.192 mhz respectively. the table below summaries the clock frequencies of rxserclk_n input when the framer is operating in non- multiplexed high-speed back-plane mode. when the receive multiplex enable bit is set to one, the framer is configured in channel-multiplexed mode. the possible data rates are multiplexed 12.352mbit/s, bit-multiplexed 16.384mbit/s, hmvip 16.384mbit/s and h.100 16.384mbit/s. in channel-multiplexed mode, four channels share the receive serial data, receive sin- gle-frame synchronization signal and receive serial clock of one channel as interface between the framer and the terminal equipment. the receive serial clock runs at frequencies of 12.352 mhz or 16.384 mhz. it serves as the primary clock source for the high-speed back-plane interface. t able 178: r eceive m ultiplex e nable bit and r eceive i nterface m ode s elect [1:0] bits with the resulting r eceive b ack - plane i nterface data rates r eceive m ultiplex e nable b it r eceive i nterface m ode s elect b it 1 r eceive i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate 0 0 0 1.544mbit/s 0 0 1 mvip 2.048mbit/s 0 1 0 4.096mbit/s 0 1 1 8.192mbit/s 1 0 0 multiplexed 12.352mbit/s 1 0 1 bit multiplexed 16.384mbit/s 1 1 0 hmvip 16.384mbit/s 1 1 1 h.100 16.384mbit/s receive multiplex enable bit = 0 r eceive i nterface m ode s elect b it 1 r eceive i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate r x s er c lk 0 0 1.544mbit/s 1.544mhz 0 1 mvip 2.048mbit/s 2.048 mhz 1 0 4.096mbit/s 4.096 mhz 1 1 8.192mbit/s 8.192 mhz
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 367 payload and signaling data of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. pay- load and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. the re- ceive single-frame synchronization signal of channel 0 pulses high at the beginning of the frame with data from channel 0-3 multiplexed together. the receive single-frame synchronization signal of channel 4 pulses high at the beginning of the frame with data from channel 4-7 multiplexed together. the table below summaries the clock frequencies of rxserclk_n input when the framer is operating in multi- plexed high-speed back-plane mode. when the frame is running at high-speed back-plane interface mode other than the 1.544mbit/s data rate, the receive single-frame synchronization signal could pulse high or low indicating boundaries of ds1 frames. the receive synchronization pulse low bit of the receive interface control register (ticr) determines whether the receive single-frame synchronization signal is high active or low active. the table below shows configurations of the receive synchronization pulse low bit of the receive interface control register (ricr). throughout the discussion of this datasheet, we assume that the receive single-frame synchronization signal pulses high unless stated otherwise. the following sections discuss details of how to operate the framer in different back-plane interface speed mode and how to connect the receive payload data output interface block to the local terminal equipment. 8.1.3.1 t1 receive input interface - mvip 2.048 mhz when the receive multiplex enable bit is set to zero and the receive interface mode select [1:0] bits are set to 01, the receive back-plane interface of framer is running at a data rate of 2.048mbit/s. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) receive multiplex enable bit = 1 r eceive i nterface m ode s elect b it 1 r eceive i nterface m ode s elect b it 0 b ack - plane i nterface d ata r ate r x s er c lk 0 0 multiplexed 12.352mbit/s 12.352 mhz 0 1 bit-multiplexed 16.384mbit/s 16.384 mhz 1 0 hmvip 16.384mbit/s 16.384 mhz 1 1 h.100 16.384mbit/s 16.384 mhz receive interface control register (ricr) (address = 0xn122h) b it n umber b it n ame b it t ype b it d escription 3 receive synchronization pulse low r/w 0 - the receive single-frame synchronization signal will pulse high indicating the beginning of a ds1 frame when the high-speed back-plane interface is running at a mode other than the 1.544mbit/s. 1 - the receive single-frame synchronization signal will pulse low indicating the beginning of a ds1 frame when the high-speed back-plane interface is running at a mode other than the 1.544mbit/s.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 368 the receive back-plane interface is pumping out data through rxser_n at an e1 equivalent data rate of 2.048mbit/s. the local terminal equipment supplies a free-running 2.048mhz clock to the receive serial clock input. the receive high-speed back-plane interface of the framer then sends out serial data at rising edge of the receive serial clock. the local terminal equipment samples the serial data at falling edge of the clock. the terminal equipment take in data grouped in 256-bit frame 8000 times every second. each frame consists of thirty-two octets as in e1. the receive high-speed back-plane interface maps a 193-bit t1 frame into this 256-bit format as described below: 1. the f-bit is mapped into msb of the first e1 time-slot. the framer will insert seven "don't care" bits to the rest of the first octet that would be ignored by the local terminal equipment. 2. payload data of t1 time-slot 0, 1 and 2 are mapped into e1 time-slot 1, 2 and 3. 3. the receive high-speed back-plane interface will stuff e1 time-slot 4 with eight "don't care" bits that would be ignored by the local terminal equipment. 4. following the same rules of step 2 and 3, the receive high-speed back-plane interface maps every three time-slots of t1 payload data into four e1 time-slots. the mapping of t1 frame into e1 framing format is shown in the table below. the receive single-frame synchronization input signal (rxsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse of the receive single-frame synchro- nization signal, the framer can identity the beginning of a ds1 frame and start pumping payload data out. t able 179: t he mapping of t1 frame into e1 framing format t1 f-bit ts0 ts1 ts2 don't care bits ts3 ts4 ts5 e1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 t1 don't care bits ts6 ts7 ts8 don't care bits ts9 ts10 ts11 e1 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 t1 don't care bits ts12 ts13 ts14 don't care bits ts15 ts16 ts17 e1 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 t1 don't care bits ts18 ts19 ts20 don't care bits ts21 ts22 ts23 e1 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 369 see figure 106 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in mvip 2.048mbit/s mode. the timing diagram of input signals to the framer when running at mvip 2.048mbit/s mode is shown in figure 107. 8.1.3.2 t1 receive input interface - 4.096 mhz this interface mode is the same as running at 2.048 mhz. the only difference is that the receive serial clock runs two times faster at 4.096 mhz. f igure 106. i nterfacing XRT86L34 to local t erminal e quipment using mvip 2.048m bit / s d ata b us f igure 107. t iming d iagram of i nput signals to the f ramer when running at mvip 2.048m bit / s [ rxserclk_0 (2.048mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxserclk_3 (2.048mhz) rxser_3 rxmsync_3 rxsync_3 rxserclk rxserclk(inv) rxser rxsync(input) rxsync(input) (mvip) rxchn[0]/rxsig rxchn[1]/frrxd rxchclk (rxsyncfrtd=1) rxchclk(inv) rxchclk (rxsyncfrtd=1) timeslot 2 f timeslot 3 timeslot 4 timeslot 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d c a b d c a b d c a b d c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 rxchn[2]/rxchn
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 370 when the receive multiplex enable bit is set to zero and the receive interface mode select [1:0] bits are set to 10, the receive back-plane interface of framer is running at a clock rate of 4.096mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_n at an e1 equivalent data rate of 2.048mbit/s. the local terminal equipment supplies a free-running 4.096mhz clock to the receive serial clock input. the receive high-speed back-plane interface of the framer then sends out serial data at every other rising edge of the receive serial clock. the local terminal equipment samples the serial data at every other falling edge of the clock. the terminal equipment take in data grouped in 256-bit frame 8000 times every second. each frame consists of thirty-two octets as in e1. the receive high-speed back-plane interface maps a 193-bit t1 frame into this 256-bit format as described below: 1. the f-bit is mapped into msb of the first e1 time-slot. the framer will insert seven "don't care" bits to the rest of the first octet that would be ignored by the local terminal equipment. 2. payload data of t1 time-slot 0, 1 and 2 are mapped into e1 time-slot 1, 2 and 3. 3. the receive high-speed back-plane interface will stuff e1 time-slot 4 with eight "don't care" bits that would be ignored by the local terminal equipment. 4. following the same rules of step 2 and 3, the receive high-speed back-plane interface maps every three time-slots of t1 payload data into four e1 time-slots. the mapping of t1 frame into e1 framing format is shown in the table below. the receive single-frame synchronization input signal (rxsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse of the receive single-frame synchro- nization signal, the framer can identity the beginning of a ds1 frame and start pumping payload data out. t able 180: t he mapping of t1 frame into e1 framing format t1 f-bit ts0 ts1 ts2 don't care bits ts3 ts4 ts5 e1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 t1 don't care bits ts6 ts7 ts8 don't care bits ts9 ts10 ts11 e1 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 t1 don't care bits ts12 ts13 ts14 don't care bits ts15 ts16 ts17 e1 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 t1 don't care bits ts18 ts19 ts20 don't care bits ts21 ts22 ts23 e1 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 371 see figure 108 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in 4.096mbit/s mode. the timing diagram of input signals to the framer when running at 4.096mbit/s mode is shown in figure 109. 8.1.3.3 t1 receive input interface - 8.192 mhz this interface mode is the same as running at 2.048 mhz. the only difference is that the receive serial clock runs four times faster at 8.192mhz. when the receive multiplex enable bit is set to zero and the receive interface mode select [1:0] bits are set to 11, the receive back-plane interface of framer is running at a clock rate of 8.192mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) f igure 108. i nterfacing XRT86L34 to local t erminal e quipment using 4.096m bit / s d ata b us f igure 109. t iming d iagram of i nput signals to the f ramer when running at 4.096m bit / s rxserclk_0 (4.096mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxserclk_3 (4.096mhz) rxser_3 rxmsync_3 rxsync_3 rxser rxsync(input) rxchclk(inv) rxchn[0]/rxsig rxchn[1]/rxfrtd f 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the rxchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care don't care don't care rxserclk (4mhz)
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 372 ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_n at an e1 equivalent data rate of 2.048mbit/s. the local terminal equipment supplies a free-running 8.192mhz clock to the receive serial clock input. the receive high-speed back-plane interface of the framer then sends out serial data at every other four rising edge of the receive serial clock. the local terminal equipment samples the serial data at ev- ery other four falling edge of the clock. the terminal equipment take in data grouped in 256-bit frame 8000 times every second. each frame consists of thirty-two octets as in e1. the receive high-speed back-plane interface maps a 193-bit t1 frame into this 256-bit format as described below: 1. the f-bit is mapped into msb of the first e1 time-slot. the framer will insert seven "don't care" bits to the rest of the first octet that would be ignored by the local terminal equipment. 2. payload data of t1 time-slot 0, 1 and 2 are mapped into e1 time-slot 1, 2 and 3. 3. the receive high-speed back-plane interface will stuff e1 time-slot 4 with eight "don't care" bits that would be ignored by the local terminal equipment. 4. following the same rules of step 2 and 3, the receive high-speed back-plane interface maps every three time-slots of t1 payload data into four e1 time-slots. the mapping of t1 frame into e1 framing format is shown in the table below. the receive single-frame synchronization input signal (rxsync_n) should pulse high at the beginning of the 256-bit frame indicating start of the frame. by sampling the high pulse of the receive single-frame synchro- nization signal, the framer can identity the beginning of a ds1 frame and start pumping payload data out. t able 181: t he mapping of t1 frame into e1 framing format t1 f-bit ts0 ts1 ts2 don't care bits ts3 ts4 ts5 e1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 t1 don't care bits ts6 ts7 ts8 don't care bits ts9 ts10 ts11 e1 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 t1 don't care bits ts12 ts13 ts14 don't care bits ts15 ts16 ts17 e1 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 t1 don't care bits ts18 ts19 ts20 don't care bits ts21 ts22 ts23 e1 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 373 see figure 110 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in 8.192mbit/s mode. the timing diagram of input signals to the framer when running at 8.192mbit/s mode is shown in figure 111. 8.1.3.4 t1 receive input interface - multiplexed 12.352mbit/s when the receive multiplex enable bit is set to one and the receive interface mode select [1:0] bits are set to 00, the receive back-plane interface of framer is running at a clock rate of 12.352mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) f igure 110. i nterfacing XRT86L34 to local t erminal e quipment using 8.192m bit / s d ata b us f igure 111. t iming d iagram of i nput signals to the f ramer when running at 8.192m bit / s rxserclk_0 (8.192mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0 receive payload data input interface chn 3 terminal equipment XRT86L34 rxserclk_3 (8.192mhz) rxser_3 rxmsync_3 rxsync_3 rxser rxsync(input) rxchclk(inv) rxchn[0]/rxsig rxchn[1]/rxfrtd f 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with the signals shown above. the rxchclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 rxserclk (8mhz) don't care don't care
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 374 ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping data through rxser_0 or rxser_4 pins at 12.352mbit/s. it multi- plexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. free-running clocks of 12.352mhz are supplied to the receive serial clock pin of channel 0 and channel 4 of the framer. the receive high-speed back-plane interface of the farmer provides data at rising edge of this re- ceive serial clock. the local terminal equipment then latches incoming serial data at falling edge of the clock. the receive high-speed back-plane interface multiplexes four 1.544mbit/s ds1 data streams into this 12.352mbit/s data stream as described below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. f x : f-bit of channel x 2. payload data of four channels are repeated and grouped together in a bit-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of channel 3 is sent last. after the first bits of timeslot 0 of all four channels are sent, it comes the second bit of timeslot 0 of channel 0 and so on. the table below demon- strates how payload bits of four channels are mapped into the 12.352mbit/s data stream. x y : the xth payload bit of channel y 3. the receive high-speed back-plane interface also multiplexed signaling bits with payload bits and sent them together through the 12.352mbit/s data stream. when receive high-speed back-plane interface is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth payload bit of a particular channels is followed by the signal- ing bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. first octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 second octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 third octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 375 the following table illustrates how payload bits and signaling bits are multiplexed together into the 12.352mbit/ s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 4. following the same rules of step 2 and 3, the receive high-speed back-plane interface maps the payload data and signaling data of four channels into a 12.352mbit/s data stream. the receive single-frame synchronization signal of channel 0 pulses high for one clock cycle at the first bit position (f-bit of channel 0) of the data stream with data from channel 0-3 multiplexed together. the receive single-frame synchronization signal of channel 4 pulses high for one clock cycle at the first bit position (f-bit of channel 4) of the data stream with data from channel 4-7 multiplexed together. by sampling the high pulse of the receive single-frame synchronization signal, the receive high-speed back-plane interface of the fram- er can identify the beginning of a multiplexed frame and can start sending payload data of that frame. sixth octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 seventh octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 eighth octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3 nineth octet of 12.352mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 376 see figure 112 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in 12.352mbit/s mode. the input signal timing is shown in figure 113 below when the framer is running at 12.352mbit/s mode. 8.1.3.5 t1 receive input interface - bit-multiplexed 16.384mbit/s when the receive multiplex enable bit is set to one and the receive interface mode select [1:0] bits are set to 01, the receive back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_0 or rxser_4 pins at 16.384mbit/s. it multiplexes payload and signaling data of every four channels into one data stream. payload and signaling da- ta of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. f igure 112. i nterfacing XRT86L34 to local t erminal e quipment using 12.352m bit / s d ata b us f igure 113. t iming d iagram of i nput signals to the f ramer when running at 12.352m bit / s rxserclk_0 (12.352mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0-3 terminal equipment XRT86L34 rxserclk (12.352mhz) rxserclk (inv) rxser rxsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 377 free-running clocks of 16.384mhz are supplied to the receive serial clock pin of channel 0 and channel 4 of the framer. the receive high-speed back-plane interface of the farmer provides data at rising edge of this re- ceive serial clock. the local terminal equipment then latches incoming serial data at falling edge of the clock. the receive high-speed back-plane interface maps four 1.544mbit/s ds1 data streams into this 16.384mbit/s data stream as described below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. f x : f-bit of channel x 2. after the first octet of data is sent, the receive high-speed back-plane interface should insert seven octets (fifty-six bits) of "don't care" data into the outgoing data stream. 3. payload data of four channels are repeated and grouped together in a bit-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of channel 3 is sent last. after the first bits of timeslot 0 of all four channels are sent, it comes the second bit of timeslot 0 of channel 0 and so on. the table below demon- strates how payload bits of four channels are mapped into the 16.384mbit/s data stream. xy: the xth payload bit of channel y 4. the receive high-speed back-plane interface also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the receive high-speed back-plane interface is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth payload bit of a particular channels is followed by the sig- naling bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 ninth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 tenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 378 the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/ s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 5. after payload bits of timeslot 0, 1 and 2 of all four channels are sent, the receive high-speed back-plane interface should stuff another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream. 6. following the same rules of step 2 to 5, the receive high-speed back-plane interface stuffs eight octets of "don't care" data after sending twenty-four octets of multiplexed payload and signaling data. a 16.384mbit/ s data stream is thus created. the receive single-frame synchronization signal of channel 0 pulses high for one clock cycle at the first bit position (f-bit of channel 0) of the data stream with data from channel 0-3 multiplexed together. the receive single-frame synchronization signal of channel 4 pulses high for one clock cycle at the first bit position (f-bit of channel 4) of the data stream with data from channel 4-7 multiplexed together. by sampling the high pulse of the receive single-frame synchronization signal, the receive high-speed back-plane interface of the fram- er can identify the beginning of a multiplexed frame and can start sending payload data of that frame. thirteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 fourteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 fifteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3 sixteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 379 see figure 114 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in bit-multiplexed 16.384mbit/s mode. the input signal timing is shown in figure 115 below when the framer is running at bit-multiplexed 16.384mbit/ s mode. 8.1.3.6 t1 receive input interface - hmvip 16.384mbit/s when the receive multiplex enable bit is set to one and the receive interface mode select [1:0] bits are set to 10, the receive back-plane interface of framer is running at a clock rate of 16.384mhz. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_0 or rxser_4 pins at 16.384mbit/s. the receive high-speed back-plane interface multiplexes payload and signaling data of every four channels into f igure 114. i nterfacing XRT86L34 to local t erminal e quipment using 16.384m bit / s d ata b us f igure 115. t iming d iagram of i nput signals to the f ramer when running at b it - multiplexed 16.384m bit / s rxserclk_0 (16.384mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0-3 terminal equipment XRT86L34 rxserclk (16.384mhz) rxserclk (inv) rxser rxsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 56 cycles
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 380 one data stream. payload and signaling data of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. free-running clocks of 16.384mhz are supplied to the receive serial clock pin of channel 0 and channel 4 of the framer. the receive high-speed back-plane interface of the farmer provides data at rising edge of this re- ceive serial clock. the local terminal equipment then latches incoming serial data at falling edge of the clock. the receive high-speed back-plane interface maps four 1.544mbit/s ds1 data streams into this 16.384mbit/s data stream as described below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. fx: f-bit of channel x 2. after the first octet of data is sent, the receive high-speed back-plane interface insert seven octets (fifty- six bits) of "don't care" data into the outgoing data stream. 3. payload data of four channels are repeated and grouped together in a byte-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the terminal equipment will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how payload bits of four channels are mapped into the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 ninth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 eleventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 thirteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 381 xy: the xth payload bit of channel y 4. the receive high-speed back-plane interface also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the receive high-speed back-plane interface is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth payload bit of a particular channels is followed by the sig- naling bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/ s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y fifteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3 tenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0 twelfth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 fourteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2 sixteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 382 5. after payload bits of timeslot 0, 1 and 2 of all four channels are sent, the receive high-speed back-plane interface should stuff another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream. 6. following the same rules of step 2 to 5, receive high-speed back-plane interface stuffs eight octets of "don't care" data after sending twenty-four octets of multiplexed payload and signaling data. a 16.384mbit/ s data stream is thus created. the receive single-frame synchronization signal should pulse high for four clock cycles (the last two bit po- sitions of the previous multiplexed frame and the first two bits of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the receive single-frame synchronization signal of channel 0 puls- es high to identify the start of multiplexed data stream of channel 0-3. the receive single-frame synchroni- zation signal of channel 0 pulses high to identify the start of multiplexed data stream of channel 0-3. by sam- pling the high pulse of the receive single-frame synchronization signal, the receive high-speed back-plane interface of the framer can identify the beginning of a multiplexed frame and can start sending payload data of that frame. see figure 116 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 117 below when the framer is running at hmvip 16.384mbit/s mode. f igure 116. i nterfacing XRT86L34 to local t erminal e quipment using 16.384m bit / s d ata b us f igure 117. t iming d iagram of i nput signals to the f ramer when running at hmvip 16.384m bit / s rxserclk_0 (16.384mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0-3 terminal equipment XRT86L34 rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig rxsync(input) hmvip, negative sync rxsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 383 8.1.3.7 t1 receive input interface - h.100 16.384mbit/s when the receive multiplex enable bit is set to one and the receive interface mode select [1:0] bits are set to 11, the receive back-plane interface of framer is running at h.100 16.384mbit/s mode. the hmvip mode and the h.100 mode are essential the same except for the high pulse position of the re- ceive single-frame synchronization signal. the interface consists of the following pins: ? data input (rxser_n) ? receive serial clock input signal (rxserclk_n) ? receive single-frame synchronization input signal (rxsync_n) ? receive input clock (rxinclk_n) ? receive time-slot indication clock (rxtsclk_n) ? receive time slot indicator bits (rxtsb[4:0]_n) the receive back-plane interface is pumping out data through rxser_0 or rxser_4 pins at 16.384mbit/s. the receive high-speed back-plane interface multiplexes payload and signaling data of every four channels into one data stream. payload and signaling data of channel 0-3 are multiplexed onto the receive serial data pin of channel 0. payload and signaling data of channel 4-7 are multiplexed onto the receive serial data pin of channel 4. free-running clocks of 16.384mhz are supplied to the receive serial clock pin of channel 0 and channel 4 of the framer. the receive high-speed back-plane interface of the farmer provides data at rising edge of this re- ceive serial clock. the local terminal equipment then latches incoming serial data at falling edge of the clock. the receive high-speed back-plane interface maps four 1.544mbit/s ds1 data streams into this 16.384mbit/s data stream as described below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. the f-bit of channel 0 is sent first, followed by f-bit of channel 1 and 2. the f-bit of channel 3 is sent last. the table below shows bit-pattern of the first octet. f x : f-bit of channel x 2. after the first octet of data is sent, the receive high-speed back-plane interface insert seven octets (fifty- six bits) of "don't care" data into the outgoing data stream. 3. payload data of four channels are repeated and grouped together in a byte-interleaved way. the first pay- load bit of timeslot 0 of channel 0 is sent first, followed by the second payload bit of timeslot 0 of channel 0 and so on. after all the bits of timeslot 0 of channel 0 is sent repeatedly, the receive high-speed back- plane interface will start sending the payload bits of timeslot 0 of channel 1 and 2. the payload bits of timeslot 0 of channel 3 are sent the last. after the payload bits of timeslot 0 of all four channels are sent, first octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 384 it comes the payload bits of timeslot 1 of channel 0 and so on. the table below demonstrates how pay- load bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y 4. the receive high-speed back-plane interface also multiplexed signaling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the receive high-speed back-plane interface is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit a of that particular channel. similarly, the sixth payload bit of a particular channels is followed by the sig- naling bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bit d. the following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384mbit/ s data stream. ninth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 eleventh octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 thirteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 fifteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3 tenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 0 a 0 6 0 b 0 7 0 c 0 8 0 d 0
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 385 x y : the xth payload bit of channel y a y : the signaling bit a of channel y 5. after payload bits of timeslot 0, 1 and 2 of all four channels are sent, the terminal equipment should stuff another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream. 6. following the same rules of step 2 to 5, the receive high-speed back-plane interface stuffs eight octets of "don't care" data after sending twenty-four octets of multiplexed payload and signaling data. a 16.384mbit/ s data stream is thus created. the receive single-frame synchronization signal should pulse high for two clock cycles (the last bit position of the previous multiplexed frame and the first bit position of the next multiplexed frame) indicating frame boundary of the multiplexed data stream. the receive single-frame synchronization signal of channel 0 puls- es high to identify the start of multiplexed data stream of channel 0-3. the receive single-frame synchroni- zation signal of channel 0 pulses high to identify the start of multiplexed data stream of channel 0-3. by sam- pling the high pulse of the receive single-frame synchronization signal, the receive high-speed back-plane interface of the framer can identify the beginning of a multiplexed frame and can start sending payload data of that frame. twelfth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 1 a 1 6 1 b 1 7 1 c 1 8 1 d 1 fourteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 2 a 2 6 2 b 2 7 2 c 2 8 2 d 2 sixteenth octet of 16.384mbit/s data stream b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 5 3 a 3 6 3 b 3 7 3 c 3 8 3 d 3
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 386 see figure 118 below for how to interface the local terminal equipment with the receive payload data output interface block of the framer in hmvip 16.384mbit/s mode. the input signal timing is shown in figure 119 below when the framer is running at h.100 16.384mbit/s mode. 8.2 ds1 r eceive f ramer b lock 8.2.1 how to configure XRT86L34 to operate in ds1 mode the XRT86L34 octal t1/e1/j1 framer supports ds1, j1 or e1 framing modes. since j1 standard is very sim- ilar to ds1 standard with a few minor changes, the j1 framing mode is included as a sub-set of the ds1 fram- ing mode. all four framers within the XRT86L34 silicon can be individually configured to support ds1, j1 or e1 framing modes. n ote : if transmitting section of one framer is configured to support either one of the framing modes, the receiving section is automatically configured to support the same framing modes. f igure 118. i nterfacing XRT86L34 to local t erminal e quipment using 16.384m bit / s d ata b us f igure 119. t iming d iagram of i nput signals to the f ramer when running at h.100 16.384m bit / s rxserclk_0 (16.384mhz) rxser_0 rxmsync_0 rxsync_0 receive payload data input interface chn 0-3 terminal equipment XRT86L34 rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 a 0 6 0 b 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 0 c 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig start of frame x y : x is the bit number and y is the channel number rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync delayer h.100 rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 387 the t1/e1 select bit of the clock select register (csr) controls which framing mode supported by the framer. the table below illustrates configurations of the t1/e1 select bit of the clock select register (csr). since j1 and ds1 are two very similar standards, to configure the framer to run in j1 mode, the user has to se- lect ds1 mode by setting the t1/e1 select bit of the clock select register to 1 first. the next step is to set the j1 crc calculation bit of the framing select register (fsr). if this bit is set to 1, the XRT86L34 will do crc-6 calculation in j1 mode. that is, the crc-6 calculation is based on the actual val- ues of all 4,632 bits in ds1 multi-frame including framing bits. if this bit is set to 0, the XRT86L34 will perform crc-6 calculation in ds1 mode. that is, the crc-6 calculation is done based on the actual values of 4,608 payload bits of a ds1 multi-frame and assumes that all the framing bits are one. the table below shows configurations of the j1 crc calculation bit of the framing select register (fsr). the table below provides summary of how to select different operating modes for the XRT86L34 framer. the purpose of the ds1 receive framer block is to accept framed ds1 data from the receive ds1 liu inter- face block. the receive framer block will identify frame boundary and establish framing alignment synchroni- zation of the incoming ds1 frame. the receive framer block will then decode and extract user payload data from received frames please note that the XRT86L34 has four (4) individual ds1 transmit framer blocks. hence, the following description applies to all four of these individual transmit ds1 framer blocks. the purpose of the ds1 receive framer block is: ? to identify frame boundary and establish framing alignment synchronization. ? to decode user data, inputted from the receive ds1 liu interface block to the terminal equipment. ? to provide individual data control and signaling conditioning of each ds0 channel. ? to support the receiving and extraction of hdlc messages, from the remote receiving terminal. ? to detect error conditions and generate indications and interrupts to notify the user that the local receive framer has received error frames from the remote terminal. clock select register (csr) (address = 0xn100h) b it n umber b it n ame b it t ype b it d escription 6 t1/e1 select r/w 0 - the XRT86L34 framer is running in e1 mode. 1 - the XRT86L34 framer is running in t1 mode. framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 5 j1 crc calculation r/w in j1 format, crc-6 calculation is done based on the actual values of all payload bits as well as the framing bits. in ds1 format, crc-6 calculation is done based on the payload bits only while assuming all the framing bits are one. 0 - the framer will perform crc-6 calculation in ds1 format. 1 - the framer will perform crc-6 calculation in j1 format. this feature permits the driver to comply with j1 standard. t1/e1 s elect bit of csr j1 crc c alculation bit of fsr t1 set to 1 set to 0 j1 set to 1 set to 1 e1 set to 0 -
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 388 ? to receive and decode alarm condition indicators from the remote terminal. the following sections discuss functionalities of the ds1 receive framer block in details. 8.2.2 how to configure the framer to receive data in various ds1 framing formats the XRT86L34 octal t1/e1/j1 framer supports the following ds1 framing formats: ? super-frame format (sf), also referred to as d4 framing ? extended super-frame format (esf) ? non-signaling format (n) ? t1dm framing format ? slc?96 data link framing format, which use the super-frame (sf) framing structure n ote : if the framer is configured to receive ds1 frames according to one particular framing format, the transmitting side of the framer is also configured to transmit ds1 frames according to the same framing format. the user can set the framing format select [2:0] bits of the framing select register (fsr) to determine which ds1 framing format should XRT86L34 be configured to operate. the table below shows configurations of the framing format select [2:0] bits of the framing select register (fsr). 8.2.3 how to configure the framer to apply data and signaling conditioning to received ds1 pay- load data on a per-channel basis the XRT86L34 t1/j1/e1 octal framer provides individual control of each of the twenty-four ds0 channels. the user can apply data and signaling conditioning to the received ds1 payload data coming from the ds1 liu receive block on a per-channel basis. the XRT86L34 framer can apply the following changes to the received ds1 payload data coming from the ter- minal equipment on a per-channel basis: ? all 8 bits of the received payload data are inverted ? the even bits of the received payload data are inverted ? the odd bits of the received payload data are inverted ? the msb of the received payload data is inverted ? all received payload data except the msb are inverted framing select register (fsr) (address = 0xn107h) b it n umber b it n ame b it t ype b it d escription 2-0 t1 framing select r/w these read/write bit-fields allow the user to select one of the five t1 framing formats supported by the framer. these framing formats include esf, slc ? 96, sf, n and t1dm mode. n ote : changing of framing format will automatically force the framer to per- form re-synchronization. 0 x x bit 2 bit 1 bit 0 1 0 0 1 0 1 1 1 0 1 1 1 framing format esf slc?96 sf n t1dm
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 389 configurations of the XRT86L34 framer to apply the above-mentioned changes to the received ds1 payload data are controlled by the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of each ds0 channel. the XRT86L34 framer can also replace the incoming ds1 payload data from the ds1 liu receive block with pre-defined or user-defined codes. the XRT86L34 supports the following conditioning substitutions: ? busy code - an octet with hexadecimal value of 0x7f ? busy_ts code - an octet of pattern "111xxxxx" where "xxxxx" represents the timeslot number ? vacant code - an octet with hexadecimal value of 0xff ? a-law digital milliwatt code ? u-law digital milliwatt code ? idle code - an octet defined by the value stored in the user idle code register (ucr) ? moof code - mux-out-of-frame code with hexadecimal value of 0x1a ? prbs code - an octet generated by the pseudo-random bit sequence (prbs) generator block of the framer once again, configuration of the XRT86L34 framer to replace the received ds1 payload data with the above- mentioned coding schemes are controlled by the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of each ds0 channel. finally, the XRT86L34 framer can configure any one or ones of the twenty-four ds0 channels to be d or e channels. d channel is used primarily for data link applications. e channel is used primarily for signaling for cir- cuit switching with multiple access configurations. the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of each channel determine whether that particular channel is configured as d or e channel.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 390 the table below illustrates configurations of the receive data conditioning select [3:0] bits of the receive channel control register (rccr). when the receive data conditioning select [3:0] bits of the receive channel control register (rccr) of a particular ds0 channel are set to 0100, the received ds1 payload data of this ds0 channel are replaced by the octet stored in the receive user idle code register (rucr). the table below shows contents of the receive user idle code register. 8.2.4 how to configure the XRT86L34 framer to apply zero code suppression to received ds1 pay- load data on a per-channel basis in order to guarantee adequate clock recovery from the received pcm data, a minimum "ones density" must be maintained. in the case of an all zero channel, that is, if all the incoming pcm data of a particular ds0 channel from the terminal equipment is zero, the raw pcm data is replaced by a certain pattern that no more than fif- teen consecutive zeros will occur. it is known as zero code suppression. receive channel control register (rccr) (address = 0xn360h - 0xn37fh) b it n umber b it n ame b it t ype b it d escription 3-0 receive conditioning select r/w 0000 - the received ds1 payload data of this ds0 channel is unchanged. 0001 - all 8 bits of the input ds1 payload data of this ds0 channel are inverted. 0010 - the even bits of the input ds1 payload data of this ds0 channel are inverted. 0011 - the odd bits of the input ds1 payload data of this ds0 channel are inverted. 0100 - the input ds1 payload data of this ds0 channel are replaced by the octet stored in user idle code register (ucr). 0101 - the input ds1 payload data of this ds0 channel are replaced by busy code (0x7f). 0110 - the input ds1 payload data of this ds0 channel are replaced by vacant code (0xff). 0111 - the input ds1 payload data of this ds0 channel are replaced by busy_ts code (111xxxxx). 1000 - the input ds1 payload data of this ds0 channel are replaced by mux- out-of-frame (moof) code with value 0x1a. 1001 - the input ds1 payload data of this ds0 channel are replaced by the a-law digital milliwatt pattern. 1010 - the input ds1 payload data of this ds0 channel are replaced by the u-law digital milliwatt pattern. 1011 - the msb bit of the input ds1 payload data of this ds0 channel is inverted. 1100 - all bits of the input ds1 payload data of this ds0 channel except msb bit are inverted. 1101 - the input ds1 payload data of this ds0 channel are replaced by prbs pat- tern created by the internal prbs generator of XRT86L34 framer. 1110 - the input ds1 payload data of this ds0 channel is unchanged. 1111 - this channel is configured as d or e timeslot. receive user idle code register (ucr) (address = 0xn380h - 0xn397h) b it n umber b it n ame b it t ype b it d escription 7-0 user idle code r/w these read/write bit-fields permits the user store any value of idle code into the framer. when the receive data conditioning select [3:0] bits of rccr register of a particular ds0 channel are set to 0100, the received ds1 payload data are replaced by contents of this register and sent to the terminal equipment.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 391 in the receive end, the user needs to know what type of zero code suppression scheme is applied on the re- ceiving data. in this way, a correct decoding method or the reverse of zero code suppression can be done to extract the payload data from the ds1 liu receive block. the XRT86L34 framer supports three types of zero code suppression schemes: ? at&t bit 7 stuffing - an old coding method that forces bit 7 (the second lsb of a ds0 channel) to a 1 in an all zero channel. ? gte zero code suppression - bit 8 (the lsb of a ds0 channel) is stuffed by 1 in non-signaling frame in an all zero channel. otherwise, bit 7 is stuffed by 1 in signaling frame if the signaling bit is zero. ? dds zero code suppression - an octet with hexadecimal value of 0x98 is used to replace the input data if it is all zero. the receive zero code suppression select [1:0] bits of the receive channel control register (rccr) of a particular ds0 channel is used to select which type of zero code suppression scheme is applied to the re- ceived ds1 payload data. the table below shows configurations of the receive zero code suppression select [1:0] bits of the receive channel control register (rccr). 8.2.5 how to configure the XRT86L34 framer to extract robbed-bit signaling information the XRT86L34 t1/j1/e1 octal framer supports insertion of robbed-bit signaling information into the outgoing ds1 frame. it also supports extraction and substitution of robbed-bit signaling information from the incoming ds1 frame. the following section describes how does the XRT86L34 framer extract and substitute robbed-bit signaling in ds1 mode. 8.2.6 configure the framer to receive and extract robbed-bit signaling the XRT86L34 framer supports receiving and extraction of robbed-bit signaling in esf, sf and slc?96 framing formats. the receive signaling extraction control [1:0] bits of the receive signaling control register (rscr) of each channel select either: ? no signaling extraction ? two-code signaling ? four-code signaling or ? sixteen-code signaling in sf or slca96 mode, the receive signaling extraction control [1:0] bits can select no signaling (transpar- ent), two-code signaling, or four-code signaling. two-code signaling decoding is done by stripping the least sig- nificant bit (lsb) of the specific channel in frame 6 and 12 and stores it into the signaling bit a position of rsra register array. four-code signaling is done by stripping the lsb of channel data in frame 6 and the lsb of channel data in frame 12, and store them into signaling bit a and signaling bit b position of rsra register array respectively. if 16-code signaling is selected in sf format, only the signaling bit a and signaling bit b po- sitions are filled. in esf mode, the receive signaling extraction control [1:0] bits can select no signaling (transparent), two- code signaling, four-code, or sixteen-code signaling. two-code signaling decoding is done by stripping the least significant bit (lsb) of the specific channel in frame 6, 12, 18 and 24 and stores it into the signaling bit a position of rsra register array. four-code signaling is done by stripping the lsb of channel data in frame 6 and frame 18 and the lsb of channel data in frame 12 and 24, and store them into signaling bit a and signal- ing bit b position of rsra register array respectively. sixteen-code signaling is implemented by stripping the receive channel control register (rccr) (address = 0xn360h - 0xn37fh) b it n umber b it n ame b it t ype b it d escription 5-4 receive zero code suppression select r/w 00 - the received ds1 payload data of this ds0 channel is unchanged. no zero code suppression is used. 01 - at&t bit 7 stuffing is used. 10 - gte zero code suppression is used. 11 - dds zero code suppression is used.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 392 lsb of channel data in frames 6, 12, 18, and 24 and stores them into the signaling bit a, signaling bit b, sig- naling bit c and signaling bit d position of rsra register array respectively. the table below shows configurations of the receive signaling extraction control [1:0] bits of the receive sig- naling control register. upon receiving and extraction of signaling bits from the incoming ds1 frames, the XRT86L34 framer compares the signaling bits with the previously received ones. if there is a change of signaling data, a signaling update (sig) interrupt request may be generated at the end of a ds1 multi-frame. the user can thus be notified of a change of signaling data event. to enable the signaling update interrupt, the signaling change interrupt enable bit of the framer interrupt en- able register (fier) has to be set. in addition, the t1/e1 framer interrupt enable bit of the block interrupt en- able register (bier) needs to be one. the table below shows configurations of the signaling change interrupt enable bit of the framer interrupt en- able register. the table below shows configurations of the t1/e1 framer interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and the signaling information received is changed, the ds1 receive framer block will set the signaling updated status bit of the framer interrupt status register (fisr) to one. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control register (icr). otherwise, a write-to- clear operation by the microprocessor is required to reset these status indicators. receive signaling control register (rscr) (address = 0xn3a0h - 0xn3b7h) b it n umber b it n ame b it t ype b it d escription 1-0 signaling extraction control r/w 00 - the XRT86L34 framer does not extract signaling information from incoming ds1 payload data. 01 - the XRT86L34 framer extracts sixteen-code signaling information from incoming ds1 payload data. 10 - the XRT86L34 framer extracts four-code signaling information from incom- ing ds1 payload data. 11 - the XRT86L34 framer extracts two-code signaling information from incom- ing ds1 payload data. framer interrupt enable register (fier) (address = 0xnb05h) b it n umber b it n ame b it t ype b it d escription 5 signaling change interrupt enable r/w 0 - the signaling update interrupt is disabled. 1 - the signaling update interrupt is enabled. block interrupt enable register (bier) (address = 0xnb00h) b it n umber b it n ame b it t ype b it d escription 1 t1/e1 framer inter- rupt enable r/w 0 - every interrupt generated by the framer interrupt status register (fisr) is dis- abled. 1 - every interrupt generated by the framer interrupt status register (fisr) is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 393 the table below shows the signaling update status bits of the framer interrupt status register. now, there is only one problem remains. since there are twenty-four ds0 channels in ds1, how do we know signaling information of which channel is changed? to solve this problem, the XRT86L34 provides three 8-bit signaling change registers to indicate the chan- nel(s) which signaling data change had occurred over the last ds1 multi-frame period. each bit of the signaling change registers represents one timeslot of the ds1 frame. if any particular bit is zero, it means there is no change of signaling data occurred in that particular timeslot over the last ds1 multi-frame period. if any partic- ular bit is one, it means there is change of signaling data occurred over the last ds1 multi-frame period. the table below shows configurations of the signaling change registers. by reading contents of the signaling update status bits of the framer interrupt status register and the signal- ing change registers, the user can clearly identify which one(s) of the twenty-four ds0 channels has changed signaling information over the last multi-frame period. depending on configurations of the XRT86L34 framer, the signaling bits can be extracted from the incoming ds1 frame and direct to all or any one of the following destinations: ? signaling data is stored to receive signaling register array (rsra) of each channel ? signaling data is sent to the terminal equipment through the receive signaling output pin (rxsig_n) ? signaling data is embedded into the output pcm data sending towards the terminal equipment through the receive serial output pin (rxser_n) the follow sections discuss how to configure the XRT86L34 framer to extract signaling information bits and send them to different destinations. 8.2.6.1 store signaling bits into rsra register array the four least significant bits of the receive signaling register array (rsra) of each timeslot can be used to store received signaling data. the user can read these bits through microprocessor access. if the XRT86L34 framer is configure to extract signaling bits from incoming ds1 payload data, the ds1 receive framer block will strip off the least significant bits of signaling frames and store them into appropriate locations of the rsra. the extraction of signaling bit from ds1 pcm data is done on a per-channel basis. the bit 3 of rsra register is used to hole signaling bit a. bit 2 is used to hold signaling bit b. bit 1 is used to hold signaling bit c. bit 0 is used to hold signaling bit d. framer interrupt status register (fisr) (address = 0xnb04h) b it n umber b it n ame b it t ype b it d escription 5 signaling updated rur / wc 0 - there is no change of signaling information in the incoming ds1 payload data. 1 - there is change of signaling information in the incoming ds1 payload data. signaling change registers (scr) (address = 0xn10dh - 0xn10fh) l ocation \ b it b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 0 xn 10dh c h 0c h 1c h 2c h 3c h 4c h 5c h 6c h 7 0xn10eh ch 8 ch 9 ch 10 ch 11 ch 12 ch 13 ch 14 ch 15 0xn10fh ch 16 ch 17 ch 18 ch 19 ch 20 ch 21 ch 22 ch 23
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 394 the table below shows the four least significant bits of the receive signaling register array. 8.2.6.2 outputting signaling bits through rxsig_n pin the XRT86L34 framer can be configure to output extracted signaling bits to external equipment through the rxsig_n pins. this pin is a multiplexed i/o pin with two functions: ? rxtsb[0]_n - receive timeslot number bit [0] output pin ? rxsig_n - receive signaling output pin when the receive fractional ds1 bit of the receive interface control register (ticr) is set to 0, this pin is configured as rxtsb[0]_n pin, it outputs bit 0 of the timeslot number of the ds1 pcm data that is receiving. when the receive fractional ds1 bit of the receive interface control register (ticr) is set to 1, this pin is configured as rxsig_n pin, it acts as an output source for the signaling bits to be received in the inbound ds1 frames. the table below shows configurations of the receive fractional ds1 bit of the receive interface control reg- ister (ticr). figure 120 below is a timing diagram of the rxsig_n output pin. please note that the signaling bit a of a cer- tain timeslot coincides with bit 3 of the received serial output data; signaling bit b coincides with bit 2 of the receive signaling register array (rsra) (address = 0xn500h - 0xn517h) b it n umber b it n ame b it t ype b it d escription 3 signaling bit a r/w this bit is used to store signaling bit a that is received and extracted as the least significant bit of timeslot of frame number 6. 2 signaling bit b r/w this bit is used to store signaling bit b that is received and extracted as the least significant bit of timeslot of frame number 12. 1 signaling bit c r/w this bit is used to store signaling bit c that is received and extracted as the least significant bit of timeslot of frame number 18. 0 signaling bit d r/w this bit is used to store signaling bit d that is received and extracted as the least significant bit of timeslot of frame number 24. receive interface control register (ticr) (address = 0xn120h) b it n umber b it n ame b it t ype b it d escription 4 receive fractional ds1 r/w this read/write bit-field permits the user to determine which one of the two functions the multiplexed i/o pin of rxtsb[0]_n/rxsig_n is spotting. 0 - this pin is configured as rxtsb[0]_n pin, it outputs bit 0 of the timeslot num- ber of the ds1 pcm data that is receiving. 1 - this pin is configured as rxsig_n pin, it acts as an output source for the signal- ing bits to be received in the inbound ds1 frames
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 395 received serial output data; signaling bit c coincides with bit 1 of the received serial output data and signal- ing bit d coincides with bit 0 of the received serial output data. the receive signaling output enable bit of the receive signaling control register (rscr) determines wheth- er the extracted signaling bits will be sent through the receive signaling output pin (rxsig_n) to external equipments. the table below shows configurations of the receive signaling output enable bit of the receive signaling control register. 8.2.6.3 send signaling data through rxser_n pin as mentioned in the above sections, signaling information embedded in the incoming ds1 pcm data can be sent to either the rsra register array and/or sent through the receive signaling output pin, at the same time, the signaling data will be directed to the receive serial data output pin together with other incoming ds1 pay- load data. the external equipment can thus still extract signaling data from the received ds1 payload data separately. 8.2.6.4 signaling data substitution after channel conditioning, the signaling conditioning can be optionally enabled by the rscr registers. the actual signaling bits in each channel can be replaced either with all ones or with signaling bits stored in the re- ceive substitution signaling register (rssr). to enable signaling substitution, the receive signaling substitu- tion enable bit of the receive signaling control register (rscr) has to be set to one. the table below shows configuration of the receive signaling substitution enable bit of the receive signaling control register. f igure 120. t iming d iagram of the r x s ig _ n o utput pin receive signaling control register (rscr) (address = 0xn3a0h - 0xn3b7h) b it n umber b it n ame b it t ype b it d escription 5 receive signaling output enable r/w 0 - the XRT86L34 framer will not send extracted signaling bits from the incom- ing ds1 payload data to external equipment through the receive signaling output pin (rxsig_n). 1 - the XRT86L34 framer will send extracted signaling bits from the incoming ds1 payload data to external equipment through the receive signaling output pin (rxsig_n). receive signaling control register (rscr) (address = 0xn3a0h - 0xn3b7h) b it n umber b it n ame b it t ype b it d escription 6 receive signaling substitution enable r/w 0 - signaling substitution is disabled. the XRT86L34 framer will not replace extracted signaling bits from the incoming ds1 payload data with all ones or with signaling bits stored in rssr registers. 1 - signaling substitution is enabled. the XRT86L34 framer will replace extracted signaling bits from the incoming ds1 payload data with all ones or with signaling bits stored in rssr registers.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 396 as mentioned before, the actual signaling bits in each channel can be replaced either with all ones or with sig- naling bits stored in the receive substitution signaling register (rssr). the table below shows configura- tions of the receive substitution signaling register. in sf or slc?96 mode, the receive signaling substitution control [1:0] bits can select all ones substitution, two-code signaling substitution, or four-code signaling substitution. the XRT86L34 framer can substitute re- ceived signaling bits with all ones. two-code signaling substitution is done by substituting the least significant bit (lsb) of the specific channel in frame 6 and 12 with the content of the sig2-a bit of the receive substitu- tion signaling register (rssr). four-code signaling substitution is done by substituting the lsb of channel da- ta in frame 6 with the sig4-a bit and the lsb of channel data in frame 12 with the sig4-b bit of the rssr reg- ister. if 16-code signaling substitution is selected in sf format, only the sig16-a bit and sig16-b bit are used. in esf mode, the receive signaling substitution control [1:0] bits can select all ones substitution, two-code signaling substitution, four-code signaling substitution, or sixteen-code signaling. the XRT86L34 framer can substitute received signaling bits with all ones. two-code signaling substitution is done by substituting the lsb of the specific channel in frame 6, 12, 18, and 24 with the content of the sig2-a bit of the register. four-code signaling substitution is done by substituting the lsb of channel data in frames 6 and 18 with the sig4-a bit and the lsb of channel data in frames 12 and 24 with the sig4-b bit of the rssr register. sixteen-code sig- naling substitution is implemented by substituting the lsb of channel data in frames 6, 12, 18, and 24 with the content of sig16-a, sig16-b, sig16-c, and sig16-d bits of rssr register respectively. receive substitution signaling register (rssr) (address = 0xn380h - 0xn397h) b it n umber b it n ame b it t ype b it d escription 7-4 reserved r/w 3 sig16-a sig4-a sig2-a sixteen-code signaling bit a four-code signaling bit a two-code signaling bit a 2 sig16-b sig4-b sig2-a sixteen-code signaling bit b four-code signaling bit b two-code signaling bit a 1 sig16-c sig4-a sig2-a sixteen-code signaling bit c four-code signaling bit a two-code signaling bit a 0 sig16-d sig4-b sig2-a sixteen-code signaling bit d four-code signaling bit b two-code signaling bit a
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 397 the table below shows configurations of the receive signaling substitution control [1:0] bits of the receive signaling control register. receive signaling control register (rscr) (address = 0xn340h - 0xn357h) b it n umber b it n ame b it t ype b it d escription 3-2 receive signaling substitution control r/w 00 - the received signaling bits are replaced by all ones and send to the external equipment. 01 - two-code signaling substitution is applied to the received signaling bits. the replaced signaling information is sent to the external equipment. 10 - four-code signaling substitution is applied to the received signaling bits. the replaced signaling information is sent to the external equipment. 11 - sixteen-code signaling substitution is applied to the received signaling bits. the replaced signaling information is sent to the external equipment. n ote : in sf mode, this option is disabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 398 9.0 liu receive path 9.1 l ine t ermination (rtip/rring) 9.1.1 case 1: internal termination the input stage of the receive path accepts standard t1/e1/j1 twisted pair or e1 coaxial cable inputs through rtip and rring. the physical interface is optimized by placing the terminating impedance inside the liu. this allows one bill of materials for all modes of operation reducing the number of external components neces- sary in system design. the receive termination impedance is selected by programming tersel[1:0] to match the line impedance. selecting the internal impedance is shown in table 182. the XRT86L34 has the ability to switch the internal termination to "high" impedance by programming rxtsel in the appropriate channel register. for internal termination, set rxtsel to "1". by default, rxtsel is set to "0" ("high" impedance). for redundancy applications, a dedicated hardware pin (rxtsel) is also available to control the receive termination for all channels simultaneously. this hardware pin takes priority over the regis- ter setting if rxtcntl is set to "1" in the appropriate global register. if rxtcntl is set to "0", the state of this pin is ignored. see figure 121 for a typical connection diagram using the internal termination. f igure 121. t ypical c onnection d iagram u sing i nternal t ermination 9.1.2 case 2: internal termination with one external fixed resistor for all modes along with the internal termination, a high precision external fixed resistor can be used to optimize the return loss. this external resistor can be used for all modes of operation ensuring one bill of materials. there are three resistor values that can be used by setting the rxres[1:0] bits in the appropriate channel register. se- lecting the value for the external fixed resistor is shown in table 183. t able 182: s electing the i nternal i mpedance tersel[1:0] r eceive t ermination 0h (00) 100 w 1h (01) 110 w 2h (10) 75 w 3h (11) 120 w t able 183: s electing the v alue of the e xternal f ixed r esistor r x res[1:0] e xternal f ixed r esistor 0h (00) none 1h (01) 240 w 2h (10) 210 w 3h (11) 150 w r tip r ring XRT86L34 liu 1:1 internal impedance line interface t1/e1/j1 one bill of materials receiver input
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 399 by default, rxres[1:0] is set to "none" for no external fixed resistor. if an external fixed resistor is used, the XRT86L34 uses the parallel combination of the external fixed resistor and the internal termination as the input impedance. see figure 122 for a typical connection diagram using the external fixed resistor. n ote : without the external resistor, the XRT86L34 meets all return loss specifications. this mode was created to add flex- ibility for optimizing return loss by using a high precision external resistor. f igure 122. t ypical c onnection d iagram u sing o ne e xternal f ixed r esistor 9.1.3 equalizer control the main objective of the equalizer is to amplify an input attenuated signal to a pre-determined amplitude that is acceptable to the peak detector circuit. using feedback from the peak detector, the equalizer will gain the in- put up to the maximum value specified by the equalizer control bits, in the appropriate channel register, nor- malizing the signal. once the signal has reached the pre-determined amplitude, the signal is then processed within the peak detector and slicer circuit. a simplified block diagram of the equalizer and peak detector is shown in figure 123. f igure 123. s implified b lock d iagram of the e qualizer and p eak d etector 9.1.4 cable loss indicator the ability to monitor the cable loss attenuation of the receiver inputs is a valuable feature. the XRT86L34 contains a per channel, read only register for cable loss indication. clos[5:0] is a 6-bit binary word that re- ports the value of cable loss in 1db steps with an absolute accuracy of 1db. an example of -25db cable loss attenuation is shown in figure 124. f igure 124. s implified b lock d iagram of the c able l oss i ndicator r tip r ring XRT86L34 liu 1:1 internal impedance line interface t1/e1/j1 r r=240 w , 210 w , or 150 w receiver input peak detector & slicer rx equalizer rx equalizer control rtip rring -25db of cable loss equalizer and peak detector clos[5:0] = 0x19h (25dec = 19hex) -25db attenuated signal read only XRT86L34
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 400 9.2 r eceive s ensitivity to meet long haul receive sensitivity requirements, the XRT86L34 can accept t1/e1/j1 signals that have been attenuated by 43db cable attenuation in e1 mode or 36db cable attenuation in t1 mode without experi- encing bit errors, lof, pattern synchronization, etc. short haul specifications are for 12db of flat loss in e1 mode. t1 specifications are 655 feet of cable loss along with 6db of flat loss in t1 mode. the XRT86L34 can tolerate cable loss and flat loss beyond the industry specifications. the receive sensitivity in the short haul mode is approximately 4,000 feet without experiencing bit errors, lof, pattern synchronization, etc. although data integrity is maintained, the rlos function (if enabled) will report an rlos condition according to the re- ceiver loss of signal section in this datasheet. the test configuration for measuring the receive sensitivity is shown in figure 125. f igure 125. t est c onfiguration for m easuring r eceive s ensitivity 9.2.1 ais (alarm indication signal) the XRT86L34 adheres to the itu-t g.775 specification for an all ones pattern. the alarm indication signal is set to "1" if an all ones pattern (at least 99.9% ones density) is present for t, where t is 3ms to 75ms in t1 mode. ais will clear when the ones density is not met within the same time period t. in e1 mode, the ais is set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. ais will clear when the incoming signal has 3 or more zeros in the 512-bit window. 9.2.2 nlcd (network loop code detection) the network loop code detection can be programmed to detect a loop-up, loop-down, or automatic loop code. if the network loop code detection is programmed for loop-up, the nlcd will be set "high" if a repeat- ing pattern of "00001" occurs for more than 5 seconds. if the network loop code detection is programmed for loop-down, the nlcd will be set "high" if a repeating pattern of "001" occurs for more than 5 seconds. if the network loop code detection is programmed for automatic loop code, the liu is configured to detect a loop-up code. if a loop-up code is detected for more than 5 seconds, the XRT86L34 will automatically program the channel into a remote loopback mode. the liu will remain in remote loopback even if the loop-up code dis- appears. the channel will continue in remote loop back until a loop-down code is detected for more than 5 seconds (or, if the automatic loop code is disabled) and then automatically return to normal operation with no loop back. the process of the automatic loop code detection is shown in figure 126. network analyzer e1 = prbs 2 15 - 1 t1 = prbs 2 23 - 1 external loopback XRT86L34 8-channel framer/liu cable loss flat loss tx tx rx rx w&g ant20
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 401 f igure 126. p rocess b lock for a utomatic l oop c ode d etection 9.2.3 flsd (fifo limit status detection) the purpose of the fifo limit status is to indicate when the read and write fifo pointers are within a pre-de- termined range (over-flow or under-flow indication). the flsd is set to "1" if the fifo read and write pointers are within 3-bits. 9.2.4 receive jitter attenuator the receive path has a dedicated jitter attenuator to reduce phase and frequency jitter in the recovered clock. the jitter attenuator uses a data fifo (first in first out) with a programmable depth of 32-bit or 64-bit. if the liu is used for line synchronization (loop timing systems), the ja should be enabled in the receive path. when the read and write pointers of the fifo are within 2-bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. when this con- dition occurs, the jitter attenuator will not attenuate input jitter until the read/write pointers position is outside the 2-bit window. in t1 mode, the bandwidth of the ja is always set to 3hz. in e1 mode, the bandwidth is pro- grammable to either 10hz or 1.5hz (1.5hz automatically selects the 64-bit fifo depth). the ja has a clock delay equal to ? of the fifo bit depth. n ote : the transmit path has a dedicated jtter attenuator. see the transmit path line interface section. 9.2.5 rxmute (receiver los with data muting) the receive muting function can be selected by setting rxmute to "1" in the appropriate global register. if se- lected, any channel that experiences an rlos condition will automatically pull the output of the liu section "low" to prevent data chattering. if rlos does not occur, the rxmute will remain inactive until an rlos on a given channel occurs. the default setting for rxmute is "0" which is disabled. a simplified block diagram of the rxmute function is shown in figure 127. automatic remote loopback loop-up code for 5 sec? yes no loop-down code for 5 sec? no yes disable remote loopback
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 402 f igure 127. s implified b lock d iagram of the r x mute f unction rlos rxmute digital output liu framer
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 403 10.0 alarms and error conditions the XRT86L34 t1/j1/e1 octal framer can be configured to monitor quality of received ds1 frames. it can generate error indicators if the local receive framer has received error frames from the remote terminal. if cor- responding interrupt is enabled, the local microprocessor operation is interrupted by these error conditions. upon microprocessor interruption, the user can intervene by looking into the error conditions. at the same time, the user can configure the XRT86L34 framer to transmit alarms and error indications to re- mote terminal. different alarms and error indications will be transmitted depending on the error condition. the section below gives a brief discussion of the error conditions that can be detected by the XRT86L34 fram- er and error indications that will be generated. 10.1 ais a larm as we discussed before, transmission of alarm indication signal (ais) or blue alarm by the intermediate node indicates that the equipment is still functioning but unable to offer services. it is an all ones (except for framing bits) pattern which can be used by the equipment further down the line to maintain clock recovery and timing synchronization. the XRT86L34 framer can detect two types of ais in ds1 mode: ? framed ais ? unframed ais unframed ais is an all ones pattern. if unframed ais is sent, the equipment further down the line will be able to maintain timing synchronization and be able to recover clock from the received ais signal. however, due to the lack of framing bits, the equipment farther down the line will not be able to maintain frame synchronization and will declare loss of frame (lof). on the other hand, the payload portion of a framed ais pattern is all ones. however, a framed ais pattern still has correct framing bits. therefore, the equipment further down the line can still maintain frame synchroniza- tion as well as timing synchronization. in this case, no lof or red alarm will be declared. the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming ds1 frames for ais. ais alarm condition are detected and declared according to the following procedure: 1. the incoming ds1 frames are monitored for ais detection. ais detection is defined as an unframed or framed pattern with less than three zeros in two consecutive frames. 2. an ais detection counter within the receive framer block of the XRT86L34 counts the occurrences of ais detection over a 6 ms interval. it will indicate a valid ais flag when twenty-two or more of a possible twenty- four ais are detected. 3. each 6 ms interval with a valid ais flag increments a flag counter which declares ais alarm when 255 valid flags have been collected. therefore, ais condition has to be persisted for 1.53 seconds before ais alarm condition is declared by the XRT86L34 framer. if there is no valid ais flag over a 6ms interval, the alarm indication logic will decrement the flag counter. the ais alarm is removed when the counter reaches 0. that is, ais alarm will be removed if over 1.53 seconds, there is no valid ais flag. the alarm indication signal detection select [1:0] bits of the alarm generation register (agr) enable the two types of ais detection that are supported by the XRT86L34 framer. the table below shows configurations of the alarm indication signal detection select [1:0] bits of the alarm generation register (agr). alarm generation register (agr) (address = 0xn108h) b it n umber b it n ame b it t ype b it d escription 1-0 ais detection select r/w 00 - ais alarm detection is disabled.when this bit is set to 01:detection of unframed ais alarm of all ones pattern is enabled. 10 - ais alarm detection is disabled.when this bit is set to 00:detection of framed ais alarm of all ones pattern except for framing bits is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 404 if detection of unframed or framed ais alarm is enabled by the user and if ais is present in the incoming ds1 frame, the XRT86L34 framer can generate a receive ais state change interrupt associated with the setting of receive ais state change bit of the alarm and error status register to one. to enable the receive ais state change interrupt, the receive ais state change interrupt enable bit of the alarm and error interrupt enable register (aeier) have to be set to one. in addition, the alarm and error inter- rupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive ais state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and ais is present in the incoming ds1 frame, the XRT86L34 framer will declare ais by doing the following: ? set the read-only receive ais state bit of the alarm and error status register (aesr) to one indicating there is ais alarm detected in the incoming ds1 frame. ? set the receive ais state change bit of the alarm and error status register to one indicating there is a change in state of ais. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive ais state change status bits of the alarm and error status register. the receive ais state bit of the alarm and error status register (aesr), on the other hand, is a read-only bit indicating there is ais alarm detected in the incoming ds1 frame. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 1 receive ais state change interrupt enable r/w 0 - the receive ais state change interrupt is disabled. 1 - the receive ais state change interrupt is enabled. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 1 receive ais state change rur / wc 0 - there is no change of ais state in the incoming ds1 payload data. 1 - there is change of ais state in the incoming ds1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 405 the table below shows the receive ais state status bits of the alarm and error status register. 10.2 r ed a larm the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming ds1 frames for red alarm or loss of frame (lof) condition. red alarm condition are detected and declared according to the following procedure: 1. the red alarm is detected by monitoring the occurrence of loss of frame (lof) over a 6 ms interval. 2. an lof valid flag will be posted on the interval when one or more lof occurred during the interval. 3. each interval with a valid lof flag increments a flag counter which declares red alarm when 63 valid intervals have been accumulated. 4. an interval without valid lof flag decrements the flag counter. the red alarm is removed when the counter reaches zero. if lof condition is present in the incoming ds1 frame, the XRT86L34 framer can generate a receive red alarm state change interrupt associated with the setting of receive red alarm state change bit of the alarm and error status register to one. to enable the receive red alarm state change interrupt, the receive red alarm state change interrupt en- able bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive red alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and red alarm is present in the incoming ds1 frame, the XRT86L34 framer will declare red alarm by doing the following: alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 6 receive ais state r 0 - there is no ais alarm condition detected in the incoming ds1 payload data. 1 - there is ais alarm condition detected in the incoming ds1 payload data. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 2 receive red alarm state change inter- rupt enable r/w 0 - the receive red alarm state change interrupt is disabled. no receive loss of frame (rxlof) interrupt will be generated upon detection of lof condition. 1 - the receive red alarm state change interrupt is enabled. receive loss of frame (rxlof) interrupt will be generated upon detection of lof condition. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 406 ? set the read-only receive red alarm state bit of the alarm and error status register (aesr) to one indicat- ing there is red alarm detected in the incoming ds1 frame. ? set the receive red alarm state change bit of the alarm and error status register to one indicating there is a change in state of red alarm. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive red alarm state change status bits of the alarm and error status regis- ter. the receive red alarm state bit of the alarm and error status register (aesr), on the other hand, is a read- only bit indicating there is red alarm detected in the incoming ds1 frame. the table below shows the receive red alarm state status bits of the alarm and error status register. 10.3 y ellow a larm the alarm indication logic within the receive framer block of the XRT86L34 framer monitors the incoming ds1 frames for yellow alarm condition. the yellow alarm is detected and declared according to the following procedure: 1. monitor the occurrence of yellow alarm pattern over a 6 ms interval. a yel valid flag will be posted on the interval when yellow alarm pattern occurred during the interval. 2. each interval with a valid yel flag increments a flag counter which declares yel alarm when 80 valid intervals have been accumulated. 3. an interval without valid yel flag decrements the flag counter. the yel alarm is removed when the counter reaches zero. if yellow alarm condition is present in the incoming ds1 frame, the XRT86L34 framer can generate a receive yellow alarm state change interrupt associated with the setting of receive yellow alarm state change bit of the alarm and error status register to one. to enable the receive yellow alarm state change interrupt, the receive yellow alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt enable bit of the block interrupt enable register (bier) needs to be one. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 2 receive red alarm state change rur / wc 0 - there is no change of red alarm state in the incoming ds1 payload data. 1 - there is change of red alarm state in the incoming ds1 payload data. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 7 receive red alarm state r 0 - there is no red alarm condition detected in the incoming ds1 payload data. 1 - there is red alarm condition detected in the incoming ds1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 407 the table below shows configurations of the receive yellow alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and yellow alarm is present in the incoming ds1 frame, the XRT86L34 framer will declare yellow alarm by doing the following: ? set the read-only receive yellow alarm state bit of the alarm and error status register (aesr) to one indi- cating there is yellow alarm detected in the incoming ds1 frame. ? set the receive yellow alarm state change bit of the alarm and error status register to one indicating there is a change in state of yellow alarm. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive yellow alarm state change status bits of the alarm and error status reg- ister. the table below shows the receive ais state change status bits of the alarm and error status register. the receive yellow alarm state bit of the alarm and error status register (aesr), on the other hand, is a read-only bit indicating there is yellow alarm detected in the incoming ds1 frame. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 0 receive yellow alarm state change interrupt enable r/w 0 - the receive yellow alarm state change interrupt is disabled. any state change of receive yellow alarm will not generate an interrupt. 1 - the receive yellow alarm state change interrupt is enabled. any state change of receive yellow alarm will generate an interrupt. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr)(address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 0 receive yellow alarm state change rur / wc 0 - there is no change of yellow alarm state in the incoming ds1 payload data. 1 - there is change of yellow alarm state in the incoming ds1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 408 the table below shows the receive yellow alarm state status bits of the alarm and error status register. 10.4 b ipolar v iolation the line coding for the ds1 signal should be bipolar. that is, a binary "0" is transmitted as zero volts while a bi- nary "1" is transmitted as either a positive or negative pulse, opposite in polarity to the previous pulse. a bipo- lar violation or bpv occurs when the alternate polarity rule is violated. the alarm indication logic within the re- ceive framer block of the XRT86L34 framer monitors the incoming ds1 frames for bipolar violations. if a bipolar violation is present in the incoming ds1 frame, the XRT86L34 framer can generate a receive bi- polar violation interrupt associated with the setting of receive bipolar violation bit of the alarm and error sta- tus register to one. to enable the receive bipolar violation interrupt, the receive bipolar violation interrupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt en- able bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive bipolar violation interrupt enable bit of the alarm and er- ror interrupt enable register (aeier). the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and one or more bipolar violations are present in the incoming ds1 frame, the XRT86L34 framer will declare receive bipolar violation by doing the following: ? set the receive bipolar violation bit of the alarm and error status register to one indicating there are one or more bipolar violations. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 5 receive yellow alarm state r 0 - there is no yellow alarm condition detected in the incoming ds1 payload data. 1 - there is yellow alarm condition detected in the incoming ds1 payload data. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 3 receive bipolar vio- lation interrupt enable r/w 0 - the receive bipolar violation interrupt is disabled. occurrence of one or more bipolar violations will not generate an interrupt. 1 - the receive bipolar violation interrupt is enabled. occurrence of one or more bipolar violations will generate an interrupt. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 409 the table below shows the receive bipolar violation status bits of the alarm and error status register. the table below shows configurations of the alarm and error interrupt enable bit of the block interrupt enable register. when these interrupt enable bits are set and one or more loss of signals are present in the incoming ds1 frame, the XRT86L34 framer will declare receive loss of signal by doing the following: ? set the receive loss of signal bit of the alarm and error status register to one indicating there is one or more loss of signals. this status indicator is valid until the framer interrupt status register is read. reading this register clears the associated interrupt if reset-upon-read is selected in interrupt control regis- ter (icr). otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica- tors. the table below shows the receive loss of signal status bits of the alarm and error status register. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 3 receive bipolar vio- lation state change rur / wc 0 - there is no change of bipolar violation state in the incoming ds1 payload data. 1 - there is change of bipolar violation state in the incoming ds1 payload data. alarm and error interrupt enable register (aeier) (address = 0xnb03h) b it n umber b it n ame b it t ype b it d escription 4 receive loss of sig- nal interrupt enable r/w 0 - the receive loss of signal interrupt is disabled. occurrence of loss of sig- nals will not generate an interrupt. 1 - the receive loss of signal interrupt is enabled. occurrence of loss of signals will generate an interrupt. block interrupt enable register (bier) (address = 0xnb01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and error interrupt status register (aeisr) is disabled. 1 - every interrupt generated by the alarm and error interrupt status register (aeisr) is enabled. alarm and error status register (aesr) (address = 0xnb02h) b it n umber b it n ame b it t ype b it d escription 4 receive loss of sig- nal state rur / wc 0 - there is no change of loss of signal state in the incoming ds1 payload data. 1 - there is change of loss of signal state in the incoming ds1 payload data.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 410 11.0 performance monitoring (pmon) the function of performance monitoring is designed to accumulate error events like line code (bipolar) viola- tions, parity errors, frame alignment errors, etc. using saturating counters. when an accumulation interval is signaled by a one-second interrupt (if enabled), the current counter value can be accessed by the micropro- cessor. after a read by the microprocessor, the counters are reset and begin accumulating error events for the next interval. the counters are reset in such a manner that error events during the reset period are not missed. 11.1 r eceive l ine c ode v iloation c ounter (16-b it ) a line code violation is any event of pulses that does not comply with b8zs or hdb3 encoding standards. line code violations and bi-polar violations cause the lcv counter to increment if this feature is enabled. the msb is stored in register 0xn900h and the lsb is stored in register 0xn901h. 11.2 16-b it r eceive f rame a lignment e rror c ounter (16-b it ) a framing bit error event is defined as a error pattern found in fas or bit 2 of the non-fas. this counter is dis- abled during loss of frame synchronization conditions. it is not disabled during loss of synchronization at either the cas or crc-4 multiframe stage. the msb is stored in register 0xn902h and the lsb is stored in register 0xn903h. 11.3 r eceive s everely e rrored f rame c ounter (8-b it ) a severely errored frame event is defined as the occurrence of two consecutive errored frame alignment sig- nals that are not responsible for loss of frame alignment. the contents of this register are stored in 0xn904h. 11.4 r eceive crc-6/4 b lock e rror c ounter (16-b it ) a synchronization bit error event is defined as a crc-6/4 error received. the counter is disabled during loss of sync at either the frame/fas or esf/crc4 level, but it will not be disabled if loss of multiframe sync occurs at the cas level. the msb is stored in register 0xn905h and the lsb is stored in register 0xn906h. 11.5 r eceive f ar -e nd b lock e rror c ounter (16-b it ) 11.6 r eceive s lip c ounter (8-b it ) a slip event is defined as a replication or deleton of a t1/e1 frame by the receiving slip buffer. the contents of this register are stored in 0xn909h. 11.7 r eceive l oss of f rame c ounter (8-b it ) a lofc is a count of the number of times a loss of fas frame has been declared. this parameter provides the capability to measure an accumulation of short failure events. the contents of this register are stored in 0xn90ah. 11.8 r eceive c hange of f rame a lignment c ounter (8-b it ) a cofa is declared when the newly-locked framing is different from the one offered by off-line framer. the contents of this register are stored in 0xn90bh. 11.9 f rame c heck s equence e rror c ounters 1, 2, and 3 (8-b it e ach ) these counters accumulate the times of occurrence the receive frame check sequence error is detected by the lapd controllers. the contents forlapd 1 are stored in register 0xn90ch. the contents for lapd 2 are stored in register 0xn91ch. the contents for lapd 3 are stored in register 0xn92ch. 11.10 prbs e rror c ounter (16-b it ) this counter contains the 16-bit prbs bit error event. the msb is stored in register 0xn90dh and the lsb is stored in register 0xn90eh. 11.11 t ransmit s lip c ounter (8-b it ) a slip event is defined as a replication or deletion of a t1/e1 frame by the transmit slip buffer. the contents of this register are stored in 0xn90fh.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 411 11.12 e xcessive z ero v iolation c ounter (16-b it ) this register contains the accumulation of the events in which excessive zeros have occured. this is defined as more than 3-bit for hdb3, more than 7-bits for b8zs, and more than 15-bits for ami. the msb is stored in register 0xn910h and the lsb is stored in register 0xn911h.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 412
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 413 12.0 appendix a: ds-1/e1 framing formats 12.1 t he e1 f raming s tructure a single e1 frame consists of 256 bits which is created 8000 times a second; thereby yielding a bit-rate of 2.048mbps. the 256 bits within each e1 frame is grouped into 32 octets or timeslots. these timeslots are num- bered from 0 to 31. figure 128 presents a diagram of a single e1 frame. a single e1 frame consists of 32 timeslots. however, not all of these timeslots are available to transmit voice or user data. for instance, timeslot 0 is always reserved for system use and timeslot 16 is sometimes used (reserved) by the system. hence, within each e1 frame, either 30 or 31 of the 32 timeslots are available for transporting user or voice data. t imeslot 0 in general, there are two types of e1 frames. ? fas (frame alignment signaling) frames ? non-fas frames in any e1 data stream, the e1 frame type alternates between the fas and non-fas frames. the timeslot 0 octet within the fas e1 frame contains a framing alignment pattern and therefore supports framing. the timeslot 0 octet within the non-fas e1 frame contains bits that support signaling or data link mes- sage transmission. t imeslot 0 octets within fas frames the bit-format of a timeslot 0 octet within a fas frame is presented in table 184. the table above indicates that the fas frame timeslot 0 octet consists of a single international bit within bit- field 0, si, followed by a fixed 7-bit pattern within bit-fields 1 through 7. f igure 128. s ingle e1 f rame d iagram t able 184: b it f ormat of t imeslot 0 octet within a fas e1 f rame b it 0 1234567 value si 0011011 function international bit frame alignment signaling (fas) pattern d escription - o peration in practice, the si bit within the fas e1 frame carries the results of a crc-4 calculation, which is discussed in greater detail in section 12.2.1. the fixed framing pattern (e.g., 0, 0, 1, 1, 0, 1, 1) is used by the receive e1 framer at the remote terminal for frame synchronization/alignment purposes. timeslot 0 timeslot 1 timeslot 29 0 1 2 3 4 5 6 7 timeslot 30 timeslot 31 e1 frame
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 414 b it 0s i (i nternational b it ) the si bit within the fas e1 frame typically carries the results of a crc-4 calculation, which is discussed in greater detail in section 12.2.1. the fixed framing pattern (e.g., 0, 0, 1, 1, 0, 1, 1) will be used by the receive e1 framer at the remote terminal for frame synchronization/alignment purposes. section 7.0 discusses how the receive e1 framer uses these bits. timeslot 0 octets within non-fas frames the bit-format of a timeslot 0 octet within a non-fas frame is presented in table 185. the table above indicates the non-fas frame timeslot 0 octet consists of a single international bit, si, within bit- field 0. b it 0s i (i nternational b it ) the si bit, within the non-fas e1 frame carries a specific value that will be used by the receive e1 framer, for crc multi-frame alignment purposes. section 7 discusses the exact role of the si bit-field within the non-fas frames. b it 1f ixed at 1 bit-field 1 contains a fixed value 1. this bit-field will be used for fas framing synchronization/alignment pur- poses by the remote receive e1 framer. section _ discusses how the receive e1 framer uses this bit-field. b it 2a (fas f rame y ellow a larm b it ) this bit-field is used to transmit a yellow alarm to the remote terminal. this bit-field is set to 0 during normal conditions, and is set to 1 whenever the receive e1 framer detects an los (loss of signal) or lof (loss of framing) condition in the incoming e1 frame data. b it 3 through 7s a 4Cs a 8 (n ational b its ) these bit-fields can be used to carry data link information from the local transmitting terminal to the remote receiving terminal. since the national bits only exist in the non-fas frames, they offer a maximum signaling data link bandwidth of 20kbps. 12.2 t he e1 m ulti - frame s tructure the 86l34 octal framer supports two kinds of e1 multi-frame structures: ? crc multi-frame ? cas multi-frame 12.2.1 the crc multi-frame structure a crc multi-frame consists of 16 consecutive e1 frames, with the first of these frames being a fas frame. from a frame alignment point of view, the timeslot 0 octets of each of these e1 frames within the multi-frame are the most important 16 octets. table 186 presents the bit-format for all timeslot 0 octets within a 16 frame crc multi-frame. t able 185: b it f ormat of t imeslot 0 octet within a n on -fas e1 f rame b it 76543 2 1 0 value sa8 sa7 sa6 sa5 sa4 a 1 si function6 national bits yellow alarm fixed value international bit description- operation national bits these bit-fields can be used to carry data link information from the local transmitting terminal to the remote receiving termi- nal. since the national bits only exist in the non-fas frames, they offer a maximum signaling data link bandwidth of 20kbps. fas frame yellow alarm bit this bit-field is used to transmit a yellow alarm to the remote termi- nal. this bit-field is set to 0 dur- ing normal conditions, and is set to 1 whenever the receive e1 framer detects an los (loss of signal) or lof (loss of framing) condition in the incoming e1 frame data. fixed at 1 bit-field 1 contains a fixed value 1. this bit-field will be used for fas framing syn- chronization/alignment pur- poses by the remote receive e1 framer. international bit the si bit within the non-fas e1 frame typically carries a specific value that will be used by the receive e1 framer for crc multi-frame alignment purposes.
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 415 table 186 has the crc multi-frame divided into 2 sub multi-frames. sub-multi-frame 1 is designated as smf1 and sub-multi-frame 2 is designated as smf2. smf1 consists of e1 frames 0 through 7 consisting of 4 fas frames and 4 non-fas frames. there are two interesting things to note in table 186. first, all of the bit-field 0 positions within each of the fas frames are designated as c1, c2, c3 and c4. these four bit-fields contain the crc-4 values which has been computed over the previous smf. hence, while the transmit e1 framer is assembling a given smf, it com- putes the crc-4 value for that smf and inserts these results into the c1 through c4 bit-fields within the very next smf. these crc-4 values ultimately are used by the remote receive e3 framer for error-detection pur- poses. n ote : this framing structure is referred to as a crc multi-frame because it permits the remote receiving terminal to locate and verify the crc-4 bit-fields. the second interesting thing to note regarding table 186 is that the bit-field 0 positions within each of the non- fas frames are of a fixed six (6) bit pattern: 0, 0, 1, 0, 1, 1; along with two bits, each designated at e. this six bit pattern is referred to as the crc multi-frame alignment pattern. this six-bit pattern will ultimately be used by the remote receive e1 framer for crc multi-frame synchronization/alignment. section 7.0 discusses how the receive e1 framer uses this 6-bit crc multi-frame alignment pattern for frame synchronization/align- ment. the "e" bits are used to indicate that the local receive e1 framer has detected errored sub-multi- frames. 12.2.2 cas multi-frames and channel associated signaling cas multi-frames are only relevant if the user is using cas or channel associated signaling. if the user is im- plementing common channel signaling then the cas multi-frame is not available. the exact role of cas multi-frames is discussed in some detail in section 7.0, channel associated signaling. 12.2.2.1 channel associated signaling if the user operates an e1 channel in channel associated signaling (cas) mode, then the timeslot 16 octets within each e1 frame will be reserved for signaling. such signaling would convey information such as on- t able 186: b it f ormat of all t imeslot 0 octets within a crc m ulti - frame smf f rame n umber b it 0b it 1b it 2b it 3b it 4b it 5b it 6b it 7 1 0 c1 0 0 1 1 0 1 1 1 0 1 a sa4 sa5 sa6 sa7 sa8 2 c2 0 0 1 1 0 1 1 3 0 1 a sa4 sa5 sa6 sa7 sa8 4 c3 0 0 1 1 0 1 1 5 1 1 a sa4 sa5 sa6 sa7 sa8 6 c4 0 0 1 1 0 1 1 7 0 1 a sa4 sa5 sa6 sa7 sa8 2 8 c1 0 0 1 1 0 1 1 9 1 1 a sa4 sa5 sa6 sa7 sa8 10 c2 0 0 1 1 0 1 1 11 1 1 a sa4 sa5 sa6 sa7 sa8 12 c3 0 0 1 1 0 1 1 13 e 1 a sa4 sa5 sa6 sa7 sa8 14 c4 0 0 1 1 0 1 1 15 e 1 a sa4 sa5 sa6 sa7 sa8
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 416 hook, off-hook conditions, call set-up, control, etc. in cas, this type of signaling data that is associated with a particular voice channel will be carried within timeslot 16 of a particular e1 frame within a cas multi-frame. the cas is carried in a multi-frame structure which consists of 16 consecutive e1 frames. the framing/byte format of a cas multi-frame is presented in figure 129. figure 129 indicates that timeslot 16 within frame 1 of the cas multi-frame, contains 4 bits of signaling data for voice channel 1 and 4 bits of signaling data for voice channel 17. likewise, timeslot 16 within frame 2 con- tains 4 bits of signaling data for voice channel 2 and 4 bits of signaling data for voice channel 18; and so on. timeslot 16 within frame 0 is a special octet that is used for two purposes. 1. to convey cas multi-frame alignment information, and 2. to convey multi-frame alarm information to the remote terminal. the bit-format of timeslot 16 within frame 0 of a cas multi-frame is 0000 xyxx. the upper nibble of this octet contains all zeros and is used to identify itself as the cas multi-frame alignment signal. if cas is used, then the user is advised to insure that none of the other timeslot 16 octets contain the value "0000". the lower nibble of this octet contains the expression "xyxx". in this case, the x-bits are the spare bits and should be set to "0" if not used. the y-bit is used to indicate a multi-frame alarm condition to the re- mote terminal. during normal operation, this bit-field is cleared to "0". however, if the local receive e1 framer detects a problem with the incoming multi-frames, then the local transmit e1 framer will set this bit-field with- in the next outbound cas multi-frame to "1". n ote : the local transmit e1 framer will continue to set the y-bit to "1" for the duration that the local receive e1 framer detects this problem. 12.2.2.2 common channel signaling (ccs) common channel signaling is an alternative form of signaling from channel associated signaling. in ccs, whatever signaling data which is transported via the outbound e1 data stream, carries information that applies f igure 129. f rame /b yte f ormat of the cas m ulti -f rame s tructure frame 0 frame 1 frame 2 frame 15 0000 xyxx timeslot 16 timeslot 16 timeslot 16 timeslot 16 abcd abcd signaling data associated with timeslot 1 signaling data associated with timeslot 17 abcd abcd abcd abcd cas multiframe alignment pattern x = dummy bits y = carries the multiframe yellow alarm bit signaling data associated with timeslot 2 signaling data associated with timeslot 18 signaling data associated with timeslot 15 signaling data associated with timeslot 31 a single cas multiframe
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 417 to all of the voice channels as a set (e.g., timeslots 1 through 15 and 17 through 31) in the e1 frame. there are numerous other variations of common channel signaling that are available. some of these are listed below. ? 31 voice channels with the common channel signaling being transported via the national bits. ? 30 voice channels with the common channel signaling data being transported via the national bits and cas data being transported via timeslot 16. ? 30 voice channels with the common channel signaling being processed via timeslot 16. (e.g., primary rate isdn signaling). a more detailed discussion of these forms of common channel signaling are discussed in section 11.0. 12.3 t he ds1 f raming s tructure a single t1 frame is 193 bits long and is transmitted at a frame rate of 8000hz. this results in an aggregate bit rate of 193 bits x 8000/sec = 1.544 mbits/sec. basic frames are divided into 24 timeslots numbered 1 thru 24 and a framing bit, see figure 131. each timeslot is 8 bits in length and is transmitted most significant bit first, numbered bit 0. this results in a single timeslot data rate of 8 bits x 8000/sec = 64 kbits/sec. f igure 130. e1 f rame f ormat fr 0 fr 1 fr 2 fr 3 fr 4 fr 5 fr 6 fr 15 fr 14 fr 13 fr 12 fr 11 fr 10 fr 9 fr 8 fr 7 1 n n n n n a 1 a d c b a d c b 1 8 7 6 5 4 3 2 1 1 1 0 1 1 0 0 0 x x y x 0 0 0 ts 0 ts 1 ts 2 ts 15 ts 31 ts 30 ts 29 ts 18 - 28 ts 17 ts 16 ts 3 - 14 fas mas time slot 16 time slot 0 time slots 1-15, 17-31 channel data b. frames 1-15 b. odd frames 1, 3, 5-15 a. even frames 0, 2, 4-14 a. frame 0 8 bits/ time slot 32 time slots/frame 16 frames/ multiframe
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 418 12.4 t1 s uper f rame f ormat (sf) the superframe format (sf), is also referred to as the d4 format. the requirement for associated signaling in frames 6 and 12 dictates that the frames be distinguishable. this leads to a multiframe structure consisting of 12 frames per superframe (sf). see figure 132 and table 187. the sf structure consists of a multiframe of 12 frames. each frame has 24 timeslots, plus an f-bit and 8 bits per timeslot. a timeslot is equivalent to one voice circuit or one 64kb/s data circuit. this structure of frames and multiframes is defined by the f-bit pattern. the f-bit is designated alternately as an ft bit (terminal framing bit) or fs bit (signalling framing bit). the ft bit carries a pattern of alternating zeros and ones (101010) in odd frames that defines the boundaries so that one timeslot may be distinguished from another. the fs bit carries a pattern of (001110) in even frames and defines the multiframe boundaries so that one frame may be distinguished from another. f igure 131. t1 f rame f ormat 125 m s ds1 frame (8/1.544) m s bit 0 bit 0 bit 1 bit 1 bit 2 bit 2 bit 3 bit 3 bit 4 bit 4 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 timeslot 24 s bit timeslots 2 - 22 s bit timeslot 23 timeslot 24 timeslot 1 timeslot 1 (1/1.544) m s
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 419 f igure 132. t1 s uperframe pcm f ormat t able 187: s uperframe f ormat f rame b it f-b its b it u se in e ach t imeslot s ignalling c hannel t erminal f raming f t t erminal f raming f s t raffic s ig 1 0 1 ---- 1-8 ---- ---- 2 193 ---- 0 1-8 ---- ---- 3 386 0 ---- 1-8 ---- ---- 4 579 ---- 0 1-8 ---- ---- 5 772 1 ---- 1-8 ---- ---- 6 965 ---- 1 1-7 8 a 7 1158 0 ---- 1-8 ---- ---- 8 1351 ---- 1 1-8 ---- ---- 9 1544 1 ---- 1-8 ---- ---- 10 1737 ---- 1 1-8 ---- ---- 11 1930 0 ---- 1-8 ---- ---- 12 2123 ---- 0 1-7 8 b b a bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 8 bits per timeslot ft or fs ft or fs ts 1 ts 1 ts 2 ts 2 ------------------ ------------------ ts 13 ts 13 ------------------- ------------------- ts 24 ts 24 fr 1 fr 1 fr 2 fr 2 ------------------ ------------------ fr 7 fr 7 ------------------- ------------------- fr 11 fr 11 fr 12 fr 12 signalling information bit 7 during: frame 12 frame 6 24 timeslots per frame frame = 193 bits multiframe sf = 12 frames
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 420 12.5 t1 e xtended s uperframe f ormat (esf) in extended superframe format (esf), as shown in figure 133 and table 188, the multiframe structure is ex- tended to 24 frames. the timeslot structure is identical to d4 (sf) format. robbed-bit signaling is accommo- dated in frame 6 (a-bit), frame 12 (b-bit), frame 18 (c-bit) and frame 24 (d-bit). the f-bit pattern of esf contains three functions: 1. framing pattern sequence (fps), which defines the frame and multiframe boundaries. 2. facility data link (fdl), which allows data such as error-performance to be passed within the t1 link. 3. cyclic redundancy check (crc), which allows error performance to be monitored and enhances the reli- ability of the receivers framing algorithm. f igure 133. t1 e xtended s uperframe f ormat d c crc crc fd l fd l b a bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 8 bits per timeslot fp s o r f s fps or fs ts 1 ts 1 ts 2 ts 2 ----------------- - ----------------- - ts 13 ts 13 ------------------ - ------------------ - ts 24 ts 24 fr 1 fr 1 fr 2 fr 2 ----------------- - ----------------- - fr 13 fr 13 ------------------ - ------------------ - fr 23 fr 23 fr 24 fr 24 signalling information bit 7 during: frame 24 frame 18 frame 12 frame 6 24 timeslots per frame frame = 193 bits multiframe esf = 24 frames
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 421 t able 188: e xtended s uperframe f ormat f rame b it f-b its b it u se in e ach t imeslot s ignalling c hannel fps dl crc t raffic s ig 16 4 2 1 0 ---- m ---- 1-8 ---- ---- ---- ---- 2 193 ---- ---- c1 1-8 ---- ---- ---- ---- 3 386 ---- m ---- 1-8 ---- ---- ---- ---- 4 579 0 ---- ---- 1-8 ---- ---- ---- ---- 5 772 ---- m ---- 1-8 ---- ---- ---- ---- 6 965 ---- ---- c2 1-7 8 a a a 7 1158 ---- m ---- 1-8 ---- ---- ---- ---- 8 1351 0 ---- ---- 1-8 ---- ---- ---- ---- 9 1544 ---- m ---- 1-8 ---- ---- ---- ---- 10 1737 ---- ---- c3 1-8 ---- ---- ---- ---- 11 1930 ---- m ---- 1-8 ---- ---- ---- ---- 12 2123 1 ---- ---- 1-7 8 b b b 13 2316 ---- m ---- 1-8 ---- ---- ---- ---- 14 2509 ---- ---- c4 1-8 ---- ---- ---- ---- 15 2702 ---- m ---- 1-8 ---- ---- ---- ---- 16 2895 0 ---- ---- 1-8 ---- ---- ---- ---- 17 3088 ---- m ---- 1-8 ---- ---- ---- ---- 18 3281 ---- ---- c5 1-7 8 c c a 19 3474 ---- m ---- 1-8 ---- ---- ---- ---- 20 3667 1 ---- ---- 1-8 ---- ---- ---- ---- 21 3860 ---- m ---- 1-8 ---- ---- ---- ---- 22 4053 ---- ---- c6 1-8 ---- ---- ---- ---- 23 4246 ---- m ---- 1-8 ---- ---- ---- ---- 24 4439 1 ---- ---- 1-7 8 d b a n otes : 1. fps indicates the framing pattern sequence (...001011...) 2. dl indicates the 4kb/s data link with message bits m. 3. crc indicates the cyclic redundancy check with bits c1 to c6 4. signaling options include 16 state, 4 state and 2 state.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 422 12.6 t1 d ata m ultiplexed f raming f ormat (t1dm) t1dm uses a similar framing structure as the sf (d4), such that the fs and ft bits on the individual frame boundaries remain the same. the differentiation between t1dm and sf is within the payload time slots. time slot 24 cannot be used for data when configured for t1dm. time slot 24 is dedicated for a special synchroni- zation byte as shown in figure 134. the y-bit is to carry the status of the yellow alarm. the r-bit is dedicated for a remote signaling bit typically not used. however, the framer allows this bit to carry an hdlc message. time slots 1 through 23 are used to carry the seven bit word from each of the 23 ds-0 signals. f igure 134. t1dm f rame f ormat f time slot 1 time slots 2 through 23 time slot 24 bit 1 bit 2 bit 3 bit 4 bit 6 bit 7 c bit 5 1 0 1 1 y r 0 1 12 t1dm frames per multi-frame t1dm frame
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 423 12.7 slc-96 f ormat (slc-96) slc framing mode allows synchronization to the slc?96 data link pattern. this pattern described in bellcore tr-tsy-000008, contains both signaling information and a framing pattern that overwrites the fs bit of the sf framer pattern. see table 189. t able 189: slc ? 96 f s b it c ontents f rame #fs b it f rame #fs b it f rame #fs b it 2 0 26 c2 50 0 4 0 28 c3 52 m1 6 1 30 c4 54 m2 8 1 32 c5 56 m3 10 1 34 c6 58 a1 12 0 36 c7 60 a2 14 0 38 c8 62 s1 16 0 40 c9 64 s2 18 1 42 c10 66 s3 20 1 44 c11 68 s4 221460701 24 c1 48 1 72 0 n otes : 1. the slc ? 96 frame format is similar to that of sf as shown in table 187 with the exceptions shown in this table. 2. c1 to c11 are concentrator bit fields. 3. m1 to m3 are maintenance bit fields. 4. a1 and a2 are alarm bit fields. 5. s1 to s4 are line switch bit fields. 6. the fs bits in frames 46, 48 and 70 are spoiler bitswhich are used to protect against false mutiframing.
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 424 electrical characteristics (framer block) absolute maximums power supply......................................... - 0.5v to +3.465v power dissipation tbga package........................... tbd storage temperature ...............................-65c to 150c input logic signal voltage (any pin) .........-0.5v to + 5.5v operating temperature range.................-40c to 85c esd protection (hbm)...........................................>2000v supply voltage ...................... gnd-0.5v to +vdd + 0.5v input current (any pin) ...................................... + 100ma dc electrical characteristics test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions i dd power supply current tbd ma all channels on i ll data bus tri-state bus leakage current -10 +10 a v il input low voltage 0.8 v v ih input high voltage 2.0 vdd v v ol output low voltage 0.0 0.4 v i ol = -1.6ma v oh output high voltage 2.4 vdd v i oh = 40a i oc open drain output leakage current a i ih input high voltage current -10 10 a v ih = vdd i il input low voltage current -10 10 a v il = gnd
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 425 electrical characteristics t able 190: xrt83l38 p ower c onsumption vdd=3.3v5%, t a =25c, unless otherwise specified m ode s upply v oltage i mpedance termination r esistor t ransformer r atio t yp .m ax .u nit t est c onditions r eceiver t ransmitter e1 3.3v 75 w internal 1:1 1:2 tbd tbd mw mw 50% 1s 100% 1s e1 3.3v 120 w internal 1:1 1:2 tbd tbd mw mw 50% 1s 100% 1s t1 3.3v 100 w internal 1:1 1:2 tbd tbd mw mw 50% 1s 100% 1s --- 3.3v --- --- --- --- tbd mw all transmitters and receivers off
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 426 t able 191: e1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos de-asserted 15 12.5 32 20 db % ones cable attenuation @1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w applica- tion. with -18db interference signal added. receiver sensitivity (long haul with cable loss) 0 43 db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w applica- tion. with -18db interference signal added. input impedance 13 k w input jitter tolerance: 1 hz 10khz-100khz 37 0.2 uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude -36 -0.5 khz db itu g.736 jitter attenuator corner fre- quency (-3db curve) (jabw=0) (jabw=1) -10 1.5 -hz hz itu g.736 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 14 20 16 --db db db itu-g.703
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 427 t able 192: t1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos clear 160 15 12.5 175 20 - 190 - - db % ones cable attenuation @772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - db with nominal pulse amplitude of 3.0v for 100 w termination receiver sensitivity (long haul with cable loss) normal extended 0 0 - 36 45 db db with nominal pulse amplitude of 3.0v for 100 w termination input impedance 13 - k w jitter tolerance: 1hz 10khz - 100khz 138 0.4 - - - - uipp at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 9.8 - 0.1 khz db tr-tsy-000499 jitter attenuator corner fre- quency (-3db curve) - 6 -hz at&t pub 62411 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 20 25 25 - - - db db db t able 193: e1 t ransmit r eturn l oss r equirement f requency r eturn l oss g.703/ch-ptt ets 300166 51-102khz 8db 6db 102-2048khz 14db 8db 2048-3072khz 10db 8db
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 428 t able 194: e1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in .t yp .m ax .u nit t est c onditions ami output pulse amplitude: 75 w application 120 w application 2.13 2.70 2.37 3.00 2.60 3.30 v v transformer with 1:2 ratio and 9.1 w resistor in series with each end of pri- mary. output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703 jitter added by the transmitter out- put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz 8 14 10 - - - - - - db db db etsi 300 166, chptt t able 195: t1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in .t yp .m ax .u nit t est c onditions ami output pulse amplitude: 2.4 3.0 3.60 v use transformer with 1:2.45 ratio and measured at dsx-1 output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 - ansi t1.102 output pulse amplitude imbalance --+ 200 mv ansi t1.102 jitter added by the transmitter out- put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 15 15 15 - - - db db db
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 429 f igure 135. itu g.703 p ulse t emplate t able 196: t ransmit p ulse m ask s pecification test load impedance 75 w resistive (coax) 120 w resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 + 0.237v 0 + 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244 C50) 244 ns 219 ns (244 C 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note C v corresponds to the nominal peak value. 20% 20%
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 430 f igure 136. dsx-1 p ulse t emplate ( normalized amplitude ) t able 197: dsx1 i nterface i solated pulse mask and corner points m inimum curve m aximum curve t ime (ui) n ormalized amplitude t ime (ui) n ormalized amplitude -0.77 -.05v -0.77 .05v -0.23 -.05v -0.39 .05v -0.23 0.5v -0.27 .8v -0.15 0.95v -0.27 1.15v 0.0 0.95v -0.12 1.15v 0.15 0.9v 0.0 1.05v 0.23 0.5v 0.27 1.05v 0.23 -0.45v 0.35 -0.07v 0.46 -0.45v 0.93 0.05v 0.66 -0.2v 1.16 0.05v 0.93 -0.05v 1.16 -0.05v
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 431 t able 198: ac e lectrical c haracteristics vdd=3.3v5%, t a =25c, unless otherwise specified p arameter s ymbol m in .t yp .m ax .u nits e1 mclk clock frequency - 2.048 mhz t1 mclk clock frequency - 1.544 mhz mclk clock duty cycle 40 - 60 % mclk clock tolerance - 50 - ppm
XRT86L34 quad t1/e1/j1 framer/liu combo rev. p1.0.2 preliminary 432 ordering information package dimensions p roduct n umber p ackage o perating t emperature r ange XRT86L34ib 225 lead tbga -40 0 c to +85 0 c 225 ball plastic ball grid array (19.0 mm x 19.0 mm, 1.0mm pitch pbga) rev. 1.00 symbol min max min max a 0.049 0.096 1.24 2.45 a1 0.016 0.024 0.40 0.60 a2 0.013 0.024 0.32 0.60 a3 0.020 0.048 0.52 1.22 d 0.740 0.756 18.80 19.20 d1 0.669 bsc 17.00 bsc d2 0.665 0.669 16.90 17.00 b 0.020 0.028 0.50 0.70 e 0.039 bsc 1.00 bsc inches millimeters note: the control dimension is in millimeter. 1 2 4 3 7 86 5 1 7 1 6 1 4 1 5 1 2 1 3 1 1 1 0 9 1 8 a b c d e f g h j k l m n p r t u v d d1 d d1 a1 feature / mark d2 a a 1 a 2 a 3 e b (a1 corner feature is mfger option) seating plane
XRT86L34 quad t1/e1/j1 framer/liu combo preliminary rev. p1.0.2 433 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2001 exar corporation datasheet october 2003. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r evision #d ate d escription p1.0.0 07/07/03 first release of the 4-channel framer/liu preliminary datasheet. p1.0.1 07/15/03 changed address registers (0xn024-0xn027) to (0xn124-0xn127) in the register descriptions. p1.0.2 10/31/03 re-arranged the datasheet and altered the table of contents. added registers for additional hdlc controllers, ss7, automatic performance report, gapped clock interface, ais-ci, and rai-ci. cleaned up diagrams.

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